DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Pub.No.: US 2015/0270952 A1 to SETHUMADHAVAN et al(hereafter referenced as SETH) in view of Patent No.: US 7,319,345 B2 to Farjad-et-al(hereafter referenced as Farjad).
Regarding claim 1, SETH discloses “a method for obfuscating analog switched phase circuits(method to disable all of these types of triggers by obfuscating or scrambling inputs Supplied to the hardware units in order to prevent those units from recognizing triggers [par.0028]) , the method comprising :generating a first input signal to an analog circuit (generating random value y [Fig.5/item 505]).
SETH does not explicitly disclose “the first input signal comprising a reference phase”, the analog circuit adapted to perform a predetermined function; generating a second input signal to the analog circuit, the second input signal comprising a provided phase; and toggling enablement of the predetermined function of the analog circuit based on alignment of the reference phase and the provided phase.”
However, Farjad in an analogous art discloses “the first input signal comprising a reference phase”(Farjad [FIG. 28] illustrates an exemplary clock generator including a reference phase generator), “the analog circuit adapted to perform a predetermined function” (clock divider comprising re-timing circuits Farjad[Col.3/lines 8-13]); generating a second input signal to the analog circuit, the second input signal comprising a provided phase; and toggling enablement of the predetermined function of the analog circuit based on alignment of the reference phase and the provided phase.”(Farjad[Fig.27] discloses a clock divider that outputs primary and secondary phase vectors at a selected subdivided frequency).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify SETH’s Obfuscation process in a circuit with Farjad’s Multi phase clock generation in order to provide additional security. One of ordinary skill would have been motivated to combined because SETH teaches an obfuscation process in a circuit comprising a clock signal, Farjad discloses multiphase clock generation during signaling, and both are from the same field of endeavor.
Regarding claim 2 in view of claim 1, the references combined disclose “wherein generating the first input signal comprises generating the first input signal by applying an output of a key space function to a clock signal.” (generate input signal SETH[Fig.1]).
Regarding claim 3 in view of claim 2, the references combined disclose “wherein the key space function is a physically unclonable function (PUF).”(encryption schemes at the on-chip inter-unit level require the efficient generation of truly random bits. This can be done realistically due to recent innovations in the design of physical unclonable functions (PUFs) SETH[par.0098]).
Regarding claim 4 in view of claim 2, the references combined disclose “wherein the output of the key space function is a first key”(using a hardware random number generator or a PUF, a random and secure key can be generated that only needs to be used and stored for a short time SETH[par.0082])
Regarding claim 5 in view of claim 2, the references combined disclose “wherein the first input signal is output from a shift register adapted to receive the clock signal and the output of the key space function”(re-timers 831b may additionally receive the undivided differential clock signals at their second clock inputs Farjad[Col.36/lines 54-56]).
Regarding claim 6 in view of claim 1, the references combined disclose “wherein generating the second input signal comprises generating the second input signal by applying a second key to a clock signal” (re-timers 831b may additionally receive the undivided differential clock signals at their second clock inputs Farjad[Col.36/lines 54-56]).
Regarding claim 7 in view of claim 6, the references combined disclose “wherein the second input signal is output from a shift register adapted to receive the clock signal and the second key” (re-timers 831b may additionally receive the undivided differential clock signals at their second clock inputs Farjad[Col.36/lines 54-56]).
Regarding claim 8 in view of claim 6, the references combined disclose “wherein the second key is a user input key”(random secure key SETH[par.0082]).
Regarding claim 9 in view of claim 1, the references combined disclose “wherein toggling the enablement of the predetermined function of the analog circuit comprises disabling the predetermined function of the analog circuit when the reference phase and the provided phase are misaligned” (divide-flop 701b is disabled and, when Div8 is high (and Div4or8 is high), divide-flop 701b outputs an in-phase differential clock signal having frequency F/4 to a second input of multiplexer 721 [Col.30/lines 62-66]).
Regarding claim 10 in view of claim 9, the references combined disclose “wherein disabling the predetermined function comprises producing a short-circuit or an open-circuit in the analog circuit” (when the TC0 is low, inverters 623 are tri-stated to set latch element 621 to a tri-state condition (i.e., appearing as an open circuit between the outputs of driver inverters 590) and therefore contributes negligible resistance to change in state when the differential input signal transitions from one state to another Farjad [Col.27/lines 20-25]).
Regarding claim 11 in view of claim 10, the references combined disclose “further comprising: sensing the short-circuit or the open-circuit in the analog circuit; and determining an occurrence of an adversarial attack based on the short-circuit or the open-circuit” (data obfuscation SETH[Fig.1]).
Regarding claim 12 in view of claim 1, the references combined disclose “wherein toggling the enablement of the predetermined function of the analog circuit comprises enabling the predetermined function of the analog circuit when the reference phase and the provided phase are aligned” (Farjad[Fig.27] discloses a clock divider that outputs primary and secondary phase vectors at a selected subdivided frequency).
Regarding claim 13, SETH discloses “a system for obfuscating analog switched phase circuits(method to disable all of these types of triggers by obfuscating or scrambling inputs Supplied to the hardware units in order to prevent those units from recognizing triggers [par.0028]), the system comprising: key space function circuit adapted to generate a first key”(generating random value y [Fig.5/item 505]).; “a key loading unit adapted to receive a second key” (random and secure key can be generated that only needs to be used and stored for a short time SETH[par.0082]) “receive the first key from the key space function circuit, and apply the first key to the clock signal to generate a first input signal to an analog circuit” (using a hardware random number generator or a PUF, a random and secure key can be generated that only needs to be used and stored for a short time SETH[par.0082]),
SETH does not explicitly disclose “a first shift register adapted to: receive a clock signal, the first input signal comprising a reference phase, and the analog circuit adapted to perform a predetermined function; and a second shift register adapted to: receive the clock signal, receive the second key from the key loading unit, and apply the second key to the clock signal generate a second input signal to the analog circuit, the second input signal comprising a provided phase; wherein enablement of the predetermined function of the analog circuit is toggled based on alignment of the reference phase and the provided phase.”
However, Farjad in an analogous art discloses “a first shift register adapted to: receive a clock signal” (clock divider comprising re-timing circuits Farjad[Col.3/lines 8-13]), the first input signal comprising a reference phase, and the analog circuit adapted to perform a predetermined function(clock divider comprising re-timing circuits Farjad[Col.3/lines 8-13]); “and a second shift register adapted to: receive the clock signal, receive the second key from the key loading unit” (re-timers 831b may additionally receive the undivided differential clock signals at their second clock inputs Farjad[Col.36/lines 54-56]), “and apply the second key to the clock signal generate a second input signal to the analog circuit, the second input signal comprising a provided phase; wherein enablement of the predetermined function of the analog circuit is toggled based on alignment of the reference phase and the provided phase.” (Farjad[Fig.27] discloses a clock divider that outputs primary and secondary phase vectors at a selected subdivided frequency).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify SETH’s Obfuscation process in a circuit with Farjad’s Multi phase clock generation in order to provide additional security. One of ordinary skill would have been motivated to combined because SETH teaches an obfuscation process in a circuit comprising a clock signal, Farjad discloses multiphase clock generation during signaling, and both are from the same field of endeavor.
Regarding claim 14 in view of claim 13, the references combined disclose “wherein the key space function circuit is a physically unclonable function (PUF) circuit” (encryption schemes at the on-chip inter-unit level require the efficient generation of truly random bits. This can be done realistically due to recent innovations in the design of physical unclonable functions (PUFs) SETH[par.0098]).
Regarding claim 15 in view of claim 13, the references combined disclose “wherein the second key is a user input key” (random secure key SETH[par.0082]).
Regarding claim 16 in view of claim 13, the references combined disclose “wherein the predetermined function of the analog circuit is disabled when the reference phase and the provided phase are misaligned” (divide-flop 701b is disabled and, when Div8 is high (and Div4or8 is high), divide-flop 701b outputs an in-phase differential clock signal having frequency F/4 to a second input of multiplexer 721 [Col.30/lines 62-66]).
Regarding claim 17 in view of claim 16, the references combined disclose “wherein the predetermined function of the analog circuit is disabled by producing a short-circuit or an open-circuit in the analog circuit”(when the TC0 is low, inverters 623 are tri-stated to set latch element 621 to a tri-state condition (i.e., appearing as an open circuit between the outputs of driver inverters 590) and therefore contributes negligible resistance to change in state when the differential input signal transitions from one state to another Farjad [Col.27/lines 20-25]).
Regarding claim 18 in view of claim 17, the references combined disclose “further comprising sensor circuitry adapted to: sense the short-circuit or the open-circuit in the analog circuit; and determine an occurrence of an adversarial attack based on the short-circuit or the open-circuit” (data obfuscation SETH[Fig.1]).
Regarding claim 19 in view of claim 13, the references combined disclose “wherein the predetermined function of the analog circuit is enabled when the reference phase and the provided phase are aligned” (Farjad[Fig.27] discloses a clock divider that outputs primary and secondary phase vectors at a selected subdivided frequency).
Regarding claim 20 in view of claim 13, the references combined disclose “wherein the analog circuit comprises a chopping amplifier, a switched-capacitor voltage regulator, a bandgap voltage reference circuit, or a DC-DC converter” (the frequency divider circuit 103 includes a set of buffer amplifiers 113 to convert the reference vectors from reduced-swing to complementary-MOS (CMOS) signal levels and provide the resulting level-converted reference phase vectors 117-117s to first inputs of respective multiplexers 121 within the selector circuit 105, thus providing a unity vector set Farjad[Col.5/lines 36-42]).
Conclusion
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/MICHAEL D ANDERSON/ Examiner, Art Unit 2433
/JEFFREY C PWU/ Supervisory Patent Examiner, Art Unit 2433