DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
1. Claim(s) 1, 9, 11, 13-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Baharmast (US 20240178806 A1).
In regard to Claim 1:
Baharmast discloses, in figure 3, an electronic comparator circuit, comprising:
an input portion (Fig 3; VINP & VINN), comprising a first input transistor (Fig 1; 311), comprising a gate connected to a first input voltage input (Fig 3; VINP), and a second input transistor (312), comprising a gate connected to a second voltage input (VINN); an output position (FIG 3; out), arranged to produce an output voltage dependent upon the relative values (Paragraph 0028) of the first voltage input (VINP) and the second voltage input (VINN);
a first portion, comprising a third transistor (332), a fourth transistor (331), and a first current supply (302), connected, connected in series (Fig 3; 332 and 331 connected in series), wherein a first terminal of the first input transistor (311) is connected between a first terminal of the third transistor (332) and a second terminal of the fourth transistor (331), such that the first terminal of the first input transistor (311) and the first terminal of the third transistor (332) are at the same voltage (AVDD), wherein the fourth transistor is connected in a diode configuration (331 gate is connected to its drain);
a second comprising a fifth transistor (337), a sixth transistor (336), and a second current supply (303), connected in series (Fig 3; 337 & 336 connected in series), wherein a first terminal of the second input transistor (312) is connected between a first terminal of the fifth transistor (337) and a second terminal of the sixth transistor (336), such that the first terminal of the second input transistor and the first terminal of the fifth transistor are at the same voltage (AVDD), wherein the sixth transistor (336) is connected in a diode configuration (336 gate is connected to its drain); and
a gain portion, comprising a seventh gain transistor (313) and an eighth gain transistor (337), wherein a gate of the seventh gain transistor (313) is cross-coupled to a gate of the fifth transistor (313).
In regard to Claim 9:
Baharmast further discloses a third current supply (Fig 1; 301), wherein the first input transistor (311) and the second input transistor (312) are connected in parallel to the third current supply (301).
In regard to Claim 11:
Baharmast further discloses wherein the first current supply (I1) and the second current supply (I2) supply approximately the same current (paragraph 120).
In regard to Claim 13:
Baharmast further discloses wherein the first terminals are drain terminals and wherein the second terminals are source terminals (Paragraph 82).
In regard to Claim 14:
Baharmast further discloses wherein at least one of the third transistor (332), the fourth transistor (331), the fifth transistor (337), the sixth transistor (336), the seventh transistor (313), and/or the eighth transistor (337) is a PMOS transistors.
In regard to Claim 15:
Baharmast further discloses wherein the first input transistor (Fig 1; 311) and the second input transistor (Fig 1; 312) are NMOS transistors.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
2. Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baharmast (US 20240178806 A1), in view of Wadhwa (US 9209790 B1)
In regard to Claim 2:
Baharmast does not disclose a third transistor and fourth transistor having the same aspect ratio.
In a similar field of endeavor Wadhwa discloses wherein the third transistor (MN2) and the fourth transistor (MN3) have the same aspect ratio (Column 6, lines 51-55).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to utilize the third and fourth transistors having the same aspect ratio, as taught by Wadhwa, in combination with the elements taught by Baharmast. One would be motivated to do so because Wadhwa teaches having the same aspect ratio for the third and fourth transistors allows the gate voltage of both transistors to be equal (Wadhwa Column 6; lines 51-55).
3. Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baharmast (US 20240178806 A1), in view of Koblitz (US 5237222 A).
In regard to Claim 3:
Baharmast does disclose wherein the voltage drop across the third transistor is approximately 50 mV and/or wherein the voltage drop across the fifth transistor is approximately 50 mV.
In a similar field of endeavor Koblitz discloses, in figure 2, wherein the voltage drop across the third transistor (Fig 2; 242) is approximately 50 mV (Column 2 lines 47-49).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to utilize the transistor having a 50 mV drop across it, as taught by Koblitz, in combination with the elements taught by Baharmast. One would be motivated to do so because Koblitz teaches that the transistor having a 50 mV allows for an extended input voltage range (Koblitz Column 1, lines 41-44).
4. Claim(s) 4-5 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baharmast (US 20240178806 A1), in view of Sakurai (US 10715117 B1).
In regard to Claim 4:
Baharmast does not disclose at least one hysteresis transistor wherein the at least one hysteresis transistor wherein at least one hysteresis transistor is arranged to provide hysteresis of the output portion.
In a similar field of endeavor, Sakurai discloses, in figure 1, at least one hysteresis transistor (Fig 1; 110) wherein the at least one hysteresis transistor (11) is arranged to provide hysteresis of the output portion.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to utilize the hysteresis transistor, as taught by Sakurai, in combination with the elements taught by Baharmast. One would be motivated to do so because Sakurai teaches these transistors comprise the input portion contributing to the hysteresis (Sakurai Fig 1; input portion 102 comprises of transistors 110 and 112; Column 2 lines 63-65).
In regard to Claim 5:
Baharmast does not disclose at least one inverter, arranged to invert the output voltage, and to supply this inverted output voltage to one of the at least one hysteresis transistors as a control signal.
In a similar field of endeavor Sakurai discloses, in figure 1, further comprising at least one inverter (Fig 1; inverter providing signal 132) arranged to invert the output voltage (Fig 1; Vout), and to supply this inverted output voltage to one of the at least one hysteresis transistors as a control signal (Fig 1; inverter provides control signal 132 to hysteresis transistors 110 & 112).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to utilize the inverter, inverting the output and providing the inverted output to the hysteresis transistor, as taught by Sakurai, in combination with the elements taught by Baharmast. One would be motivated to do so because Sakurai teaches the inverter provides for the control signal (Fig 1; 132) to the portions of the comparator that provide the hysteresis (Sakurai Column 2 lines 63-65 & Column 3 lines 24-26) .
In regard to Claim 7:
Baharmast does not disclose a comparator circuit further comprising a first inverter, arranged to invert the output voltage, and to apply the resulting signal to a gate of the thirteenth hysteresis transistor and a second inverter, arranged to invert the resulting the signal produced by the first inverter, and to apply to further inverted signal to a gate of the fourteenth hysteresis transistor.
In a similar field of endeavor Sakurai discloses, in figure 1, further comprising a first inverter (Fig 1; inverter providing signal 132), arranged to invert the output voltage (Vout), and to apply the resulting signal to a gate of the thirteenth hysteresis transistor (110) and a second inverter (Fig 1; inverter providing signal 134), arranged to invert the resulting signal produced by the first inverter, and to apply the further inverted signal (signal 134) to a gate of the fourteenth transistor (120).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to utilize the a first inverter to invert the output voltage and to apply the resulting signal to a gate of the thirteenth transistor and a second inverter arranged to invert the resulting signal from the first inverter and to apply that signal to a gate of the fourteenth transistor, as taught by Sakurai, in combination with the elements taught by Baharmast. One would be motivated to do so because Sakurai teaches that these two inverters provide two control signals (Fig 1; 132 and 134) to control the input portions of the comparator providing the hysteresis (Sakurai Column 2 lines 63-65).
5. Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baharmast (US 20240178806 A1), in view of Rizzo (US 12487623 B2).
In regard to Claim 10:
Baharmast does not disclose wherein the third current supply supplies a current of approximately 30 nA.
In a similar field of endeavor Rizzo discloses, in figure 4, the third current supply (Fig 4; 44) supplies a current of approximately 30 nA (Column 5 lines 54-55).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to utilize the third current supply supplying a current of approximately 30 nA taught by Rizzo in combination with the elements taught by Baharmast. One would be motivated to do so because Rizzo teaches that having a low current of 30 nA is part of the bigger goal of reducing the quiescent current consumption (Rizzo Column 10, lines 9-12).
6. Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baharmast (US 20240178806 A1), in view of Agut (US 20140091846 A1).
In regard to Claim 16:
Baharmast does not disclose a first or second mirror portion arranged to mirror current form the fifth or third transistors.
In a similar field of endeavor Agut discloses, in figure 6, a first mirror portion (Fig 6; T5), arranged to mirror current from the fifth transistor (Fig 6; T9) to the output portion (NOUT) and a second mirror portion (T6), arranged to mirror current from the third transistor (T10) to the output portion (OUT).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to utilize the first and second mirror portion arranged to mirror current from the fifth and third transistor to the output portion. One would be motivated to do so because Agut teaches that these mirror portions contribute to the means for creating the hysteresis (Agut Column 3 paragraph 66).
Allowable Subject Matter
Claim 6 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 6 is objected to under the following: a thirteenth hysteresis transistor and a fourteenth hysteresis transistor, wherein the third transistor comprises a first pair of series-connected transistors and the fifth transistor comprises a second pair of series-connected transistors, wherein a first terminal of the thirteenth hysteresis transistor is connected between the first pair of series-connected transistors and wherein a first terminal of the fourteenth hysteresis transistor is connected between the second pair of series-connected transistors.
Claim 8 is objected under the following: at least one of the third transistor, the fourth transistor, the seventh gain transistor, the eighth gain transistor are provided by a series-connected pair of transistors.
Claim 12 is objected under the following: wherein the first and second current supplies are approximately 7.5 nA.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMAAN JAWAD KHAN whose telephone number is (571)270-7266. The examiner can normally be reached M-Th 9-4.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at (571)-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/A.J.K./
Examiner, Art Unit 2843
/Jessica Han/Supervisory Patent Examiner, Art Unit 2843
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