DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of FIG. 2, Species I, claims 1-5, 8, and 11-20 in the reply filed on 08/09/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Claims 6, 7, 9 and 10 which depends on claim 9 are withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites “the same landing pad” lack antecedent basis.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 8, and 11-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho et al. 20220384661.
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Regarding claim 1, figs. 1-2B of Cho discloses a semiconductor device comprising:
a substrate 101;
a lower insulation layer 105/108 (fig. 2B) positioned above the substrate;
a bit line 110 positioned above the lower insulation layer (see 110 is above portion 105 of lower insulation layer) and extending parallel to the substrate in a first direction D1;
a first insulating pattern 120 positioned above the bit line and extending in a second direction D2 intersecting the first direction;
a channel pattern 130 electrically connected to the bit line and covering a side of the first insulating pattern 120;
a word line 150A/B extending in the second direction D2 and spaced apart from the channel pattern;
a gate insulating pattern 140 positioned between the channel pattern and the word line;
a second insulating pattern 181 positioned above the word line, the gate insulating pattern, and the first insulating pattern; and
a landing pad 170A/B electrically connected to the channel pattern,
wherein a part of the word line is positioned between a plurality of bit lines arranged spaced apart in the second direction (fig. 1).
Regarding claim 12, figs. 1-2B of Cho discloses a semiconductor device comprising:
a substrate 101;
a lower insulation layer 105/108 (fig. 2B) positioned above the substrate;
a bit line 110 positioned above the lower insulation layer (see 110 is above portion 105 of lower insulation layer) and extending parallel to the substrate in a first direction D1;
a first insulating pattern 120 positioned above the bit line and extending in a second direction D2 intersecting the first direction;
a channel pattern 130 electrically connected to the bit line and covering a side of the first insulating pattern 120;
a word line 150A/B extending in the second direction D2 and spaced apart from the channel pattern;
a gate insulating pattern 140 positioned between the channel pattern and the word line;
a second insulating pattern 181 positioned above the word line, the gate insulating pattern, and the first insulating pattern; and
a landing pad 170A/B electrically connected to the channel pattern,
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wherein the word line 150A/15B includes protruded parts protruding in a third direction vertical D3 to the substrate towards an upper surface of the lower insulation layer, and
wherein each of the protruded parts of the word line is positioned between bit lines adjacent in the second direction.
Regarding claim 19, figs. 1-2B of Cho discloses a semiconductor device comprising:
a substrate 101;
a lower insulation layer 105/108 (fig. 2B) positioned above the substrate;
a bit line 110 positioned above the lower insulation layer (see 110 is above portion 105 of lower insulation layer) and extending parallel to the substrate in a first direction D1;
a first insulating pattern 120 positioned above the bit line and extending in a second direction D2 intersecting the first direction;
a channel pattern 130 electrically connected to the bit line and covering a side of the first insulating pattern 120;
a word line 150A/B extending in the second direction D2 and spaced apart from the channel pattern;
a gate insulating pattern 140 positioned between the channel pattern and the word line;
a second insulating pattern 181 positioned above the word line, the gate insulating pattern, and the first insulating pattern; and
a landing pad 170A/B electrically connected to the channel pattern,
wherein the bit line 110 has an upper surface at a higher vertical level than the upper surface of the lower insulation layer (see upper surface of 115 portion of 110), and
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wherein a portion of the bit line positioned at a higher vertical level than the upper surface of the lower insulation layer overlaps with the word line in the second direction and in a third direction vertical to the substrate.
Regarding claim 2, fig. 2A of Cho discloses wherein: the word line includes a first part (bottom surface parts) covering upper surfaces of bit lines arranged in the second direction (see bottom surface extends into D2) and extending in the second direction, and second parts (side surface parts) extending in a third direction vertical to the substrate toward an upper surface of the lower insulation layer from a bottom surface of the first part, and the second parts are each positioned between the bit lines adjacent in the second direction.
Regarding claim 3, fig. 2A of Cho discloses wherein the first part of the word line overlaps the bit lines in the third direction, and the second parts of the word line respectively overlap the bit lines in the second direction.
Regarding claim 4, fig. 2A of Cho discloses wherein the channel pattern is in contact with an upper surface and both sides of the bit line.
Regarding claim 5, figs. 2A-2B of Cho discloses wherein: an upper surface of the lower insulation layer is positioned at a vertical level between the upper surface and a bottom surface of the bit line (see fig. 2B), the channel pattern surrounds the upper surface of the bit line and a portion of the both sides of the bit line extending from the upper surface of the bit line, and a part of the both sides of the bit line includes a part positioned at a higher vertical level than the upper surface of the lower insulation layer (see fig. 2A).
Regarding claim 8, fig. 2A/B of Cho discloses wherein: the first insulating pattern is a plurality of first insulating patterns (108 and 105), the plurality of first insulating patterns are arranged and spaced apart along the first direction (fig. 2B showing 108 are as such), the channel pattern is positioned between first insulating patterns adjacent in the first direction of the plurality of first insulating patterns and includes a horizontal part 10C (fig. 2A) covering the bit line and vertical parts 130A extending from the horizontal part in a third direction perpendicular to the substrate and facing the first direction, and the vertical parts are connected to the same landing pad.
Regarding claim 11, par [0035] of Cho discloses wherein the channel pattern includes indium gallium zinc oxide (IGZO).
Regarding claim 13, fig. 1 of Cho discloses wherein each of the protruded parts of the word line overlap with the bit lines adjacent in the second direction.
Regarding claim 14, fig. 2A of Cho discloses wherein three sides of the bit line are surrounded by the channel pattern.
Regarding claim 15, figs. 2A-2B of Cho discloses wherein: a bottom surface of the bit line and a lower part of both sides of the bit line extending from the bottom surface of the bit line are surrounded by the lower insulation layer, and an upper surface of the bit line and an upper part of both sides of the bit line extending from the upper surface are surrounded by the channel pattern.
Regarding claim 16, figs. 2A-2B of Cho discloses wherein: an upper surface of the bit line and both sides of the bit line are surrounded by the channel pattern, and a bottom surface of the bit line is in contact with the upper surface of the lower insulation layer.
Regarding claim 17, fig. 2A-2B of Cho discloses wherein: the first insulating pattern and the channel pattern are alternately and repeatedly arranged along the first direction, the channel pattern includes a horizontal part covering an upper surface of the bit line and vertical parts covering opposing sides of first insulating patterns adjacent in the first direction, and one word line is positioned between the vertical parts.
Regarding claim 18, fig. 2A-2B of Cho discloses wherein: the first insulating pattern and the channel pattern are alternately and repeatedly arranged along the first direction, the channel pattern includes a horizontal part covering an upper surface of the bit line and vertical parts covering opposing sides of first insulating patterns adjacent in the first direction, and two word lines 150A/B spaced apart in the first direction are positioned between the vertical parts.
Regarding claim 20, fig. 2A of Cho discloses wherein: the channel pattern includes a first surface in contact with the upper surface of the bit line, and second surfaces in contact with both sides of the bit line, and each of the second surfaces is in contact with the side of the bit line positioned at a higher vertical level than the upper surface of the lower insulation layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VONGSAVANH SENGDARA whose telephone number is (571)270-5770. The examiner can normally be reached 9AM-6PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VONGSAVANH SENGDARA/ Primary Examiner, Art Unit 2893
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