Detailed Action
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
2. The Amendment filed on 03/24/2026 has been entered. Claims 1 and 12 have been amended. Claims 1-3, 5-14 and 16-22 remain pending in the application.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
4. Claims 1-2, 5-13, and 16-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by UEHARA (US 20180182064 A1).
Regarding claim 1, UEHARA (Figs. 3-6 and 12-13) discloses a method of data transmission in a display device, the method comprising: monitoring delimiter pulses of pixel packets in an active area of a frame (e.g., Figs. 3 and 5-6; dummy signals act as delimiters to define boundary between successive data packets and mark when one data packet ends and the next begins), delimiter pulses of at least two pixel packets in the active area of the frame being different in width (e.g., Figs. 5-6; dummy signals having different width); synchronizing a clock according to the delimiter pulses of the pixel packets in the active area of the frame to generate a synchronized clock (e.g., Fig. 4; synchronization clock signal and pixel data packet, clock signal is synchronized with a dummy signal to identify a start and an end of a pixel data); and clocking data in the pixel packets in the active area of the frame using the synchronized clock (e.g., Fig. 4; pixel data packet and synchronization clock signal), wherein data rates of the pixel packets vary according to respective widths of the delimiter pulses of the pixel packets (e.g., Figs. 5-6; data rates are varied in accordance with widths of delimiter pulses).
Regarding claim 2, UEHARA (Figs. 3-6 and 12-13) discloses the method of Claim 1, wherein monitoring the delimiter pulses of the pixel packets in active area of the frame comprises: identifying a delimiter pulse in a pixel packet in the active area of the frame (e.g., Figs. 3 and 5-6; dummy signals act as delimiters to separate data signals of data packets).
Regarding claim 5, UEHARA (Figs. 3-6 and 12-13) discloses the method of Claim 1, wherein data rates of the pixel packets are varied within a predetermined rate range (Figs. 5-6, 12-13, and 15; variable data rate).
Regarding claim 6, UEHARA (Figs. 3-6 and 12-13) discloses the method of Claim 1, wherein: a data rate of a succeeding data packet is increased by a constant amount compared to a preceding data packet (e.g., Figs. 5-6 and 12-13; increasing a data rate).
Regarding claim 7, UEHARA (Figs. 3-6 and 12-13) discloses the method of Claim 1, wherein: a data rate of a succeeding data packet is increased by a variable amount compared to a preceding data packet (e.g., Figs. 5-6 and 12-13; increasing a data rate).
Regarding claim 8, UEHARA (Figs. 3-6 and 12-13) discloses the method of Claim 1, wherein: a data rate of a succeeding data packet is decreased by a constant amount compared to a preceding data packet (e.g., Figs. 5-6 and 12-13; decreasing a data rate).
Regarding claim 9, UEHARA (Figs. 3-6 and 12-13) discloses the method of Claim 1, wherein: a data rate of a succeeding data packet is decreased by a variable amount compared to a preceding data packet (e.g., Figs. 5-6 and 12-13; decreasing a data rate).
Regarding claim 10, UEHARA (Figs. 3-6 and 12-13) discloses the method of Claim 1, wherein the at least two pixel packets are located in a dummy line of the active area (e.g., Figs. 3-5 and 12; dummy data and data packet).
Regarding claim 11, UEHARA (Figs. 3-6 and 12-13) discloses the method of Claim 1, wherein the at least two pixel packets are located in a pixel line of the active area (e.g., Figs. 3-5 and 12; data packet and pixel line).
Regarding claim 12, UEHARA (Figs. 3-6 and 12-13) discloses a display device comprising: a timing controller (controller 10); a transmission line (signal line connected to display driver 100); and a source driver (display driver 100) coupled to the timing controller (controller 10) via the transmission line to monitor delimiter pulses of pixel packets in an active area of a frame (e.g., Figs. 3 and 5-6; dummy signals act as delimiters to define boundary between successive data packets and mark when one data packet ends and the next begins), synchronize a clock according to the delimiter pulses of the pixel packets in the active area of the frame to generate a synchronized clock (e.g., Fig. 4; synchronization clock signal and pixel data packet, clock signal is synchronized with a dummy signal to identify a start and an end of a pixel data), and clock data in the pixel packets in the active area of the frame using the synchronized clock (e.g., Fig. 4; pixel data packet and synchronization clock signal); wherein delimiter pulses of at least two pixel packets in the active area of the frame are different in width (e.g., Figs. 5-6; dummy signals having different width), and data rates of the pixel packets vary according to respective widths of the delimiter pulses of the pixel packets (e.g., Figs. 5-6; data rates are varied in accordance with widths of delimiter pulses).
Regarding claim 13, UEHARA (Figs. 3-6 and 12-13) discloses the display device of Claim 12, wherein the source driver identifies a delimiter pulse in a pixel packet in the active area of the frame (e.g., Figs. 3 and 5-6; dummy signals act as delimiters to separate data signals of pixel data packets).
Regarding claim 16, UEHARA (Figs. 3-6 and 12-13) discloses the display device of Claim 12, wherein the timing controller varies data rates of the pixel packets within a predetermined rate range (Figs. 5-6, 12, and 15; variable data rate).
Regarding claim 17, UEHARA (Figs. 3-6 and 12-13) discloses the display device of Claim 12, wherein the timing controller increases a data rate of a succeeding data packet by a constant amount compared to a preceding data packet (e.g., Figs. 5-6 and 12-13; increasing a data rate).
Regarding claim 18, UEHARA (Figs. 3-6 and 12-13) discloses the display device of Claim 12, wherein the timing controller increases a data rate of a succeeding data packet by a variable amount compared to a preceding data packet (e.g., Figs. 5-6 and 12-13; increasing a data rate).
Regarding claim 19, UEHARA (Figs. 3-6 and 12-13) discloses the display device of Claim 12, wherein the timing controller decreases a data rate of a succeeding data packet by a constant amount compared to a preceding data packet (e.g., Figs. 5-6 and 12-13; decreasing a data rate).
Regarding claim 20, UEHARA (Figs. 3-6 and 12-13) discloses the display device of Claim 12, wherein the timing controller decreases a data rate of a succeeding data packet by a variable amount compared to a preceding data packet (e.g., Figs. 5-6 and 12-13; decreasing a data rate).
Regarding claim 21, UEHARA (Figs. 3-6 and 12-13) discloses the display device of Claim 12, wherein the at least two pixel packets are located in a dummy line of the active area (e.g., Figs. 3-5 and 12; dummy data and data packet).
Regarding claim 22, UEHARA (Figs. 3-6 and 12-13) discloses the display device of Claim 12, wherein the at least two pixel packets are located in a pixel line of the active area (e.g., Figs. 3-5 and 12; data packet and pixel line).
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 3 and 14 are rejected under 35 U.S.C. 103 as unpatentable over UEHARA (US 20180182064 A1) in view of JEON (US 20110286562 A1).
Regarding claim 3, UEHARA (Figs. 3-6 and 12-13) discloses the method of Claim 2, but does not disclose adjusting a phase and a frequency of the clock according to the delimiter pulse in the pixel packet to generate the synchronized clock. However, JEON discloses wherein synchronizing the clock according to the delimiter pulses of the pixel packets in the active area of the frame to generate the synchronized clock comprises: adjusting a phase and a frequency of the clock according to the delimiter pulse in the pixel packet to generate the synchronized clock (e.g., Fig. 2; dummy signals act as delimiters to separate data signals of data packets, a phase and a frequency of clock signals are adjusted in accordance with dummy signals). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from JEON to the data transmission of the display device of UEHARA, which would provide a signal control for the data transmission.
Regarding claim 14, UEHARA (Figs. 3-6 and 12-13) discloses the display device of Claim 13, but does not disclose wherein the source driver adjusts a phase and a frequency of the clock according to the delimiter pulse in the pixel packet to generate the synchronized clock. However, JEON discloses a display device, wherein the source driver adjusts a phase and a frequency of the clock according to the delimiter pulse in the pixel packet to generate the synchronized clock (e.g., Fig. 2; dummy signals act as delimiters to separate data signals of data packets, a phase and a frequency of clock signals are adjusted in accordance with dummy signals). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from JEON to the data transmission of the display device of UEHARA, which would provide a signal control for the data transmission.
Response to Arguments
7. Applicant's arguments filed 03/24/2026 have been fully considered but they are not persuasive.
8. Regarding claims 1 and 12, applicant first argues that the cited references do not disclose the limitations “synchronizing a clock according to the delimiter pulses”.
The examiner respectfully disagrees with applicant’s arguments. UEHARA (Figs. 3-6 and 12-13) discloses a data transmission in a display device. UEHARA (e.g., Figs. 3 and 5-6) discloses dummy signals act as delimiters, which define boundary between successive data packets and mark when one data packet ends and the next begins. Clock signals are aligned or synchronized in accordance with the dummy signals (delimiter pulses) so that the receiving circuits identify the start and end of data transfer.
Applicant further argues that the cited references do not disclose the new limitations wherein data rates of the pixel packets vary according to respective widths of the delimiter pulses of the pixel packets. The examiner respectfully disagrees with applicant’s arguments because UEHARA (e.g., Figs. 5-6) discloses data rates are varied in accordance with widths of dummy signals (delimiter pulses). Specifically, UEHARA (e.g., Figs. 5-6) discloses data rates are increased with reduced widths of dummy signals (delimiter pulses).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YUZHEN SHEN whose telephone number is (571)272-1407. The examiner can normally be reached on 9:00-18:00.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YUZHEN SHEN/Primary Examiner, Art Unit 2623
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