Prosecution Insights
Last updated: April 19, 2026
Application No. 18/744,745

GATE DRIVER CIRCUIT CAPABLE OF PREVENTING SPIKES

Non-Final OA §102
Filed
Jun 17, 2024
Examiner
PUENTES, DANIEL CALRISSIAN
Art Unit
2849
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Richtek Technology Corporation
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
2y 3m
To Grant
92%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allow Rate
807 granted / 911 resolved
+20.6% vs TC avg
Minimal +3% lift
Without
With
+2.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
29 currently pending
Career history
940
Total Applications
across all art units

Statute-Specific Performance

§101
1.0%
-39.0% vs TC avg
§103
39.7%
-0.3% vs TC avg
§102
33.6%
-6.4% vs TC avg
§112
18.8%
-21.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 911 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claim 6 is withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 11/24/2025. It is noted that no arguments were made with Applicant’s traversal. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-2 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Applicant’s Admitted Prior Art (Figure 1, hereinafter “AAPA”) in view of Feng (CN115864790A). For claim 1, AAPA teaches a gate driver circuit (Figure 1) for providing a soft-start current to a gate of a power switch (Iss) during a soft-start period to soft-start the power switch ([0003] of Applicant’s Specification), the gate driver circuit comprising: a first current mirror circuit (all four NMOS transistors of Figure 1) configured to mirror a reference current (unlabeled current source at the top of the left branch) according to a mirror ratio to generate a mirror output current (Imr, [0003] of Applicant’s Specification), wherein the soft-start current is generated according to the mirror output current (as understood by examination of Figure 1); and a path switch (Sp) coupled to a signal path between the mirror output current and the soft-start current and configured to turn off the signal path when the power switch is turned off (as understood by examination of Figure 1); AAPA fails to teach: wherein, during a predetermined period within the soft-start period, the mirror ratio of the first current mirror circuit is reduced to compensate for a spike caused by the path switch being turning on during the soft-start period, so as to prevent the soft-start current from surging during the soft-start period. However, Feng teaches varying the ratio of a current mirror (right side of Figure 1) to produce a gradual stepwise increase (via F1, F2, F3) in output current (Ic, Figure 3) by enabling/disabling a plurality of branches of the current mirror based on a comparison of the output voltage to a plurality of reference values (left side of Figure 1). For example, the plurality of branches can correspond to 1/8, 2/8 and 4/8 of a reference current (right side of Figure 1). Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to vary the mirror ratio of AAPA’s first current mirror (by connecting additional NMOS transistors in parallel to the NMOS receiving B at its gate on the right side) based on a comparison of AAPA’s output voltage (VG) with a plurality of reference values in order to prevent overshoot and undershoot of the gate drive voltage (Disclosure of Invention, Feng). Furthermore, the substitution of one known element for another would have yielded predictable results to one of ordinary skill in the art at the time of the invention. The combination of AAPA and Feng teaches: wherein, during a predetermined period within the soft-start period (based on comparison of VG to reference values), the mirror ratio of the first current mirror circuit is reduced to compensate for a spike caused by the path switch being turning on during the soft-start period, so as to prevent the soft-start current from surging during the soft-start period (as understood by examination of Feng’s Figures 1 and 3). For claim 2, AAPA in view of Feng teaches the limitations of claim 1 and AAPA further teaches: a second current mirror circuit (MP1, MP2) configured to mirror the mirror output current to generate the soft-start current, wherein the path switch is coupled between the first current mirror circuit and the second current mirror circuit (as understood by the combination of references as cited above). Allowable Subject Matter Claims 3-5 and 7-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL CALRISSIAN PUENTES whose telephone number is (571)270-5070. The examiner can normally be reached M-F 9-6:30 (flex). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DANIEL C PUENTES/Primary Examiner, Art Unit 2849
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Prosecution Timeline

Jun 17, 2024
Application Filed
Dec 13, 2025
Non-Final Rejection — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
92%
With Interview (+2.9%)
2y 3m
Median Time to Grant
Low
PTA Risk
Based on 911 resolved cases by this examiner. Grant probability derived from career allow rate.

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