DETAILED ACTION
This action is responsive to the Response to Election filed 24 Feb 2026, the application filed 17 Jun 2024 and the Information Disclosure Statement filed 1 Jul 2024. Claims 1-10 are elected, claims 11-20 are withdrawn. Claims 1 and 9 are independent.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Notice of Foreign Priority Claim
Acknowledgment is made of applicant’s claim for foreign priority. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1 Jul 2024 is acknowledged. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Examiner Note
The present application has used the limitations of “erase operations” an “program operations” and “first program command”. The examiner notes that an “erase operation” can comprise any step in a process that erases data from a memory cell, which sometimes comprises writing a “zero” as data in each of the memory cells; which can comprise a verification step, or a testing step. The limitation “erase operation” does not necessarily require any actual voltages applied to any control line unless specified in the claims.
The present application has used the limitation of “target block”. In paragraph 0064, the block is described as a “plurality of memory cell transistors… a plurality of bit lines, a plurality of word lines.” Thus, the claimed “block” can be any subset of memory cells containing at least two word lines, two bit lines, and a plurality of memory cell. This may comprise Thoppa’s cited “sub-block” as well.
Claim Objections
Claim 3 is objected to because of the following informalities: the claim contains the word “configutred”. It has been examined as if this word were “configured”. Correction is required.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claim 5 and 11 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
Specifically, the limitation “that detects the number of clocks of a charge pump that generates a voltage of the source line”, the specification does not describe how a charge pump has a “number of clocks”.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim(s) 5, 10, 7 and 8 is/are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 5 and 10 have the limitation, “that detects the number of clocks of a charge pump that generates a voltage of the source line,”. It is indefinite because charge pumps comprise circuitry to typically increase the voltage of a source voltages, such as Vdd. They do not typically comprise a “number of clocks”.
Claim 7 and 8 have the limitations “the first erase operation: and “the determination operation” Claim 1 has the different limitation “an erase operation” and “an erase verification operation”. There is insufficient antecedent for the limitations in claims 7 and 8. It is unknown if the cited “operations” are different operations, a sub-set of the claim 1 operations, or the same operate as cited in claim 1. Correction is required.
Claim Rejections – 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless —
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1 – 10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Thoppa, et al, United States Publication 2024/0290412 (“Thoppa”).
Regarding claim 1, Thoppa teaches:
A semiconductor memory device, comprising: a plurality of planes, each of the plurality of planes including at least one or more blocks, each of the one or more blocks including a plurality of memory cells, (Thoppa, fig 1, 2, “[0006] The term “erase block” or “erase group” may be used herein to refer to a group of NAND memory cells that share word lines and are erased together. It is also possible to erase multiple erase blocks together, such as one erase block on each plane on a memory die.”; a memory array with multiple blocks on multiple planes; a controller is used to send commands to erase addressable blocks or sub-blocks, or blocks on different planes).
a controller configured to erase data of each of the plurality of memory cells in an erase target block selected in each of the plurality of planes, (Thoppa, fig 1, 2, “[0034] Processor 156 performs the various controller memory operations, such as programming, erasing, reading, and memory management processes. [0082] For example, one block in each plane may be selected for erase in a parallel multi-block erase. Because the blocks being erased are on different planes, this could also be referred to as a multi-plane erase.”; a controller that can erase memory blocks; that can erase one block in each plane in a “multi-plane erase” operation).
by executing an erase sequence that repeats a plurality of loops, each of the loops including a set of an erase operation that erases the data of each of the plurality of memory cells in the erase target block and (Thoppa, fig 6, 7, “[0120] At step 711 the block is then erased, followed by erase verification at step 713, and then determine whether the block passes the erase verify at step 715. … More specifically, at step 715, if the block does not pass the erase verify, the blocks status is either set to fail or, in an embodiment with multiple erase pulses with verifies in between, the flow can loop back to the equivalent of a step 615.”; a controller executes an erase operation on a block; that the erase operation includes a verify step that can lead to multiple erase pulses (a loop)).
an erase verification operation that checks whether the data is erased, and (Thoppa, fig 7, “[0120] If the block passes the erase verify at step 715, the flow then continues on to determine whether the post-erase defect detection test modes are enabled.”; a verify step that checks if the data is erased).
a source line electrically connected to one end of the plurality of memory cells in the plurality of planes, (Thoppa, fig 6, 7, “[0110] Process 600 describes a double sided erase in which an erase voltage (Vera) is applied at both ends of NAND strings (e.g., bit lines and source line).”; a source line connected to a NAND string which comprises a plurality of memory cells in a block, in a plane; each NAND string comprises a source line).
for each of the plurality of the erase target blocks, the controller is configured to detect whether there is a current leak from the source line, (Thoppa, fig 6, 7, “[0133] Returning to FIG. 7, the HIVR test mode of step 727 is also directed at determining whether there is current leakage between the word lines and the memory holes, [0134] FIG. 10 is a flowchart for an embodiment of a post-erase HIVR test mode.”; after the erase verify step, an HIVR test mode determines if there is current leakage between word lines and source lines).
determine validity of the erase sequence based on a detection result, and (Thoppa, fig 7, 10, “[0135] Step 1007 determines whether there is word line memory hole leakage… For example, leakage current either though the drain side select gate to the bit lines or through the source side select gate to the source line can be measure through circuitry in the column control circuitry 210.”; a current leak test of figure 10, step 1007 using the source line to detect the leaked current).
stop execution of the erase sequence for the erase target blocks that are determined not to be valid. (Thoppa, fig 7, 10, “[0135] Based on the result of the detection at step 1007, step 1009 determines whether the block is defective. [0136] Returning again to FIG. 7, the shown embodiment includes the three post-erase test modes described above at step 721. [0122] Step 729 determines whether or not the block passes the tests of step 721 and, if not, the block is retired at step 731.”; that the erase sequence of figures 6, 7, and 10 are halted (step 731 of fig 7) if a NAND string fails the current leakage test of step 1007 of figure 10).
Regarding claim 2, Thoppa teaches:
The semiconductor memory device according to claim 1, further comprising: a first voltage generation circuit configured to generate a voltage to be supplied to the source line, (Thoppa, fig 2, “[0037] The system control logic 260 is also shown to include charge pumps 269, which are voltage generators that can be used to generate operating voltages (e.g., read, program, and erase voltage levels) that are higher than the supply level.”; a voltage generator with charge pumps that can provide erase voltages to the memory array).
wherein the first voltage generation circuit is configured to supply an erase voltage to the source line during the erase operation. (Thoppa, fig 6, 7, “[0116] Process 600 describes a double-sided erase in which Vera is applied to both ends of the NAND strings (bit lines and source line(s)).”; the voltage generator applies Vera to both ends of the NAND string, specifically the bit line and source line).
Regarding claim 3, Thoppa teaches:
The semiconductor memory device according to claim 2, further comprising: a plurality of word lines connected to gates of the plurality of memory cells, respectively; and (Thoppa, fig 2, “[0053] Similarly, row control circuitry 220, including row decoder 222, array drivers 224, and block select 226 are coupled to memory structure 202 through electrical paths 208. Each electrical path 208 may correspond to a word line, dummy word line, or select gate line. [0082] In some embodiments, a physical block represents a groups of connected memory cells as the memory cells of a physical block share a common set of word lines.”; that word lines are connected to memory cells from the voltage generators;).
a plurality of second voltage generation circuits configutred to generate voltages to be supplied to the plurality of word lines, wherein during the erase operation, the plurality of word lines in the erase target block in at least one of the planes are supplied with a ground voltage from the second voltage generation circuit (Thoppa, fig 2, “[0111] Step 608 includes applying an erase enable to the word lines in the erase block. In one embodiment, the erase enable voltage is 0V. Step 610 includes applying a select voltage to select lines (e.g., SGD, SGS). The select voltage allows Vera to pass to the NAND channels.”; that at least three voltages are sent from the controller and charge pumps to the memory array, requiring three different ‘circuits’; that the word lines can be set to “erase enable” or zero volts).
corresponding to the at least one plane. (Thoppa, fig 2, “[0036] Row control circuitry 220 receives a group of M row address signals and one or more various control signals from System Control Logic circuit 260, and typically may include such circuits as row decoders 222, array drivers 224, and block select circuitry 226 for both reading and writing (programming) operations.”; that the control circuitry has a “block select circuitry” 226 to select the correct memory block for operations).
Regarding claim 4, Thoppa teaches:
The semiconductor memory device according to claim 3, wherein each of the plurality of planes further includes a first detection circuit configured to execute a first detection operation to detect a current of the plurality of word lines supplied with a voltage from the corresponding second voltage generation circuit, (Thoppa, fig 10, “[0135] Step 1007 determines whether there is word line memory hole leakage once the block is biased according to steps 1001, 1003, and 1005. For example, leakage current either though the drain side select gate to the bit lines or through the source side select gate to the source line can be measure through circuitry in the column control circuitry 210.”; a circuit in the column control circuitry that can sense current leakage from the method of figure 10 in step 1007; that the row control circuitry sets the word lines from a separate voltage line).
each of the first detection circuits configured to perform the first detection operation while the erase voltage is supplied from the first voltage generation circuit to the source line and (Thoppa, fig 6, 7, “[0110] Process 600 describes a double sided erase in which an erase voltage (Vera) is applied at both ends of NAND strings (e.g., bit lines and source line). [0133] Since the larger the voltage difference, the easier it is to detect leakage; and since the control circuitry of a NAND memory can typically apply higher voltage levels to word lines than bit line, the following embodiment sets the word lines to a higher voltage (one of the operating voltage levels available) and the memory hole to a lower level, such as 0V. [0111] Step 602 includes setting an initial magnitude of an erase voltage (Vera). The initial Vera may have a relatively large magnitude such as, for example, 20V.”; a source line connected to a NAND string which comprises a plurality of memory cells in a block, in a plane; each NAND string comprises a source line; that the source and bit lines can be set to a “higher voltage”, or one of the operating voltages available, that Thoppa previously disclosed that Vera could be 20V).
the ground voltage is supplied from the second voltage generation circuit to a plurality of the word lines connected to the plurality of memory cells in the erase target block, and (Thoppa, fig 2, “[0111] Step 608 includes applying an erase enable to the word lines in the erase block. In one embodiment, the erase enable voltage is 0V. Step 610 includes applying a select voltage to select lines (e.g., SGD, SGS). The select voltage allows Vera to pass to the NAND channels.”; that at least three voltages are sent from the controller and charge pumps to the memory array, requiring three different ‘circuits’; that the word lines can be set to “erase enable” or zero volts; that the 0 volts can be used in both the erase step and used in the current leakage test step).
the controller configured to determine that the erase target block is not valid in the erase sequence when the current is detected in the first detection operation. (Thoppa, fig 10, “[0135] Step 1007 determines whether there is word line memory hole leakage once the block is biased according to steps 1001, 1003, and 1005. For example, leakage current either though the drain side select gate to the bit lines or through the source side select gate to the source line can be measure through circuitry in the column control circuitry 210. … Bases on the result of the detection at step 1007, step 1009 determines whether the block is defective.”; a circuitry in the column control circuitry that can sense current leakage from the method of figure 10 in step 1007; the result of the test is determined in step 1009).
Regarding claim 5, Thoppa teaches:
The semiconductor memory device according to claim 3, wherein the first voltage generation circuit further includes a second detection circuit configured to execute a second detection operation that detects the number of clocks of a charge pump that generates a voltage of the source line, (Thoppa, fig 10, “[0135] Step 1007 determines whether there is word line memory hole leakage once the block is biased according to steps 1001, 1003, and 1005. A number of embodiments are available for this determination. *Alternate, after trapping charge on the word lines for an interval, the voltage levels on the word lines can be measured to see if there has been appreciable discharge from the block’s word lines. In other embodiments, after allow a discharge period for any leaking word lines, a read can be performed of the memory block to see whether one or more word lines have discharged to the extent that they tum off the NAND string.”; a circuit in the column control circuitry that can sense current leakage from the method of figure 10 in step 1007; that the row control circuitry sets the word lines from a separate voltage line).
the second detection circuit configured to perform the second detection operation while the erase voltage is supplied from the first voltage generation circuit to the source line and (Thoppa, fig 6, 7, “[0110] Process 600 describes a double sided erase in which an erase voltage (Vera) is applied at both ends of NAND strings (e.g., bit lines and source line). [0133] Since the larger the voltage difference, the easier it is to detect leakage; and since the control circuitry of a NAND memory can typically apply higher voltage levels to word lines than bit line, the following embodiment sets the word lines to a higher voltage (one of the operating voltage levels available) and the memory hole to a lower level, such as 0V. [0111] Step 602 includes setting an initial magnitude of an erase voltage (Vera). The initial Vera may have a relatively large magnitude such as, for example, 20V.”; a source line connected to a NAND string which comprises a plurality of memory cells in a block, in a plane; each NAND string comprises a source line; that the source and bit lines can be set to a “higher voltage”, or one of the operating voltages available, that Thoppa previously disclosed that Vera could be 20V).
the ground voltage is supplied from one second voltage generation circuit to a plurality of the word lines connected to the plurality of memory cells in the erase target block, and (Thoppa, fig 2, “[0111] Step 608 includes applying an erase enable to the word lines in the erase block. In one embodiment, the erase enable voltage is 0V. Step 610 includes applying a select voltage to select lines (e.g., SGD, SGS). The select voltage allows Vera to pass to the NAND channels.”; that at least three voltages are sent from the controller and charge pumps to the memory array, requiring three different ‘circuits’; that the word lines can be set to “erase enable” or zero volts; that the 0 volts can be used in both the erase step and used in the current leakage test step).
the controller configured to determine that the erase target block is not valid in the erase sequence when the number of clocks is higher than a set threshold in the second detection operation. (Thoppa, fig 10, “[0135] Step 1007 determines whether there is word line memory hole leakage once the block is biased according to steps 1001, 1003, and 1005. *Alternate, after trapping charge on the word lines for an interval, the voltage levels on the word lines can be measured to see if there has been appreciable discharge from the block’s word lines. In other embodiments, after allow a discharge period for any leaking word lines, a read can be performed of the memory block to see whether one or more word lines have discharged to the extent that they tum off the NAND string.. … Bases on the result of the detection at step 1007, step 1009 determines whether the block is defective.”; a circuitry in the column control circuitry that can sense current leakage from the method of figure 10 in step 1007; here after a set interval of time (the claimed “clocks”), the voltage levels on the word lines can be measured (the second detection circuit) “to the extent” (a threshold voltage) they turn off the NAND string; then the result of the test is determined in step 1009).
Regarding claim 6, Thoppa teaches:
The semiconductor memory device according to claim 1, wherein for each of the plurality of erase target blocks, the controller is configured to sequentially execute the erase operation and (Thoppa, fig 6, 7, “[0006] It is also possible to erase multiple erase blocks together, such as one erase block on each plane on a memory die. [0082] For example, one block in each plane may be selected for erase in a parallel multi-block erase. Because the blocks being erased are on different planes, this could also be referred to as a multi-plane erase. [0110] For example, the sub-block selected by SGD-s0 may be erased independent of the other four sub-blocks.”; that memory blocks can be erased together in different planes, in different blocks, and in sequenced in different sub-blocks. Note: “Sequentially” here has been interpreted that a set of blocks can be erase in a controlled sequence, as is common in the art. “Block” as claimed here can refer to any subset of wordlines to include Thoppa’s “sub-blocks”).
the erase verification operation, and in the erase verification operation, determine that the erase target blocks whose erase degree of the data is less than or equal to a set value are not valid in the erase sequence. (Thoppa, fig 7, 10, “[0135] Step 1007 determines whether there is word line memory hole leakage… For example, leakage current either though the drain side select gate to the bit lines or through the source side select gate to the source line can be measure through circuitry in the column control circuitry 210. … Based on the result of the detection at step 1007, step 1009 determines whether the block is defective.”; a current leak test of figure 10, step 1007 using the source line to detect the leaked current).
Regarding claim 7, Thoppa teaches:
The semiconductor memory device according to claim 4, wherein the controller is configured to make the determination after the first erase operation in the erase sequence is executed, and (Thoppa, fig 6, 7, 8, 9, 10, “[0021] FIG. 6 is a flowchart describing one embodiment of a process 600 for erasing memory cells. [0022] FIG. 7 is a flowchart describing one embodiment for incorporating post-erase defect testing into the process for erasing memory cells. [0023] FIG. 8 is a flow chart for post-erase defect detection mode to determine whether threshold voltages of the select gates of a block have become outside of the desired range. [0024] FIG. 9 is a flowchart describing one embodiment of a process for performing post-erase test mode for NAND strings in a block or sub-block and comparing the even word line result from the erase verify for the sub-block to the odd word line result from a post-erase verify for the sub-block. [0025] FIG. 10 is a flowchart for an embodiment of a post-erase HIVR test mode.”; an “erase operation” and a “first erase operation” do not require any specific steps (such as setting voltage on a word line); they can involve multiple generic steps to include actual transistor erasure, to waiting a time interval, or evaluating a current leakage. Without further limitations, the claim can be broadly interpreted to merely require a “step 1” followed by “step 2”).
after the determination operation is completed, the erase sequence is executed from the erase verification operation. (Thoppa, fig 1, “[0158] The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit to the precise form disclosed. Many modifications and variations are possible in light of the above teaching.”; an explicit statement that the use of the steps does not preclude other modifications as in step 2 can be performed before step 1).
Regarding claim 8, Thoppa teaches:
The semiconductor memory device according to claim 4, wherein the controller is configured to make the determination before the first erase operation in the erase sequence is executed, and (Thoppa, fig 6, 7, 8, 9, 10, “[0021] FIG. 6 is a flowchart describing one embodiment of a process 600 for erasing memory cells. [0022] FIG. 7 is a flowchart describing one embodiment for incorporating post-erase defect testing into the process for erasing memory cells. [0023] FIG. 8 is a flow chart for post-erase defect detection mode to determine whether threshold voltages of the select gates of a block have become outside of the desired range. [0024] FIG. 9 is a flowchart describing one embodiment of a process for performing post-erase test mode for NAND strings in a block or sub-block and comparing the even word line result from the erase verify for the sub-block to the odd word line result from a post-erase verify for the sub-block. [0025] FIG. 10 is a flowchart for an embodiment of a post-erase HIVR test mode.”; an “erase operation” and a “first erase operation” do not require any specific steps (such as setting voltage on a word line); they can involve multiple generic steps to include actual transistor erasure, to waiting a time interval, or evaluating a current leakage. Without further limitations, the claim can be broadly interpreted to merely require a “step 1” followed by “step 2”).
after the determination operation is completed, the erase sequence is executed from the erase operation. (Thoppa, fig 1, “[0158] The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit to the precise form disclosed. Many modifications and variations are possible in light of the above teaching.”; an explicit statement that the use of the steps does not preclude other modifications as in step 2 can be performed before step 1).
Regarding claim 9, Thoppa teaches:
A data erasing method for a semiconductor memory device comprising a plurality of planes, wherein each of the plurality of planes includes at least one or more blocks, the block includes a plurality of memory cells, (Thoppa, fig 1, 2, “[0006] The term “erase block” or “erase group” may be used herein to refer to a group of NAND memory cells that share word lines and are erased together. It is also possible to erase multiple erase blocks together, such as one erase block on each plane on a memory die.”; a memory array with multiple blocks on multiple planes; a controller is used to send commands to erase addressable blocks or sub-blocks, or blocks on different planes).
a source line electrically connected to one end of the plurality of memory cells in the plurality of planes is provided, the data erasing method includes: (Thoppa, fig 6, 7, “[0110] Process 600 describes a double sided erase in which an erase voltage (Vera) is applied at both ends of NAND strings (e.g., bit lines and source line).”; a source line connected to a NAND string which comprises a plurality of memory cells in a block, in a plane; each NAND string comprises a source line).
detecting whether there is a current leak from the source line for each of the erase target blocks selected in each of the plurality of planes, and (Thoppa, fig 6, 7, “[0133] Returning to FIG. 7, the HIVR test mode of step 727 is also directed at determining whether there is current leakage between the word lines and the memory holes, [0134] FIG. 10 is a flowchart for an embodiment of a post-erase HIVR test mode.”; after the erase verify step, an HIVR test mode determines if there is current leakage between word lines and source lines).
determining, based on a detection result, validity of an erase sequence that repeats a plurality of loops including a set of an erase operation that erases data of each of the plurality of memory cells in each of the blocks and an erase verification operation that checks whether the data is erased, and (Thoppa, fig 7, 10, “[0120] At step 711 the block is then erased, followed by erase verification at step 713, and then determine whether the block passes the erase verify at step 715. … More specifically, at step 715, if the block does not pass the erase verify, the blocks status is either set to fail or, in an embodiment with multiple erase pulses with verifies in between, the flow can loop back to the equivalent of a step 615. [0135] Step 1007 determines whether there is word line memory hole leakage… For example, leakage current either though the drain side select gate to the bit lines or through the source side select gate to the source line can be measure through circuitry in the column control circuitry 210.”; an erase sequence the determines the success of an erase operation; that may or may not use a loop; and a current leak test of figure 10, step 1007 using the source line to detect the leaked current).
stopping execution of the erase sequence for the erase target blocks that are determined not to be valid. (Thoppa, fig 7, 10, “[0135] Based on the result of the detection at step 1007, step 1009 determines whether the block is defective. [0136] Returning again to FIG. 7, the shown embodiment includes the three post-erase test modes described above at step 721. [0122] Step 729 determines whether or not the block passes the tests of step 721 and, if not, the block is retired at step 731.”; that the erase sequence of figures 6, 7, and 10 are halted (step 731 of fig 7) if a NAND string fails the current leakage test of step 1007 of figure 10).
Regarding claim 10, Thoppa teaches:
The data erasing method according to claim 9, wherein detecting whether there is a current leak from the source line (Thoppa, fig 6, 7, “[0110] Process 600 describes a double sided erase in which an erase voltage (Vera) is applied at both ends of NAND strings (e.g., bit lines and source line). [0133] Since the larger the voltage difference, the easier it is to detect leakage; and since the control circuitry of a NAND memory can typically apply higher voltage levels to word lines than bit line, the following embodiment sets the word lines to a higher voltage (one of the operating voltage levels available) and the memory hole to a lower level, such as 0V. [0111] Step 602 includes setting an initial magnitude of an erase voltage (Vera). The initial Vera may have a relatively large magnitude such as, for example, 20V.”; a source line connected to a NAND string which comprises a plurality of memory cells in a block, in a plane; each NAND string comprises a source line; that the source and bit lines can be set to a “higher voltage”, or one of the operating voltages available, that Thopps previously disclosed that Vera could be 20V).
further includes measuring the number of operating clocks of a charge pump that supplies voltage to the source line for each of the selected blocks in each of the plurality of planes, between the first erase operation and the first erase verification operation of the erase sequence, and (Thoppa, fig 10, “[0135] Step 1007 determines whether there is word line memory hole leakage once the block is biased according to steps 1001, 1003, and 1005. A number of embodiments are available for this determination. *Alternate, after trapping charge on the word lines for an interval, the voltage levels on the word lines can be measured to see if there has been appreciable discharge from the block’s word lines. In other embodiments, after allow a discharge period for any leaking word lines, a read can be performed of the memory block to see whether one or more word lines have discharged to the extent that they tum off the NAND string.”; a circuit in the column control circuitry that can sense current leakage from the method of figure 10 in step 1007; that the row control circuitry sets the word lines from a separate voltage line).
determining that the erase sequence is not valid in the block where the number of operating clocks exceeds a set threshold. (Thoppa, fig 10, “[0135] Step 1007 determines whether there is word line memory hole leakage once the block is biased according to steps 1001, 1003, and 1005. *Alternate, after trapping charge on the word lines for an interval, the voltage levels on the word lines can be measured to see if there has been appreciable discharge from the block’s word lines. In other embodiments, after allow a discharge period for any leaking word lines, a read can be performed of the memory block to see whether one or more word lines have discharged to the extent that they tum off the NAND string.. … Bases on the result of the detection at step 1007, step 1009 determines whether the block is defective.”; a circuitry in the column control circuitry that can sense current leakage from the method of figure 10 in step 1007; here after a set interval of time (the claimed “clocks”), the voltage levels on the word lines can be measured (the second detection circuit) “to the extent” (a threshold voltage) they turn off the NAND string; then the result of the test is determined in step 1009).
Conclusion
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/Donald HB Braswell/ Primary Examiner, Art Unit 2825