DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office action has been modified in response to amendment filed 1/5/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Deng et al. (US 2022/0310174 hereinafter Deng) in view of Takeuchi et al. (US 2004/0215857 A1 hereinafter Takeuchi).
Regarding claim 1, Deng discloses a memory device (figure 3, 300) comprising: a memory cell array (figure 3, 301) comprising N planes (figure 8, 602), wherein N is a positive integer greater than 1 ([0049], memory device includes 4 memory planes and the number of memory planes can be generally represented as N, where N is an integer greater than 1); and a peripheral circuit (figure 3, 300) coupled to the memory cell array (figure 3, 301) and comprising a host process processor (figure 5, 512) coupled to the memory cell array (figure 5, 301); and N processors corresponding to the N planes, wherein each of the N processors comprises an internal memory ([0052], main MCU 802 can include one or more processing cores that can execute firmware and/or software codes stored in a memory 806 coupled to main MCU 802 or as part thereof), wherein the N processors comprise one master processor and N-1 slave processors, and N-1 internal memories corresponding to the N-1 slave processors ([0048]-[0050], control logic 512 includes a main MCU 802 and a plurality of AMPI read units 804, and interface 516, and control logic 512 of memory device 800 in FIG. 8 represents an example of a “1+(N−1)” architecture in general in performing AMPI read operations and non-AMPI read operations on N memory planes, where “1” represents a single main MCU 802, and “N−1” represents the number of multiple AMPI read units 804). Deng differs from the claimed invention in not specifically disclosing a host process processor coupled to the memory cell array and a bus, wherein the N processors comprise one master processor and N-1 slave processors, and N-1 internal memories corresponding to the N-1 slave processors have a same bus address. However, Takeuchi teaches a multiprocessor system which conducts data transfer through a shared bus in order to efficiently execute data transfer between the processor elements such that a host process processor coupled to a bus (figure 1), and a processor element operating as a master of the first shared bus and selectively outputs the signal to the first shared bus in response to a signal corresponding to right to use bus for the first shared bus (figure 3 and [0080]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Deng in having that the N processors comprise one master processor and N-1 slave processors, and N-1 internal memories corresponding to the N-1 slave processors have a same bus address, as per teaching of Takeuchi, in order to efficiently execute data transfer between the processor elements.
Regarding claim 2, Deng discloses that the N-1 slave processors are configured to: simultaneously receive instruction set data through a bus in a reset operation process; and provide asynchronous multi-plane independent (AMPI) read control signals for a respective plane based on the instruction set data in an AMPI read operation process ([0071]-[0073], main MCU 802 or AMPI read unit 804 of control logic 512 in memory device 800 may generate an AMPI read control signal based on the AMPI read instruction in response to the instruction being an AMPI read instruction, and the operations may be performed simultaneously).
Regarding claim 3, Deng discloses that the internal memory corresponding to the master processor is coupled to the bus, and a bus address of the internal memory corresponding to the master processor is a first bus address; and the N-1 internal memories corresponding to the N-1 slave processors are interconnected and coupled to the bus, and a bus address of each of the N-1 internal memories corresponding to the N-1 slave processors is a second bus address (figure 9A, [0052] and [0055], main MCU 802 can include one or more processing cores (e.g., arithmetic-logic units (ALUs)) that can execute firmware and/or software codes stored in a memory 806 coupled to main MCU 802, and each AMPI read unit 804 includes an MCU 902 and a memory 904 coupled to MCU 902).
Regarding claim 4, Deng discloses that the host process processor is configured to: acquire, in response to a reset instruction, instruction set data from the memory cell array; send, through the bus, a first instruction set data of the instruction set data into the master processor, wherein the first instruction set data matched with the first bus address; and simultaneously send a second instruction set data of the instruction set data into the N-1 slave processors, wherein the second instruction set data matched with second bus address ([0029] and [0071]-[0073], memory controller 106 can be configured to control operations of memory device 104, such as read, erase, and program operations by sending instructions, such as SMPI read instruction, AMPI read instruction, erase instruction, and program instruction, to memory device 104, and main MCU 802 or AMPI read unit 804 of control logic 512 in memory device 800 may generate an AMPI read control signal based on the AMPI read instruction in response to the instruction being an AMPI read instruction, and the operations may be performed simultaneously).
Regarding claim 5, Deng discloses that the master processor is configured to: provide an AMPI read control signal for a plane corresponding to the master processor in an AMPI read operation process, and provide a non-AMPI read control signal for each of the N planes in a non-AMPI read operation; the peripheral circuit further comprises a multiplexing circuit; and the multiplexing circuit is coupled to the N processors and the N planes, and is configured to: output each of N AMPI read control signals from a corresponding one of the N processors to a respective plane in the AMPI read operation process, and output the non-AMPI read control signal from the master processor to each of the N planes in the non-AMPI read operation ([0048] and [0051]-[0052], memory device 800 can include peripheral circuits including control logic 512, interface 516, registers 514, and a multiplexing circuit (MUX) 808, as well as a plurality of memory planes 602, and main MCU 802 is configured to provide an AMPI read control signal for one of memory planes 602 (e.g., plane 0) to control an AMPI read operation on memory plane 602 (e.g., plane 0), as well as provide a non-AMPI read control signal for each memory plane 602 (e.g., plane 0, 1, 2, or 3) to control a non-AMPI read operation on each memory plane 602).
Regarding claim 6, Deng discloses that the peripheral circuit further comprises an interface; and the interface (figure 8, 516) is coupled to the multiplexing circuit (figure 8, 808), and is configured to: control the multiplexing circuit to output each of the N AMPI read control signals from a corresponding processor to the respective plane in the AMPI read operation process, and output the non-AMPI read control signal from the master processor to each of the N planes in the non-AMPI read operation process (figure 8, [0044] and [0051], interface 516 can be coupled to control logic 512 and act as an instruction fetcher/buffer as well as an instruction decoder to decode instructions received from a memory controller and relay the decoded instructions to control logic 512, and main MCU 802 can have at least dual roles: (1) acting as an AMPI read unit responsible for handling the AMPI read operation control of a respective memory plane 602, e.g., plane 0, and (2) acting as a control unit for handling any non-AMPI read operation control of each memory plane 602).
Regarding claim 7, Deng discloses that each of the N planes is configured to independently and asynchronously perform a read operation in response to receiving the AMPI read control signal; and independently and synchronously perform the read operation in response to receiving a synchronous multi-plane independent (SMPI) read control signal ([0029] and [0043], memory controller 106 can be configured to control operations of memory device 104, such as read, erase, and program operations by sending instructions, such as SMPI read instruction, AMPI read instruction, erase instruction, and program instruction, to memory device 104 and control logic 512 can include a main MCU and multiple AMPI read units in different architectures and implementations to control the AMPI read operations and non-AMPI read operations of multiple memory planes independently).
Regarding claim 8, Deng discloses that the multiplexing circuit comprises N multiplexers, a first input end of each of the N multiplexers is configured to receive the non-AMPI read control signal from the master processor, a second input end of each multiplexer is configured to receive the AMPI read control signal from one of the N processors ([0059], each MUX can include an output coupled to a respective memory plane 602, a first input receiving the non-AMPI read control signal from main MCU 802, and a second input receiving the AMPI read control signal from respective AMPI read unit 804).
Regarding claim 9, Deng discloses that the interface (figure 8, 516) comprises an instruction decoder (figure 8, 810) configured to: control, in response to receiving an AMPI read instruction, the N processors to generate a corresponding AMPI read control signal based on the AMPI read instruction, and control the multiplexer to output a corresponding AMPI read control signal received from the second input end; and the instruction decoder is further configured to: control, in response to receiving a non-AMPI read instruction, the master processor to generate the non-AMPI read control signal based on the non-AMPI read instruction, and control each multiplexer to output the non-AMPI read control signal received from the first input end ([0062]-[0063], instruction decoder 810 controls main MCU 802 to generate the non-AMPI read control signal based on the decoded non-AMPI read instruction in response to obtaining a non-AMPI read instruction upon decoding and instruction decoder 810 can cause main MCU 802 or AMPI read unit 804 to provide the AMPI read control signal to a corresponding memory plane 602 when performing an AMPI read operation).
Regarding claim 10, Deng discloses that each of the N-1 slave processors is configured with a corresponding register group, and N-1 register groups corresponding to the N-1 slave processors have different bus addresses ([0058], registers 514 are organized as one or more register files that can be accessed by main MCU 802 and each AMPI read unit 804).
Regarding claim 11, Deng discloses that the internal memory comprises a random access memory (RAM) ([0052], memory 806 can include any suitable read-only memory (ROM) and/or random-access memory (RAM) for storing the firmware and/or software codes implementing the functions of main MCU 802).
Regarding claim 12, the limitations of the claim are rejected as the same reasons as set forth in claim 1. In addition, Deng discloses that the memory system, comprising: one or more memory devices (figure 1, 104), and a memory controller (figure 1, 106) coupled to the memory device and configured to control the memory devices ([0029]).
Regarding claim 13, the limitations of the claim are rejected as the same reasons as set forth in claim 2.
Regarding claim 14, the limitations of the claim are rejected as the same reasons as set forth in claim 3.
Regarding claim 15, the limitations of the claim are rejected as the same reasons as set forth in claim 4.
Regarding claim 16, the limitations of the claim are rejected as the same reasons as set forth in claim 5.
Regarding claim 17, the limitations of the claim are rejected as the same reasons as set forth in claims 1-2.
Regarding claim 18, the limitations of the claim are rejected as the same reasons as set forth in claim 4.
Regarding claim 19, the limitations of the claim are rejected as the same reasons as set forth in claim 3.
Regarding claim 20, the limitations of the claim are rejected as the same reasons as set forth in claim 5.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments filed 1/5/2026 have been fully considered but they are not persuasive.
In response to applicant's argument that the references fail to show peripheral circuit coupled to the memory cell array and comprising a host process processor, Examiner respectfully disagreed because Deng discloses peripheral circuits 302 coupled to memory cell array 301 as shown in figure 3, and peripheral circuits including control logic 512, interface 516, registers 514, and a multiplexing circuit (MUX) 808, as well as a plurality of memory planes 602 ([0048]) such that the peripheral circuit comprising a host process processor. Therefore, the combination of Deng and Takeuchi teaches the claimed limitations.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Pollio et al. (US 11,238,940 B1) discloses a memory system may include a memory array on a first die and a controller on a second die, where the second die is coupled with the first die, wherein the controller may perform an initialization procedure based on operating instructions stored within the memory system (abstract and figure 1).
Kim (US 11,373,709 B2) discloses a plurality of memory systems may be divided into a master and a slave using a position or a dip switch that switches the plurality of memory systems when the plurality of memory systems are connected to a single host (figure 1 and col. 16 lines 20-44).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHUO H LI whose telephone number is (571)272-4183. The examiner can normally be reached Mon. Tue. and Thurs. 8:00-4:00 PM.
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/ZHUO H LI/Primary Examiner, Art Unit 2133