Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office acknowledges receipt of the following items from the Applicant:
Information Disclosure Statement (IDS) filed on 3/31/26, 2/20/26, 1/28/26, 1/02/26, 12/10/25, 11/19/25, 11/11/25, 09/22/25, 9/11/25, 6/17/25, 6/12/25, 5/27/25, 4/30/25, 4/24/25, 03/26,25, 2/05/25, 1/02/25, 12/27/24, 11/14/24, 09/27/24, 08/28/24, 7/23/24 were considered.
Claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1-4, 8-10, 14-15 and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shin et al, U.S. Patent No. 11,568,917.
Regarding to claims 1, 8, and 15, Shin discloses an apparatus (fig. 1, semiconductor memory device 100) comprising: an targeted refresh queue configured store a row address responsive to an aggressor signal of which the candidate aggressor row address count storage includes n entries (i.e. that is, the plurality of n entries constitutes a queue or list of row addresses (col. 1, line 53-58) (also with regard to claim 14 and 20); an aggressor detector circuit (fig. 5, hammer refresh row address detector 28) configured to provide the aggressor signal (fig. 5, HRFF), cara, hcnt) after a first number of times that the row address is accessed in a first mode and configured to provide the aggressor signal after a second number of times that the row address is accessed in a second mode (operating in a threshold-based detection mode and set/reset window/operation period) (different operational phases: reset window vs active detection, thus they are operating in different functional modes (i.e. first mode and second mode) ((col. 3, line 57-62) (col. 4, line 18-21) (col. 4, line 39-59).
With regard to claim 2 and 19, Shin discloses, wherein the aggressor detector circuit (fig. 1, 10) includes a test circuit (fig. 1, control logic 2) configured to change the behavior of the aggressor detector circuit based on a state of a test mode enable signal, wherein the test mode enable signal is in a first state in the first mode and a second state in the second mode (col. 4, line 12-24) and col. 9, line 1-14).
With regard to claim 3 and 9, Shin discloses wherein the aggressor detector circuit comprises: a counter circuit (fig. 2, count storage 4) configured to change a count value associated with the row address responsive to the row address being accessed (col. 4, line 27-38); and a comparator circuit (fig. 3B, S34) configured to compare the changed count value to a threshold and provide the aggressor signal if the changed count value has crossed the threshold.
With regard to claim 4 and 10, Shin discloses does not discloses wherein the aggressor detector circuit further comprises: a multiplexer configured to provide a first value as the threshold in the first mode or a second value as the threshold in the second mode of which is a selection logic. However, the selection logic can inherently be replace by a multiplexer.
Allowable Subject Matter
Claims 5-7, 11-13 and 16-18 are objected as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art of record does not show the limitation of wherein the aggressor detector circuit further a multiplexer configured to provide the most significant bits of the count value as a comparison value in the first mode or the least significant bits of the count value as the comparison value in the second mode, wherein the comparator circuit is configured to compare the comparison bits to the most significant bits of the threshold.
Prior art of record does not show the limitation of wherein the counter circuit is configured to change the count value by adding a first value to the count value in the first mode or by adding a second value to the count value in the second mode.
Prior art of record does not show the limitation of further comprising: the method of comparing a first portion of the changed count value to a first portion of the threshold in the first mode or comparing a second portion of the changed count value to the first portion of the threshold in the second mode
Prior art of record does not show the limitation of the method further comprising: changing the count value by adding a fist value to the count value in the first mode or by adding a second value to the count value in the second mode.
Prior art of record does not show the limitation of wherein the first mode is a normal operational mode and the second mode is a per row activation counter test (PRACT) mode.
Prior art of record does not show the limitation of further comprising: an oscillator counter circuit configured to provide an access time signal, wherein the access time signal has a value based on a count of oscillations of an oscillating signal in the first mode and wherein the access time signal has a fixed value in the second mode, wherein the counter circuit is configured to add the access time signal to the count value to generate the updated count value
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicants’ disclosure. Roberts (11810612).
The present disclosure is drawn to apparatuses, systems, and methods for PRAC testing (PRACT). A memory may be placed in a PRACT mode. During the PRACT mode, a PRACT circuit changes the operation of an aggressor detector circuit so that fewer activations are required to add a word line’s address to the aggressor queue than when the PRACT mode is disabled. In this manner, the device may be placed in a PRACT mode, and test activations may be sent which will relatively quickly add the address to the queue (or not, depending on the outcome of the test).
However, Roberts’ is drawn to apparatuses, systems, and methods for row hammer based cache lockdown. The controller (and/or memory) may include a cache. A set of the most recent data accessed from the memory may be stored in the cache, which may allow more rapid access to recently accessed information. Information stored in the cache may not be susceptible to the row hammer effect (or may be less susceptible). The controller may include logic, which may determine a number of times (and/or a rate) at which an identified row of the memory (e.g., an aggressor row) is accessed. If the number of times (and/or rate) is above a first threshold, the controller may manage the entry in the cache associated with an address associated with the identified row. For example, the cache may be managed in such a way as to ensure that the data associated with the identified row remains in the cache for at least a minimum amount of time.
A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the date of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Connie Yoha, whose telephone number is (571) 272-1799. The examiner can normally be reached on Mon. - Fri. from 8:00 A.M. to 5:30 PM. The examiner's supervisor, Alexander Sofocleous, can be reached at (571) 272-0635. The fax phone number for this Group is (571) 273-8300.
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/CONNIE C YOHA/Primary Examiner, Art Unit 2825
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