DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I in the reply filed on 11/17/2025 is acknowledged.
Claims 4-5, 7-8,14-16 and 18-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species II, III and IV, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 11/17/2025.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 9-12 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chuang et al. (US 2021/0211128).
In regards to claim 1, Chuang discloses of a logic gate circuit comprising: a first N-type transistor circuit having a first terminal, a second terminal, and a third terminal, wherein the first N-type transistor circuit includes at least one N-type transistor (MH1); a second N-type transistor circuit having a fourth terminal and a fifth terminal, wherein the fourth terminal is coupled to the third terminal and the second N-type transistor circuit includes at least one N-type transistor (ML1); a capacitor (MC1) coupled between the first terminal and the third terminal; and a clamping circuit (102) coupled to the first terminal and configured to clamp a voltage of the first terminal (see Figs 2-5 and Paragraphs 0037-0058).
In regards to claim 3, Chuang discloses of the logic gate circuit according to claim 1, wherein the second N-type transistor circuit comprises an N-type enhancement-mode GaN transistor (ML1) having a gate, a drain, and a source and the gate, the drain, and the source are respectively coupled to a control signal, the fourth terminal, and the fifth terminal (see Figs 2-5 and Paragraph 0029, ML1 illustrated as an enhancement-mode transistor).
In regards to claim 9, Chuang discloses of a power chip, comprising: a driver portion; a switch portion; and an electric connection portion electrically connecting the driver portion and the switch portion (see Fig 1), wherein the driver portion comprises: a first N-type transistor circuit having a first terminal, a second terminal, and a third terminal, wherein the first N-type transistor circuit includes at least one N-type transistor (MH1); a second N-type transistor circuit having a fourth terminal and a fifth terminal, wherein the fourth terminal is coupled to the third terminal and the second N-type transistor circuit includes at least one N-type transistor (ML1); a capacitor (MC1) coupled between the first terminal and the third terminal; and a clamping circuit (102) coupled to the first terminal and configured to clamp a voltage of the first terminal (see Figs 1-5 and Paragraphs 0025-0058).
In regards to claim 10, Chuang discloses of the power chip according to claim 9, further comprising a substrate for carrying the driver portion and the switch portion (for example see at least Paragraph 0008, 0029, 0033, 0035, 0041, 0043, devices are constructed of semiconductor elements that would have substrates for carrying them).
In regards to claim 11, Chuang discloses of the power chip according to claim 9, wherein the driver portion comprises a first semiconductor material and the switch portion comprises a second semiconductor material, and the first semiconductor material and the second semiconductor material are the same (for example see Paragraphs 0008, 0029, 0035, 0041).
In regards to claim 12, Chuang discloses of the power chip according to claim 11, wherein the first semiconductor material comprises GaN series semiconductor (see Paragraphs 0008, 0029, 0035, 0041).
In regards to claim 20, Chuang discloses of the power chip according to claim 10, wherein the substrate comprises a growth substrate or a bonding substrate (for example see at least Paragraph 0008, 0029, 0033, 0035, 0041, 0043, devices are constructed of semiconductor elements that would have either growth or bonding substrates).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Chuang et al. (US 2021/0211128) in view of Kinzer et al. (US 2019/0148961).
In regards to claims 2 and 13, Chuang discloses of the logic gate circuit according to claim 1 and the power chip according to claim 9 as found within the respective explanations above, wherein the first N-type transistor circuit comprises an N-type enhancement-mode GaN transistor (MH1, see Paragraph 0029) having a gate, a drain, and a source and the gate, the drain, and the source are respectively coupled to the first terminal, the second terminal, and the third terminal (see Figs 2-5 and Paragraph 0029).
However, Chuang does not explicitly disclose of wherein the first N-type transistor circuit comprises an N-type depletion-mode GaN transistor.
Kinzer discloses of a logic gate circuit comprising: a first N-type transistor circuit having a first terminal, a second terminal, and a third terminal, wherein the first N-type transistor circuit includes at least one N-type transistor (125); a second N-type transistor circuit having a fourth terminal and a fifth terminal, wherein the fourth terminal is coupled to the third terminal and the second N-type transistor circuit includes at least one N-type transistor (115); wherein the first N-type transistor circuit comprises an N-type enhancement-mode GaN transistor or a N-type depletion-mode GaN transistor having a gate, a drain, and a source and the gate, the drain, and the source are respectively coupled to the first terminal, the second terminal, and the third terminal (see Fig 1 and Paragraph 0097).
It would have been obvious to one of ordinary skill in the art to have the first N-type transistor circuit comprising an N-type depletion-mode GaN transistor as taught by Kinzer for reducing fabrication costs by limiting the device to N-type transistors and protect and improving efficiency by utilizing a depletion-mode transistor.
Allowable Subject Matter
Claims 6 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
In regards to claim 6, the prior art does not explicitly disclose of the logic gate circuit according to claim 1, wherein the clamping circuit comprises: an N-type transistor having a drain, a source, and a gate, wherein the drain is coupled to the first terminal and the gate is coupled to the third terminal; and a biasing voltage source coupled to the source and configured to provide a biasing voltage for the source, nor would it have been obvious to one of ordinary skill in the art to do so.
In regards to claim 17, the prior art does not explicitly disclose of the power chip according to claim 9, wherein the clamping circuit comprises: an N-type transistor having a drain, a source, and a gate, wherein the drain is coupled to the first terminal and the gate is coupled to the third terminal; and a biasing voltage source coupled to the source and configured to provide a biasing voltage for the source,, nor would it have been obvious to one of ordinary skill in the art to do so.
Conclusion
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/JASON M CRAWFORD/Primary Examiner, Art Unit 2844