DETAILED ACTION
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
Applicant’s arguments filled 07/24/2026 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-7, 9-18, 20 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Abboud(US 5179712 A) in view of Halma(US 5907684 A)
Regarding claim 1, Abboud discloses
A method for ordered statistics constant false alarm rate (OS-CFAR) detection (“a number ranking circuit for an OS CFAR detector circuit “ [(Col.2, ll.46-47]), comprising: storing, at storage circuitry comprising a plurality of storage segments (“ranking circuitry is provided which includes a number of identically structured rank cells for storing and ranking sample values” [Col.2, ll.64-66]) address data (FIG.2, Parts RC1-RC8)[…]; and performing a sorting algorithm for OS-CFAR detection comprising the steps of: comparing a new data element of the radar data to at least one data element indicated by address data (“a new sample VIN is added to the rank array RC1 . . . RC8, the new sample VIN is compared to the sample VQ in each of the other rank cells RC1 . . . RC8” [Col.4, ll.58-61]) […], determining a storage segment of the plurality of storage segments at which address data of the new data element is to be stored based on the comparing (“The signals in the rank cells RC1 . . . RC8 are then shifted in a manner such that there exists a vacancy for the new sample VIN “ [Col.4, ll.61-64]), and controlling the storage circuitry to shift address data stored at the determined storage segment to another storage segment (“ all signals are once again ranked in descending order after the new sample VIN has been inserted into the vacant rank cell.” [Col.4, ll.64-66]).
Abboud does not explicitly disclose nor limit wherein the address data indicates the addresses of data elements of radar data stored at a further storage circuitry. Halma discloses, address data indicating addresses of data elements of radar data stored at a further storage circuitry that is separate from the storage circuitry (“the indexed logical address comprises a pointer into the logical address table which contains the actual image identifier concatenated with the process node identifier at the channel end of the link in a channel path” [Col.6, ll.50-53]), wherein each portion of the address data has a smaller bit- width than the data element of the radar data indicated by that portion of the address data (“said indexed logical address having less bits than a concatenation of said Image.sub.-- ID and said PN.sub.-- ID.” [CLM. 25])
Halma teaches in the same field of data processing systems. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Abboud with the teachings of Halma to incorporate the features of storing addresses of data elements of radar data at a further storage circuitry so as to gain the advantage of improving information retrieval efficiency. Also, since it has been held that if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill (MPEP 2143).
Regarding claim 2, Abboud as modified by Halma discloses all the limitations of claim 1. Abboud discloses the method further comprising, controlling the storage circuitry to store the address data of the new data element at the determined storage segment (“ the input sample value VIN, the sample value VQN stored in the next succeeding rank cell RC(N+1)” [Col.6, ll.5-7]).
Regarding claim 3, Abboud as modified by Halma discloses all the limitations of claim 1. Abboud discloses the method further comprising, controlling the storage circuitry to shift all address data stored in storage segments subsequent or previous to the determined storage segment by a predefined number of storage segments (“The signals in the rank cells RC1 . . . RC8 are then shifted in a manner such that there exists a vacancy for the new sample VIN such that all signals are once again ranked in descending order after the new sample VIN has been inserted into the vacant rank cell” [Col.4, ll.61-66]).
Regarding claim 4, Abboud as modified by Halma discloses all the limitations of claim 1. Abboud discloses wherein performing the sorting algorithm comprises performing an insertion sort for OS-CFAR detection (“the insertion of "38" into the window and the extraction of "59" from the window” [Col.4, ll. 21-25] & FIG.2).
Regarding claim 5, Abboud as modified by Halma discloses all the limitations of claim 1. Abboud discloses the method further comprising: performing the sorting algorithm for a first window of data elements of the radar data (“The input VIN is the sample entering the sorting window. The VIN input is provided to each rank cell RC1 . . . RC8 on a respective line 15” [Col.3, ll.34-36]); after the sorting algorithm for the first window is performed, selecting a second window of data elements of the radar data (“The rank cells RC1 . . . RC8 may be cleared or reset by placing a sample value of zero in each rank cell RC1 . . . RC8. To build up the window size after such a reset, as shown in FIG. 4, video samples must be inserted into the window one at a time, while at the same time extracting zero amplitude samples.” [Cpl.4, ll.42-48]); and performing the sorting algorithm for the second window by removing a portion of the address data stored in the storage circuitry during performance of the sorting algorithm for the first window, wherein the portion of the address data is less than an entirety of the address data (“FIG. 5 illustrates a method of reducing the window size utilizing the rank cell array of the preferred embodiment. In this method, zero is inserted into the window, while, at the same time, one of the video samples is extracted from the window.” [Col.4, ll.48-52])
Regarding claim 6, Abboud as modified by Halma discloses all the limitations of claim 5. Abboud discloses the method further comprising performing the sorting algorithm for the second window by controlling the storage circuitry to exclusively insert address data of data elements of the second window which has not been inserted during performance of the sorting algorithm for the first window data (“During a clock cycle wherein a new sample VIN is added to the rank array RC1 . . . RC8, the new sample VIN is compared to the sample VQ in each of the other rank cells RC1 . . . RC8.” [Cpl.4, ll.57-61])
Regarding claim 7, Abboud as modified by Halma discloses all the limitations of claim 1. Abboud discloses the method further comprising, after performing the sorting algorithm: selecting a data element indicated by address data stored at a predefined storage segment of the plurality of storage segments (“Selects the sample which has a Predetermined Rank (RT) from the sample set”[Col.1, ll.48-49]); comparing the selected data element to a data element under test (“The amplitude of this sample is used as a basis for setting the Target Detection Threshold.”[Col.1, ll.49-51]); and determining a presence of a target or a motion of the target based on the comparing (“Inputs all video samples within N/2 samples on either side of the sample cell which is being examined for the presence or absence of a Target” [Col.1, ll.40-42]).
Regarding claim 9, Abboud discloses
An apparatus, comprising: storage circuitry comprising a plurality of storage segment (“ranking circuitry is provided which includes a number of identically structured rank cells for storing and ranking sample values” [Col.2, ll.64-66]s, wherein the storage circuitry is configured to store address data (FIG.2, Parts RC1-RC8) […]; and control circuitry comprising a processor and a memory coupled to the processor with instructions stored thereon (“Each pass requires moving data among locations in memory and comparing operations in an arithmetic logic unit (ALU)” [Col.2, ll.1-3]), wherein the instructions, when executed by the processor, enable the apparatus to perform a sorting algorithm for ordered statistics constant false alarm rate (OS-CFAR) detection (“a new sample VIN is added to the rank array RC1 . . . RC8, the new sample VIN is compared to the sample VQ in each of the other rank cells RC1 . . . RC8” [Col.4, ll.58-61])comprising: comparing a new data element of the radar data to at least one data element indicated by address (“a new sample VIN is added to the rank array RC1 . . . RC8, the new sample VIN is compared to the sample VQ in each of the other rank cells RC1 . . . RC8” [Col.4, ll.58-61]) […], determining a storage segment of the plurality of storage segments at which address data of the new data element is to be stored based on the comparing (“The signals in the rank cells RC1 . . . RC8 are then shifted in a manner such that there exists a vacancy for the new sample VIN “ [Col.4, ll.61-64]), and controlling the storage circuitry to shift address data stored at the determined storage segment to another storage segment (“ all signals are once again ranked in descending order after the new sample VIN has been inserted into the vacant rank cell.” [Col.4, ll.64-66]).
Abboud does not explicitly disclose nor limit wherein the address data indicates the addresses of data elements of radar data stored at a further storage circuitry. Halma discloses, address data indicating addresses of data elements of radar data stored at a further storage circuitry that is separate from the storage circuitry (“the indexed logical address comprises a pointer into the logical address table which contains the actual image identifier concatenated with the process node identifier at the channel end of the link in a channel path” [Col.6, ll.50-53]), wherein each portion of the address data has a smaller bit-width than the data element of the radar data indicated by that portion of the address data (“said indexed logical address having less bits than a concatenation of said Image.sub.-- ID and said PN.sub.-- ID.” [CLM. 25])
Halma teaches in the same field of data processing systems. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Abboud with the teachings of Halma to incorporate the features of storing addresses of data elements of radar data at a further storage circuitry so as to gain the advantage of improving information retrieval efficiency. Also, since it has been held that if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill (MPEP 2143).
Regarding claim 10, Abboud as modified by Halma discloses all the limitations of claim 9. Abboud discloses, when executed by the processor, further enable the apparatus to control the storage circuitry to store the address data of the new data element at the determined storage segment (“ the input sample value VIN, the sample value VQN stored in the next succeeding rank cell RC(N+1)” [Col.6, ll.5-7]).
Regarding claim 11, Abboud as modified by Halma discloses all the limitations of claim 9. Abboud discloses, when executed by the processor, further enable the apparatus to control the storage circuitry to shift all address data stored in storage segments subsequent or previous to the determined storage segment by a predefined number of storage segments (“The signals in the rank cells RC1 . . . RC8 are then shifted in a manner such that there exists a vacancy for the new sample VIN such that all signals are once again ranked in descending order after the new sample VIN has been inserted into the vacant rank cell” [Col.4, ll.61-66]).
Regarding claim 12, Abboud as modified by Halma discloses all the limitations of claim 9. Abboud discloses, wherein the instructions, when executed by the processor, enable the apparatus to perform an insertion sort for OS-CFAR detection (“the insertion of "38" into the window and the extraction of "59" from the window” [Col.4, ll. 21-25] & FIG.2).
Regarding claim 13, Abboud as modified by Halma discloses all the limitations of claim 9. Abboud discloses, wherein the storage circuitry comprises a parallel (“Such a simultaneous insertion and extraction of zero into the rank cells RC1 . . . RC8 is shown in FIG. 6.” [Col.4, ll.55-57]) shift register (“Each rank cell RC1 . . . RC8 contains logic which determines which sample will be clocked into its own internal sample storage register“ [Col.5, ll.19-21]) coupling the plurality of storage segments in a cascade (“a number of rank cell logic arrays, each identical to that disclosed in FIG. 1, may be connected together or ‘cascaded.’” [Col.3, ll.57-59])
Regarding claim 14, Abboud as modified by Halma discloses all the limitations of claim 13. Abboud discloses, wherein: the plurality of storage segments (“FIG. 7 discloses the structure of a rank cell RCN” [Col.5, ll.64]) are coupled to respective multiplexers (“a multiplexer (MUX) 49” [Col.5, ll.68]); and each multiplexer of the multiplexers comprises: a first input node coupled to a respective output node of a first one of a previous storage segment or a subsequent storage segment in the cascade (“The inputs A, B, C, D to the MUX 49 are, respectively, the sample value VQP from the preceding rank cell RC(N-1),” [Col.6, ll.3-5]), and a second input node coupled to a data input (“ the sample value VQN stored in the next succeeding rank cell RC(N+1)” [Col.6, ll.5-7]).
Regarding claim 15, Abboud as modified by Halma discloses all the limitations of claim 14. Abboud discloses, wherein each multiplexer of the multiplexers further comprises a third input node coupled to a respective output node of a second one of the previous storage segment or the subsequent storage segment in the cascade (“ the sample value VQN stored in the next succeeding rank cell RC(N+1)” [Col.6, ll.5-7]).
Regarding claim 16, Abboud as modified by Halma discloses all the limitations of claim 9. Abboud discloses, wherein the instructions, when executed by the processor, further enable the apparatus to: perform the sorting algorithm for a first window of data elements of the radar data (“The input VIN is the sample entering the sorting window. The VIN input is provided to each rank cell RC1 . . . RC8 on a respective line 15” [Col.3, ll.34-36]); after the sorting algorithm for the first window is performed, select a second window of data elements of the radar data (“The rank cells RC1 . . . RC8 may be cleared or reset by placing a sample value of zero in each rank cell RC1 . . . RC8. To build up the window size after such a reset, as shown in FIG. 4, video samples must be inserted into the window one at a time, while at the same time extracting zero amplitude samples.” [Cpl.4, ll.42-48]); and perform the sorting algorithm for the second window by removing a portion of the address data stored in the storage circuitry during performance of the sorting algorithm for the first window wherein the portion of the address data is less than an entirety of the address data. (“FIG. 5 illustrates a method of reducing the window size utilizing the rank cell array of the preferred embodiment. In this method, zero is inserted into the window, while, at the same time, one of the video samples is extracted from the window.” [Col.4, ll.48-52]).
Regarding claim 17, Abboud as modified by Halma discloses all the limitations of claim 16. Abboud discloses, wherein the instructions, when executed by the processor, further enable the apparatus to perform the sorting algorithm for the second window by controlling the storage circuitry to exclusively insert address data of data elements of the second window which has not been inserted during performance of the sorting algorithm for the first window (“During a clock cycle wherein a new sample VIN is added to the rank array RC1 . . . RC8, the new sample VIN is compared to the sample VQ in each of the other rank cells RC1 . . . RC8.” [Cpl.4, ll.57-61]).
Regarding claim 18, Abboud as modified by Halma discloses all the limitations of claim 9. Abboud discloses, wherein the instructions, when executed by the processor, further enable the apparatus to, after performing the sorting algorithm: select a data element indicated by address data stored at a predefined storage segment of the plurality of storage segments (“Selects the sample which has a Predetermined Rank (RT) from the sample set”[Col.1, ll.48-49]); compare the selected data element to a data element under test (“The amplitude of this sample is used as a basis for setting the Target Detection Threshold.”[Col.1, ll.49-51]); and determine a presence of a target or a motion of the target based on the comparing (“Inputs all video samples within N/2 samples on either side of the sample cell which is being examined for the presence or absence of a Target” [Col.1, ll.40-42]).
Regarding claim 20, Abboud as modified by Halma discloses all the limitations of claim 9. Abboud discloses, a radar system, comprising: the apparatus according to claim 9; and a radar sensor (“radars which employ OS CFAR detection “[Col.1, ll.13-14]) configured to generate the radar data (“Inputs all video samples “ [Col.1, ll.40]).
Regarding claim 23, Abboud discloses,
An apparatus, comprising: storage circuitry comprising a plurality of storage segments (“ranking circuitry is provided which includes a number of identically structured rank cells for storing and ranking sample values” [Col.2, ll.64-66]), wherein the storage circuitry is configured to store address data (FIG.2, Parts RC1-RC8) […]; and control circuitry configured to perform a sorting algorithm for ordered statistics constant false alarm rate (OS-CFAR) detection (“a number ranking circuit for an OS CFAR detector circuit “ [(Col.2, ll.46-47]) using the steps of: comparing a new data element of the radar data to at least one data element indicated by address data (“a new sample VIN is added to the rank array RC1 . . . RC8, the new sample VIN is compared to the sample VQ in each of the other rank cells RC1 . . . RC8” [Col.4, ll.58-61]) […], determining a storage segment of the plurality of storage segments at which address data of the new data element is to be stored based on the comparing (“The signals in the rank cells RC1 . . . RC8 are then shifted in a manner such that there exists a vacancy for the new sample VIN “ [Col.4, ll.61-64]), and controlling the storage circuitry to shift address data stored at the determined storage segment to another storage segment (“ all signals are once again ranked in descending order after the new sample VIN has been inserted into the vacant rank cell.” [Col.4, ll.64-66]).
Abboud does not explicitly disclose nor limit wherein the address data indicates the addresses of data elements of radar data stored at a further storage circuitry. Halma discloses, address data indicating addresses of data elements of radar data stored at a further storage circuitry that is separate from the storage circuitry (“the indexed logical address comprises a pointer into the logical address table which contains the actual image identifier concatenated with the process node identifier at the channel end of the link in a channel path” [Col.6, ll.50-53]), wherein each portion of the address data has a smaller bit-width than the data element of the radar data indicated by that portion of the address data (“said indexed logical address having less bits than a concatenation of said Image.sub.-- ID and said PN.sub.-- ID.” [CLM. 25])
Halma teaches in the same field of data processing systems. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Abboud with the teachings of Halma to incorporate the features of storing addresses of data elements of radar data at a further storage circuitry so as to gain the advantage of improving information retrieval efficiency. Also, since it has been held that if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill (MPEP 2143).
Claims 8, 19, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Abboud(US5179712A) as modified by Halma(US 5907684 A) as applied to claims 1 and 9 above, and further in view of Will(US20210349203A1).
Regarding claim 8, Abboud as modified by Halma discloses all the limitations of claim 7. Abboud as modified by Halma do not appear to explicitly disclose sending an interrupt to processing circuitry in response to presence or motion detection. Will discloses the method further comprising, in response to determining presence of the target or the motion of the target, sending an interrupt to processing circuitry to trigger further processing of the radar data (“when a human target remains in static state 408 for longer than a predetermined period of time (e.g., such as 10 frames), processor 104 may determine vital signs of such human target (such as heartbeat rate and/or respiration rate) while the target remains in static state 408” [0188])
Will teaches in the same field of OS-CFAR systems. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Abboud as modified by Halma with the teachings of Will to incorporate the features of sending an interrupt to processing circuitry in response to presence or motion detection so as to gain the advantage of reducing computational effort [0165, Will]. Also, since it has been held that if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill (MPEP 2143).
Regarding claim 19, Abboud as modified by Halma discloses all the limitations of claim 18. Abboud as modified by Halma do not appear to explicitly disclose sending an interrupt to processing circuitry in response to presence or motion detection. Will discloses, wherein the instructions, when executed by the processor, further enable the apparatus to, in response to determining presence of the target or the motion of the target, send an interrupt to processing circuitry to trigger further processing of the radar data (“when a human target remains in static state 408 for longer than a predetermined period of time (e.g., such as 10 frames), processor 104 may determine vital signs of such human target (such as heartbeat rate and/or respiration rate) while the target remains in static state 408” [0188])
Will teaches in the same field of OS-CFAR systems. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Abboud as modified by Halma with the teachings of Will to incorporate the features of sending an interrupt to processing circuitry in response to presence or motion detection so as to gain the advantage of reducing computational effort [0165, Will]. Also, since it has been held that if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill (MPEP 2143).
Regarding claim 22, Abboud as modified by Halma discloses all the limitations of claim 20. Abboud discloses, processing circuitry […] wherein the processing circuitry is separate from the radar sensor (“Inputs all video samples within N/2 samples on either side of the sample cell which is being examined for the presence or absence of a Target” [Col.1, ll.40-42] & Fig.1)
Abboud as modified by Halma do not appear to explicitly disclose sending an interrupt to processing circuitry in response to presence or motion detection. Will discloses, wherein the processing circuitry is configured to, in response to receiving an interrupt from the apparatus, perform further processing of the radar data (“when a human target remains in static state 408 for longer than a predetermined period of time (e.g., such as 10 frames), processor 104 may determine vital signs of such human target (such as heartbeat rate and/or respiration rate) while the target remains in static state 408” [0188])
Will teaches in the same field of OS-CFAR systems. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Abboud as modified by Halma with the teachings of Will to incorporate the features of sending an interrupt to processing circuitry in response to presence or motion detection so as to gain the advantage of reducing computational effort [0165, Will]. Also, since it has been held that if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill (MPEP 2143).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Abboud(US5179712A) as modified by Halma(US 5907684 A) as applied to claims 1 and 9 above, and further in view of RAMALINGAM(US20220155368A1) and Will(US20210349203A1).
Regarding claim 21, Abboud as modified by Halma discloses all the limitations of claim 20. Although Abboud as modified by Halma discloses the use of radar, Abboud as modified by Halma does not appear to explicitly disclose a first antenna configured to receive a first signal from a field of view of the radar sensor. RAMALINGAM discloses wherein: the radar sensor comprises a first antenna configured to receive a first signal from a field of view of the radar sensor (“ Detection occurs when returning radar signals are received by an antenna “ [0002]), wherein the radar sensor is configured to generate the radar data based on the first signal (“Data samples of the returning radar signals are stored in a shift register” [0002]);
RAMALINGAM teaches in the same field of OS-CFAR systems. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Abboud as modified by Halma with the teachings of RAMALINGAM to incorporate the features of a first antenna configured to receive a first signal from a field of view of the radar sensor so as to gain the advantage of improving receive capabilities. Also, since it has been held that if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill (MPEP 2143).
Abboud as modified by Halma and RAMALINGAM do not appear to disclose a second radar sensor. Will discloses wherein, the radar sensor comprises at least one second antenna configured to receive at least one second signal from the field of view of the radar sensor (“In some cases, multiple antennas may be used“ [0003]), wherein the radar sensor is configured to generate second radar data based on the second signal (“A multiple-input and multiple-output (MIMO) configuration “ [0003]); and the radar system comprises at least one second apparatus comprising a further storage circuitry and further control circuitry and configured to process the second radar data (“ During steps 314b and/or 316b, an order statistics (OS) constant false alarm rate (CFAR) (OS-CFAR) detector may be used “ [0066]).
Will teaches in the same field of OS-CFAR systems. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Abboud as modified by Halma and RAMALINGAM with the teachings of Will to incorporate the features of a second radar sensor so as to gain the advantage of improving signal processing [0003, Will]. Also, since it has been held that if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill (MPEP 2143).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CLAYTON PAUL RIDDER whose telephone number is (571)272-2771. The examiner can normally be reached Monday thru Friday ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Keith can be reached on (571) 272-6878. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.P.R./Examiner, Art Unit 3646
/JACK W KEITH/Supervisory Patent Examiner, Art Unit 3646
Prosecution Insights