DETAILED ACTION
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6 and 8-11 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Heo et al. (US 2021/0359101 A1; hereinafter “Heo”).
In regard to claim 1, Heo teaches a semiconductor device (a semiconductor device) (paragraph 25), comprising:
a capacitor structure (a capacitor D60) (Fig. 11, Fig. 15, paragraphs 66 and 83), comprising: a bottom electrode (a first electrode 600) (Fig. 11 and paragraph 66); a first dielectric layer (anti-ferroelectric layer 210) on the bottom electrode (Fig. 11 and paragraph 66);
a second dielectric layer (a ferroelectric layer 220) on the first dielectric layer (Fig. 11 and paragraph 66);
a third dielectric layer (a second anti-ferroelectric layer 230) on the second dielectric layer (Fig. 11 and paragraph 66); and
a top electrode (second electrode 700) on the third dielectric layer (Fig. 11 and paragraph 66), wherein each of the first dielectric layer and the third dielectric layer comprises zirconium oxide, wherein the second dielectric layer comprises hafnium-zirconium oxide (the ferroelectrics and anti-ferroelectrics can contain either one or both of zirconium oxide (ZrO2) and hafnium-zirconium oxide (HfxZr1-xO2, 0<x<1) (paragraph 86), and wherein each of the first dielectric layer, the second dielectric layer, and the third dielectric layer comprises a first crystal phase and a second crystal phase (the ferroelectric layer 22 and the first and second anti-ferroelectric layers 21 and 23 may each independently include both orthorhombic crystal structure and tetragonal crystal structure) (paragraph 91).
In regard to claim 2, Heo teaches wherein the first crystal phase of each of the first dielectric layer, the second dielectric layer, and the third dielectric layer has an anti-ferroelectric property, and wherein the second crystal phase of each of the first dielectric layer, the second dielectric layer, and the third dielectric layer has a ferroelectric property (the orthorhombic crystal structure and the tetragonal crystal structure in zirconium oxide and hafnium-zirconium oxide exhibits anti-ferroelectric and ferroelectric properties) (paragraph 15).
In regard to claim 3, Heo teaches wherein the first crystal phase each of the first dielectric layer, the second dielectric layer, and the third dielectric layer is a tetragonal crystal phase, and wherein the second crystal phase each of the first dielectric layer, the second dielectric layer, and the third dielectric layer is an orthorhombic crystal phase (the ferroelectric layer 22 and the first and second anti-ferroelectric layers 21 and 23 may each independently include both orthorhombic crystal structure and tetragonal crystal structure) (paragraph 91).
In regard to claim 4, Heo teaches wherein the hafnium-zirconium oxide of the second dielectric layer is Hf1-xZrxO2, and wherein x ranges from 0.1 to 0.7 (the ferroelectrics and anti-ferroelectrics can contain hafnium-zirconium oxide) (HfxZr1-xO2, 0<x<1) (paragraph 86).
In regard to claim 5, Heo teaches wherein at least one of the first dielectric layer, the second dielectric layer, and the third dielectric layer comprises aluminum-doped zirconium oxide (at least one of the ferroelectric layer, the first anti-ferroelectric layer, and the second anti-ferroelectric layer may comprise one or more dopant materials such as aluminum Al) (paragraph 14).
In regard to claim 6, Heo teaches wherein an aluminum concentration in the aluminum-doped zirconium oxide is greater than 0 at % and is lower than or equal to 20 at % (the ferroelectric layer may have a content of the dopant material between 0 at % and 10 at %) (paragraph 14).
In regard to claim 8, Heo teaches wherein a thickness of each of the first dielectric layer, the second dielectric layer, and the third dielectric layers ranges from 5 Å to 40 Å (the thickness of the first anti-ferroelectric layer 21, the ferroelectric layer 22, and the second anti-ferroelectric layer 23 may also be independently 4 nm (40 Å) or less) (paragraph 92).
In regard to claim 9, Heo teaches wherein a thickness of the second dielectric layer ranges from 5 Å to 30 Å (the thickness of the first anti-ferroelectric layer 21, the ferroelectric layer 22, and the second anti-ferroelectric layer 23 may also be independently 0.5 nm (5 Å) or more and 4 nm (40 Å) or less) (paragraph 92).
In regard to claim 10, Heo teaches wherein the first dielectric layer contacts the bottom electrode, and wherein the third dielectric layer contacts the top electrode (the thickness of the first anti-ferroelectric layer 21, the ferroelectric layer 22, and the second anti-ferroelectric layer 23 may also be independently 0.5 nm (5 Å) or more and 4 nm (40 Å) or less) (paragraph 92).
In regard to claim 11, Heo teaches wherein, in a plan view, the first dielectric layer, the second dielectric layer, and the third dielectric layer sequentially enclose the bottom electrode (as shown in Fig. 12C, the thin film structure 200 which includes the first anti-ferroelectric layer 210, the ferroelectric layer 220, and the second anti-ferroelectric layer 230 is shown enclosing the first electrode 600) (Fig. 12C and paragraph 52).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Heo as applied to claim 1 above.
In regard to claim 7, Heo teaches wherein the capacitor structure is configured to reach a maximum capacitance when a voltage applied to the capacitor structure is within a range from -0.9 V to 0.9 V (as the capacitance is determined by the “x” in HfxZr1-xO2 (see paragraphs 41-42 of instant application specification for example), the examiner takes official notice that since Heo teaches the claimed range of the HfxZr1-xO2 being 0.1 to 0.7 the maximum capacitance is reached when a voltage applied to the capacitor structure is within a range from -0.9 V to 0.9 V).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Heo as applied to claim 1 above, and further in view of (Tao et al. “Slope and Hysteresis-FreeMoS2 Negative-Capacitance Transistors Using Single HfZrAlO Layer as Gate Dielectric” Nanomaterials 2022, 12, 4352; hereinafter “Tao”).
In regard to claim 7, Heo doesn’t explicitly state wherein the capacitor structure is configured to reach a maximum capacitance when a voltage applied to the capacitor structure is within a range from -0.9 V to 0.9 V.
Tao teaches a semiconductor device (negative-capacitance field-effect transistors (NCFETs)) (abstract), state wherein a capacitor structure (the (Au/Cr)/HZAO/p++-Si capacitor) is configured to reach a maximum capacitance when a voltage applied to the capacitor structure is within a range from -0.9 V to 0.9 V (the peak capacitance is shown to be between -1V to 0V in Fig. 2b) (Fig. 1a, Fig. 2b and [Results and Discussion, lns. 1-2, lns. 13-14]).
It would’ve been obvious to one skilled in the art to combine the teachings of Heo with the teachings of Tao to have the capacitor structure configured to reach a maximum capacitance when a voltage applied to the capacitor structure is within a range from -0.9 V to 0.9 V since this allows fabrication of fabrication of high-performance and low-power dissipation devices as taught by Tao (abstract, lns. 11-12).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Heo as applied to claim 1 above, and further in view of Kang et al. (US 2020/0395438 A1; hereinafter “Kang”).
In regard to claim 12, Heo doesn’t explicitly teach wherein the bottom electrode has a pillar shape or a cylinder shape.
Kang teaches a semiconductor device (an integrated circuit device 100) (Fig. 1 and paragraph 28), wherein a bottom electrode (a bottom electrode 170) has a pillar shape or a cylinder shape (the bottom electrode 170 may have a pillar or column shape) (Fig. 2 and paragraph 46).
It would have been obvious to one skilled in the art to combine the teachings of Heo with the teachings of Kang to form the bottom electrode with pillar shape or a cylinder shape since it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984).
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Heo.
In regard to claim 13, Heo teaches a semiconductor device (a semiconductor device (field effect transistor)) (paragraph 25), comprising:
a capacitor structure (a capacitor D60) (Fig. 11, Fig. 15, paragraphs 66 and 83), comprising: a bottom electrode (a first electrode 600) (Fig. 11 and paragraph 66); a first dielectric layer (anti-ferroelectric layer 210) on the bottom electrode (Fig. 11 and paragraph 66);
a second dielectric layer (a ferroelectric layer 220) on the first dielectric layer (Fig. 11 and paragraph 66);
a third dielectric layer (a second anti-ferroelectric layer 230) on the second dielectric layer (Fig. 11 and paragraph 66); and
a top electrode (second electrode 700) on the third dielectric layer (Fig. 11 and paragraph 66), wherein each of the first dielectric layer and the third dielectric layer comprises zirconium oxide, wherein the second dielectric layer comprises hafnium-zirconium oxide (the ferroelectrics and anti-ferroelectrics can contain either one or both of zirconium oxide (ZrO2) and hafnium-zirconium oxide (HfxZr1-xO2, 0<x<1) (paragraph 86), and wherein the capacitor structure is configured to reach a maximum capacitance when a voltage applied to the capacitor structure is within a range from -0.9 V to 0.9 V (as the capacitance is determined by the “x” in HfxZr1-xO2 (see paragraphs 41-42 of instant application specification for example), the examiner takes official notice that since Heo teaches the range of the HfxZr1-xO2 being 0.1 to 0.7 the maximum capacitance is reached when a voltage applied to the capacitor structure is within a range from -0.9 V to 0.9 V).
In regard to claim 14, Heo teaches wherein each of the first dielectric layer, the second dielectric layer, and the third dielectric layer comprises an anti-ferroelectric region and a ferroelectric region (the ferroelectric layer 22 and the first and second anti-ferroelectric layers 21 and 23 may each independently include both orthorhombic crystal structure and tetragonal crystal structure, which means that the first dielectric layer, the second dielectric layer, and the third dielectric layer comprises an anti-ferroelectric region and a ferroelectric region) (paragraph 91).
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Heo, and further in view of Tao.
In regard to claim 13, Heo teaches a semiconductor device (a semiconductor device (field effect transistor)) (paragraph 25), comprising:
a capacitor structure (a capacitor D60) (Fig. 11, Fig. 15, paragraphs 66 and 83), comprising: a bottom electrode (a first electrode 600) (Fig. 11 and paragraph 66); a first dielectric layer (anti-ferroelectric layer 210) on the bottom electrode (Fig. 11 and paragraph 66);
a second dielectric layer (a ferroelectric layer 220) on the first dielectric layer (Fig. 11 and paragraph 66);
a third dielectric layer (a second anti-ferroelectric layer 230) on the second dielectric layer (Fig. 11 and paragraph 66); and
a top electrode (second electrode 700) on the third dielectric layer (Fig. 11 and paragraph 66), wherein each of the first dielectric layer and the third dielectric layer comprises zirconium oxide, wherein the second dielectric layer comprises hafnium-zirconium oxide (the ferroelectrics and anti-ferroelectrics can contain either one or both of zirconium oxide (ZrO2) and hafnium-zirconium oxide (HfxZr1-xO2, 0<x<1) (paragraph 86),
Heo doesn’t explicitly state, wherein the capacitor structure is configured to reach a maximum capacitance when a voltage applied to the capacitor structure is within a range from -0.9 V to 0.9 V.
Tao teaches a semiconductor device (negative-capacitance field-effect transistors (NCFETs)) (abstract), wherein a capacitor structure (the (Au/Cr)/HZAO/p++-Si capacitor) is configured to reach a maximum capacitance when a voltage applied to the capacitor structure is within a range from -0.9 V to 0.9 V (the peak capacitance is shown to be between -1V to 0V in Fig. 2b) (Fig. 1a, Fig. 2b and [Results and Discussion, lns. 1-2, lns. 13-14]).
It would’ve been obvious to one skilled in the art to combine the teachings of Heo with the teachings of Tao to have the capacitor structure configured to reach a maximum capacitance when a voltage applied to the capacitor structure is within a range from -0.9 V to 0.9 V since this allows fabrication of fabrication of high-performance and low-power dissipation devices as taught by Tao (abstract, lns. 11-12).
In regard to claim 14, Heo teaches wherein each of the first dielectric layer, the second dielectric layer, and the third dielectric layer comprises an anti-ferroelectric region and a ferroelectric region (the ferroelectric layer 22 and the first and second anti-ferroelectric layers 21 and 23 may each independently include both orthorhombic crystal structure and tetragonal crystal structure, which means that the first dielectric layer, the second dielectric layer, and the third dielectric layer comprises an anti-ferroelectric region and a ferroelectric region) (paragraph 91).
Claims 25-30 are rejected under 35 U.S.C. 103 as being unpatentable over Kang, and further in view of Heo.
In regard to claim 25, Kang teaches a semiconductor device (an integrated circuit device 100C) (Fig. 8 and paragraph 73), comprising:
a substrate (a substrate 110) (Fig. 8 and paragraph 29);
a first conductive contact and a second conductive contact on the substrate (two of a plurality capacitor contacts 150 arranged on the second source/drain regions 114B as shown in Fig. 8) (Fig. 8 and paragraph 41);
a first bottom electrode on the first conductive contact and a second bottom electrode on the second conductive contact (two of a plurality of bottom electrodes 170c, are shown on the capacitor contacts 150 in Fig. 8); and
a first stack dielectric layer on the first bottom electrode and the second bottom electrode (two of the plurality of lower dielectric layers 180 shown over the bottom electrodes 170c may have a stack structure) (Fig. 8 and paragraph 55), the first stack dielectric layer comprising: a first dielectric layer on each of the first bottom electrode and the second bottom electrode (the dielectric layer 180 may have a stack structure of a first dielectric layer and a second dielectric layer) (Fig. 8 and paragraph 55);
a second dielectric layer on the first dielectric layer (the dielectric layer 180 may have a stack structure of a first dielectric layer and a second dielectric layer) (paragraph 55);
Kang doesn’t explicitly teach a third dielectric layer on the second dielectric layer; and a top electrode on the third dielectric layer, wherein each of the first dielectric layer and the third dielectric layer of the first stack dielectric layer comprises zirconium oxide, wherein the second dielectric layer of the first stack dielectric layer comprises hafnium-zirconium oxide, and wherein each of the first dielectric layer, the second dielectric layer, and the third dielectric layer of the first stack dielectric layer comprises a first crystal phase and a second crystal phase.
Heo teaches a semiconductor device (a semiconductor device) (paragraph 25), a third dielectric layer (a second anti-ferroelectric layer 230) on the second dielectric layer (Fig. 11 and paragraph 66); and
a top electrode (second electrode 700) on the third dielectric layer (Fig. 11 and paragraph 66), wherein each of the first dielectric layer and the third dielectric layer comprises zirconium oxide, wherein the second dielectric layer comprises hafnium-zirconium oxide (the ferroelectrics and anti-ferroelectrics can contain either one or both of zirconium oxide (ZrO2) and hafnium-zirconium oxide (HfxZr1-xO2, 0<x<1) (paragraph 86), and wherein each of the first dielectric layer, the second dielectric layer, and the third dielectric layer of the first stack dielectric layer comprises a first crystal phase and a second crystal phase (the ferroelectric layer 22 and the first and second anti-ferroelectric layers 21 and 23 may each independently include both orthorhombic crystal structure and tetragonal crystal structure) (paragraph 91).
It would’ve been obvious to one skilled in the art to combine the teachings of Kang with the teachings of Heo to have, a third dielectric layer on the second dielectric layer; and a top electrode on the third dielectric layer, wherein each of the first dielectric layer and the third dielectric layer of the first stack dielectric layer comprises zirconium oxide, wherein the second dielectric layer of the first stack dielectric layer comprises hafnium-zirconium oxide, and wherein each of the first dielectric layer, the second dielectric layer, and the third dielectric layer of the first stack dielectric layer comprises a first crystal phase and a second crystal phase, since this allows for the creation of more compact semiconductor devices with improved performance of applying ferroelectric properties to semiconductor devices as taught by Heo (paragraphs 4-5).
In regard to claim 26, Kang teaches further comprising a supporting layer (a first supporter 192) between the first bottom electrode and the second bottom electrode (the first supporter 192 is shown between the bottom electrodes 170 in Fig. 8) (Fig. 9 and paragraph 51), wherein the first dielectric layer of the first stack dielectric layer is on the supporting layer (dielectric layers 180 are shown on the first supporter 192 in Fig. 8).
In regard to claim 27, Kang teaches the semiconductor device of claim 25 further comprising:
an etch stop layer (etch stop layer 162) between the substrate and the top electrode (Fig. 8 and paragraph 43); and a second stack dielectric layer (an upper dielectric layers 180) on the etch stop layer (Fig. 8), the second stack dielectric layer comprising:
a first dielectric layer on the etch stop layer (two of the plurality of upper dielectric layers 180 are shown over the etch stop layer 162 have a stack structure) (Fig. 8 and paragraph 55);
a second dielectric layer on the first dielectric layer (two of the plurality of upper dielectric layers 180 are shown over the etch stop layer 162 have a stack structure) (Fig. 8 and paragraph 55);
However, Kang doesn’t explicitly teach a third dielectric layer on the second dielectric layer, wherein each of the first dielectric layer and the third dielectric layer of the second stack dielectric layer comprises zirconium oxide, wherein the second dielectric layer of the second stack dielectric layer comprises hafnium-zirconium oxide, and wherein each of the first dielectric layer, the second dielectric layer, and the third dielectric layer of the second stack dielectric layer comprises a first crystal phase and a second crystal phase.
Heo teaches a third dielectric layer (a second anti-ferroelectric layer 230 of the plurality of second anti-ferroelectric layer 230) on the second dielectric layer (Fig. 11 and paragraphs 66 and 71); wherein each of the first dielectric layer and the third dielectric layer comprises zirconium oxide, wherein the second dielectric layer comprises hafnium-zirconium oxide (the ferroelectrics and anti-ferroelectrics can contain either one or both of zirconium oxide (ZrO2) and hafnium-zirconium oxide (HfxZr1-xO2, 0<x<1) (paragraph 86), and wherein each of the first dielectric layer, the second dielectric layer, and the third dielectric layer of the first stack dielectric layer comprises a first crystal phase and a second crystal phase (the ferroelectric layer 22 and the first and second anti-ferroelectric layers 21 and 23 may each independently include both orthorhombic crystal structure and tetragonal crystal structure) (paragraph 91).
It would’ve been obvious to one skilled in the art to combine the teachings of Kang with the teachings of Heo to have each of the first dielectric layer and the third dielectric layer of the first stack dielectric layer comprises zirconium oxide, wherein the second dielectric layer of the first stack dielectric layer comprises hafnium-zirconium oxide, and wherein each of the first dielectric layer, the second dielectric layer, and the third dielectric layer of the first stack dielectric layer comprises a first crystal phase and a second crystal phase, since this allows for the creation of more compact semiconductor devices with improved performance of applying ferroelectric properties to semiconductor devices as taught by Heo (paragraphs 4-5).
In regard to claim 28, Kang teaches wherein each of the first bottom electrode and the second bottom electrode has a pillar shape or a cylinder shape (the bottom electrode 170 may have a pillar or column shape) (Fig. 2 and paragraph 46).
In regard to claim 29, Kang in view of Heo teaches wherein the first crystal phase of each of the first dielectric layer, the second dielectric layer, and the third dielectric layer of the first stack dielectric layer has an anti-ferroelectric property, and wherein the second crystal phase of each of the first dielectric layer, the second dielectric layer, and the third dielectric layer of the first stack dielectric layer has a ferroelectric property (the orthorhombic crystal structure and the tetragonal crystal structure in zirconium oxide and hafnium-zirconium oxide exhibits anti-ferroelectric and ferroelectric properties) (paragraph 15).
In regard to claim 30, Kang in view of Heo teaches wherein the first crystal phase of each of the first dielectric layer, the second dielectric layer, and the third dielectric layer of the first stack dielectric layer is a tetragonal crystal phase, and wherein the second crystal phase of each of the first dielectric layer, the second dielectric layer, and the third dielectric layer of the first stack dielectric layer is an orthorhombic crystal phase (the ferroelectric layer 22 and the first and second anti-ferroelectric layers 21 and 23 may each independently include both orthorhombic crystal structure and tetragonal crystal structure) (paragraph 91).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure, Mun et al. (US 20200058731 A1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEYON ALI-SIMAH PUNCHBEDDELL whose telephone number is (571)270-0078. The examiner can normally be reached Mon-Thur: 7:30AM-3:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SEYON ALI-SIMAH PUNCHBEDDELL/ Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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