Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
This office acknowledges receipt of the following item(s) from the Applicant:
Papers submitted under 35 U.S.C. 119(a)-(d) have been placed of record in thefile.
Claims 1-20 are present for examination.
Response to Arguments
Applicant's arguments with respect to the claimed limitations have been considered but are moot in view of the new ground(s) of rejections as follows:
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 9-10, 11-12, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Prakash et al (US 20230197175 A1) in view of Lee et al. (US 20050036369 A1).
Regarding claims 1, 11, and 20: Prakash discloses a control logic for memory devices for source bias temperature compensation comprising: a memory string (NAND string 306, FIG. 2) comprising a drain select gate (DSG) transistor (drain select gate (SDG) transistor 312, FIG. 3A), memory cells (memory cells 308, FIG. 3A), and a source select gate (SSG) transistor (source select gate (SGS) transistor 310, FIG. 3A); a bit line (bitline 304, FIG. 3A) coupled to the DSG transistor (FIG. 3A); a source line (common source SRC, source voltage line 303, FIG. 3A) coupled to the SSG transistor (FIG. 3A); and a memory controller (controller 115, FIG 1A) coupled to the memory device and configured to control the memory device.
Prakash does not disclose a peripheral circuit coupled to the memory string through the bit line and the source line, and configured to, in a pre-charge period of a program operation, apply a bias voltage to at least one of the bit line or the source line, wherein the bias voltage is determined based on a temperature associated with the memory device.
Lee does disclose a semiconductor memory device with a temperature compensated bit-line precharge, wherein in a pre-charge period (FIG. 3A) of a program operation, apply a bias voltage to at least one of the bit line (BL Precharge, FIG. 3A) or the source line, wherein the bias voltage is determined based on a temperature (bit line precharge level dependent on temperature, par. 51, FIG. 5) associated with the memory device.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Prakash with the precharge configuration of Lee to allow the bias voltage determined to be applied to the bit line during the pre-charge period of operation to be variable depending on the temperature of the memory device like the claimed invention.
Regarding claims 2 and 12: Prakash does not disclose a memory device, herein the temperature comprises a first temperature and a second temperature lower than the first temperature: and the bias voltage comprises a first bias voltage at the first temperature and a second bias voltage at the second temperature that is lower than the first bias voltage.
Lee does disclose a semiconductor memory device with a temperature compensated bit-line precharge, wherein the temperature comprises a first temperature (higher temperature point, FIG. 5B) and a second temperature lower than the first temperature (lower temperature point, FIG. 5B); and the bias voltage comprises a first bias voltage at the first temperature (higher bit line voltage VBL at higher temperature point, FIG. 5B) and a second bias voltage at the second temperature that is lower than the first bias voltage (lower bit line voltage VBL at lower temperature point, FIG. 5B).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Prakash with the configuration of Lee to allow the designated bias voltage to be applied follows the same trend over a range of temperature as the claimed invention.
Regarding claims 9 and 19: Prakash discloses a memory device configured to: obtain the temperature associated with the memory device (410 of FIG. 4); and determine the bias voltage based on the temperature (415 of FIG. 4).
Regarding claim 10: Prakash discloses a memory device wherein the memory string (NAND string 204, FIG. 2) comprises a plurality of memory strings (NAND strings 2060-206M, FIG. 2) each comprising a DSG transistor (drain select gate (SDG) transistors 2120-2123, FIG. 2), memory cells (plurality of memory cells 208x in each string 2060-206M, FIG. 2), and an SSG transistor (source select gate (SGS) transistor 2100-3, FIG. 2); the bit line comprises a plurality of bit lines (bitlines 2040-M, FIG. 2) coupled to the DSG transistors (drain select gate (SDG) transistors 2120-212M, FIG. 2), respectively; and the source line (common source SRC, source voltage line 216, FIG. 2) is coupled to the SSG transistors (source select gate (SGS) transistor 2100-M, FIG. 2).
Claim(s) 3-4 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Prakash et al (US 20230197175 A1) in view of Lee et al. (US 20050036369 A1), in further view of Wang et al. (US 20100073069 A1).
Regarding claims 3 and 13: Regarding claim 3: Prakash does not disclose a memory device wherein a difference between the first and second bias voltages is determined based on a difference between the first and second temperatures.
Lee does disclose a semiconductor memory device with a temperature compensated bit-line precharge, wherein a difference between the first and second bias voltages (difference between higher first bit line voltage and second lower bit line voltage, FIG. 5B) is determined based on a difference between the first and second temperatures (difference between first higher temperature value and second lower temperature value, FIG. 5B).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Prakash with the configuration of Lee to allow the designated bias voltage to be applied follows the same trend over a range of temperature as the claimed invention.
Prakash and Lee do not disclose a temperature coefficient.
Wang does disclose a temperature coefficient (temperature coefficient TCO, used to determine bias voltage in formula, par. 25, FIG. 3).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Prakash and Lee with the configuration of Wang to allow the system to utilize a temperature coefficient to be used in the determination of the bias voltage.
Regarding claims 4 and 14: Prakash and Lee do not disclose the temperature coefficient is a constant.
Wang does disclose the temperature coefficient is a constant (temperature coefficient TCO constant with increasing temperature, shown as bar 301, FIG. 3).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Prakash and Lee with the configuration of Wang in order to have the implemented temperature coefficient allow the determined bias voltage to have a linear relationship with the temperature.
Claim(s) 5-8 and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Prakash et al (US 20230197175 A1) in view of Lee et al. (US 20050036369 A1), in further view of Kim et al. (US 20120262986 A1).
Regarding claims 5 and 15: Prakash and Lee do not disclose a memory device configured to: program the memory cells in a direction from the DSG transistor to the SSG transistor; and in the pre-charge period, apply the bias voltage to the source line.
Kim does disclose a source side asymmetrical precharge programming configured to: program the memory cells in a direction from the DSG transistor to the SSG transistor (sequential programming direction from upper most memory cell close to string select transistor 52 towards lower most memory cells close to ground select transistor 56, par. 75, FIG. 9); and in the pre-charge period, apply the bias voltage to the source line (biasing source line CSL, par. 62, FIG. 11).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Prakash and Lee with the configuration of Kim to allow the system to determine a direction of programming the NAND cells and use the bias voltage determined by Lee to bias the source line in operation.
Regarding claims 6 and 16: Prakash and Lee do not disclose a memory device configured to: in the pre-charge period, turn on the SSG transistor.
Kim does disclose a source side asymmetrical precharge programming configured to: in the pre-charge period, turn on the SSG transistor (in precharge phase, drive GSL connected to gate of ground select transistor 56 between t1 and t2, par. 62, FIG. 11).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Prakash and Lee with the configuration of Kim to allow the programming scheme to drive the equivalent string select gate transistor during operation like the claimed invention.
Regarding claims 7 and 17: Prakash and Lee do not disclose a memory device configured to: program the memory cells in a direction from the SSG transistor to the DSG transistor; and in the pre-charge period, apply the bias voltage to the bit line.
Kim does disclose a source side asymmetrical precharge programming configured to: program the memory cells in a direction from the SSG transistor to the DSG transistor (sequential programming direction from lower most memory cells close to ground select transistor 56 towards upper most memory cell close to string select transistor 52 towards, par. 75, FIG. 9); and in the pre-charge period, apply the bias voltage to the bit line (in precharge, bitline is driven to VDD, par. 65)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Prakash and Lee with the configuration of Kim to allow the system to determine a direction of programming the NAND cells and use the bias voltage determined by Lee to bias the bit line in operation.
Regarding claims 8 and 18: Prakash and Lee do not disclose a memory device configured to: in the pre-charge period, turn on the DSG transistor.
Kim does disclose a source side asymmetrical precharge programming configured to: in the pre-charge period, turn on the DSG transistor (in precharge phase, drive SSL connected to gate of string select transistor 52 between t5 and t6, par. 65, FIG. 11).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Prakash and Lee with the configuration of Kim to allow the programming scheme to drive the equivalent ground select gate transistor during operation like the claimed invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY THINH TANG whose telephone number is (571)272-6845. The examiner can normally be reached Monday-Friday 7:30-5:00 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTHONY THINH TANG/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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