DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yoon et al. (US PUB 2015/0214827), hereinafter Yoon.
With respect to claim 1, Yoon discloses a zero current detection device (See [400] in figure 10 of Yoon) comprising: a scaling circuit (See [420] in figure 10 of Yoon) configured to generate a first voltage (See [VSC] in figure 10 of Yoon) which is scaled from a target voltage (See [VDD] in figure 10 of Yoon); a mirroring circuit (See [431] and [43n] in figure 10 of Yoon) configured to generate a mirroring current (See [431] and [43n] in figure 10 of Yoon) when the first voltage is higher than or equal to a reference voltage (See paragraph [0110] of Yoon); and a comparator circuit (See [470] in figure 10 of Yoon) configured to compare the target voltage (See [VDD] via the switches [441], [413] and [44n] in figure 10 of Yoon) and a ground voltage when the mirroring current is input (See [VREF2] in figure 10 of Yoon in view of paragraph [0112] of Yoon).
With respect to claim 2, Yoon discloses the zero current detection device of claim 1, further comprising a clock signal generation circuit (See [475] in figure 10 of Yoon) configured to delay a result of comparing the target voltage and the ground voltage to generate a clock signal for an operation of the comparator circuit unit (See paragraphs [0109] and [0111] of Yoon).
With respect to claim 3, Yoon discloses the zero current detection device of claim 1, wherein the first voltage has a phase identical to that of the target voltage (Note that in figure 10 of Yoon both [VDD] and [VSC] are DC voltages, thus both having a phase of zero), and has a maximum magnitude greater than the reference voltage by a preset offset value (See paragraph [0112] of Yoon).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoon and further in view of Campbell, Jr. (US PAT 4,484,092), hereinafter Campbell.
With respect to claim 8, Yoon discloses a zero current detection device (See [400] in figure 10 of Yoon) comprising: a comparison signal generation circuit (See [410] in figure 10 of Yoon) including: a first capacitor (See [461] in figure 10 of Yoon) having a first terminal connected to a reference voltage (See the ground potential connected to the lower plate of [461] in figure 10 of Yoon), a first switch connected in parallel with the first capacitor (See [45n] in figure 10 of Yoon), a second switch (See [451] in figure 10 of Yoon) having one terminal connected to a second terminal of the first capacitor (See the bottom terminal of switch [451] connected to the top terminal of [461] in figure 10 of Yoon), a D flip-flop configured to delay a clock signal (See paragraphs [0119] and [0120] of Yoon) to output a control signal controlling operations of the first switch and the second switch (See paragraphs [0105] and [0106] in view of the abstract of Yoon), and a comparator circuit (See [470] in figure 10 of Yoon) configured to compare a target voltage (See [VDD] via the switches [441], [413] and [44n] in figure 10 of Yoon) and a ground voltage based on an output of the comparison signal generation circuit (See [VREF2] in figure 10 of Yoon in view of paragraph [0112] of Yoon) but fails to disclose an inverter configured to invert a voltage applied to the second terminal of the first capacitor and output the voltage. However, Campbell does disclose an inverter configured to invert a voltage applied to the second terminal of the first capacitor and output the voltage (See the inverter [68] connected to the second terminal of capacitor [58] in figure 3 of Campbell). Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the device disclosed by Yoon to include the features disclosed by Campbell because doing so stabilizes power flow and filters noise.
Allowable Subject Matter
Claims 4-7 and 9-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 4, the prior art of record neither shows nor suggests the combination of structural elements wherein the offset value is configured to cause a magnitude of the first voltage to be greater than or equal to a threshold gate voltage for operating the mirroring circuit when a magnitude of the target voltage is greater than or equal to a preset magnitude.
With respect to claim 5, the prior art of record neither shows nor suggests the combination of structural elements wherein the scaling circuit is configured to receive a second voltage with a phase that is 90° ahead of the phase of the target voltage and a maximum magnitude that is smaller than the maximum magnitude of the target voltage, and output the first voltage by adjusting the phase and magnitude of the second voltage.
Claims 6 and 7 depend from objected to claim 5 and are therefore also objected to.
With respect to claim 9, the prior art of record neither shows nor suggests the combination of structural elements further comprising: a counter circuit configured to count a number of times the target voltage is greater than the ground voltage or a number of times the target voltage is smaller than the ground voltage based on the output of the comparator circuit; and a current output digital-to-analog converter connected to the second terminal of the first capacitor, wherein the current output digital-to-analog converter is configured to operate based on the counting result.
Claims 10-12 depend from objected to claim 9 and are therefore also objected to.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US PUB 2016/0028302 discloses the protection of switched capacitor power converter.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TEMILADE S RHODES-VIVOUR whose telephone number is (571)270-5814. The examiner can normally be reached M-F (flex schedule).
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/TEMILADE S RHODES-VIVOUR/Examiner, Art Unit 2858
/HUY Q PHAN/Supervisory Patent Examiner, Art Unit 2858