DETAILED ACTION
This action is responsive to the application filed on June 17, 2024.
Claims 1-20 are pending. Claims 1, 8 and 13 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Brannigan et al (US 5896040) in view of Ma (US 6054334) and Graf et al (US 20060267721).
Regarding Independent Claim 1, Brannigan teaches an apparatus (fig. 1: 300 MIL I. C. Device), comprising:
a memory array (fig. 1: 300 MIL I. C. Device; cols 1 lines 66-67 and col 2 line 1 “The assembly demands for a larger density integrated circuit device, such as a 1 Meg SRAM (Static Random Access Memory) shown in FIG. 1.”) of a semiconductor component;
a first conductive pad (Fig. 3a 36) at a surface of the semiconductor component and
a second conductive pad (Fig. 3a: 12) at the surface of the semiconductor component and electrically disconnected from the first conductive pad via a disconnection region (Fig. 3a: Fuse Circuitry) of a conductor portion between the first conductive pad (Fig. 3a: 36) and the second conductive pad (Fig. 3a: 12).
However, Brannigan fails to teach a molten disconnection region and fails to teach circuitry of the semiconductor component that is configured for accessing the memory array.
Ma Teaches circuitry (Fig. 1: 6) of the semiconductor component that is configured for accessing the memory array (Fig. 1: 4);
Memory arrays require circuitry to access the information in order to write and read data to the array. Therefore, having access circuitry between a first pad and array would be beneficial to making use of memory device.
Graf teaches a method of providing disconnection region that is molten (para 42 “the molten material may flow off completely from the current-carrying area into the volume, so that a completely disconnected fuse path results”).
In order to sever an electrical connection in order to permanently isolate two structures electrically from one another a high current is used. One aspect of high current that can be leveraged is the heat generated by passing a high current through a material in order to induce a phase change from the heat generated by the current. This phase change causes certain conductive elements to become molten and thus vacates the space between two elements severing the connection. Therefore, having materials that would become molten would be beneficial for electrically disconnecting two probe pads.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Graf and Ma to the teachings of Brannigan to produce a semiconductor device with access circuitry between a first pad and memory array and where a second pad is disconnected from the first pad by a molten disconnection region.
Regarding Claim 2, Brannigan, Ma, and Graf teach the limitations of claim 1. Brannigan further teaches the first conductive pad (Fig. 2: END PAD) and a first portion of the conductor portion (Fig. 3a: FUSE CIRCUITRY) comprise a first contiguous portion of a conductive material; and
the second conductive pad (Fig. 2: SIDE PAD) and a second portion of the conductor portion (Fig. 3a: FUSE CIRCUITRY) comprise a second contiguous portion of the conductive material.
Its understood that when the fuse is blown there is now a physical disconnect in the center of the fuse and each end is now connected to a pad with space between. (col 5 lines 16-21 “A fuse may be used in place of the transmission gate formed by transistors 30 and 32 to disconnect configurable probe pad 12 from pad 36 in order to reduce the capacitive impact of configurable probe pad 12 during normal operation of the device. Fuse circuitry, however, is a permanent solution that may not be undone.”)
Regarding Claim 3, Brannigan, Ma, and Graf teach the limitations of claim 1. Graf further teaches wherein the first conductive pad and the second conductive pad comprise a first conductor material and the conductor portion comprises a second conductor material that is different than the first conductor material. (para 12 “A fuse element for protecting a current consumer may comprise a first terminal point, a second terminal point, and a fusible material, which melts at a predetermined temperature, between the first and the second terminal points, which is configured to establish, in the non-molten state, an electrically conductive connection between the first and the second terminal points; and an assistor between the first and the second terminal points, configured to assist in removing the fusible material in the molten state from an area between the first and the second terminal points.”)
Regarding Claim 5, Brannigan, Ma, and Graf teach the limitations of claim 1. Graf further teaches wherein the molten disconnection region comprises an opened electrical connection of a fuse. (para 41 “Thus, the disconnection of the fuse is assisted, since, due to the repellant property of the carrier material, the molten material of the fuse is removed from the current-carrying area after it has melted.”)
Regarding Claim 6, Brannigan, Ma, and Graf teach the limitations of claim 1. Brannigan further teaches wherein the first conductive pad is configured for coupling with a second component to convey command signaling, data signaling, clock signaling, or any combination (col 4 lines 44-46 “Pad 36 may be connected to any number of functional pin types of the. device, such as an Address pin, a Chip Enable pin, a Write pin, etc.”) thereof between the second component and the circuitry configured for accessing the memory array.
Claims 8, 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Brannigan et al (US 5896040) in view of Ma (US 6054334).
Regarding Independent Claim 8, Brannigan teaches A method, comprising:
evaluating operations of a semiconductor component (Fig. 2a: PROBE CARD), the semiconductor component including a memory array (fig. 1: 300 MIL I. C. Device; cols 1 lines 66-67 and col 2 line 1 “The assembly demands for a larger density integrated circuit device, such as a 1 Meg SRAM (Static Random Access Memory) shown in FIG. 1.”), a first conductive pad (Fig. 3a: 36) at a surface of the semiconductor component, and a second conductive (Fig. 3a: 12) pad at the surface of the semiconductor component and electrically connected with the first conductive pad via a conductor portion (fig. 3a: FUSE CIRCUITRY), wherein evaluating the operations of the semiconductor component is based at least in part on signaling communicated via the second conductive pad (col 2 lines 26-28 “During parallel testing of the device, the side pad is effectively tested when the configurable probe pad is probed and tested.”); and
electrically disconnecting the second conductive pad from the first conductive pad based at least in part on breaking an electrical continuity through the conductor portion after evaluating the operations of the semiconductor component (col 5 lines 16-21 “A fuse may be used in place of the transmission gate formed by transistors 30 and 32 to disconnect configurable probe pad 12 from pad 36 in order to reduce the capacitive impact of configurable probe pad 12 during normal operation of the device. Fuse circuitry, however, is a permanent solution that may not be undone.”).
However, Brannigan fails to teach circuitry of the semiconductor component that is configured for accessing the memory array,
Ma Teaches circuitry (Fig. 1: 6) of the semiconductor component that is configured for accessing the memory array (Fig. 1: 4);
Memory arrays require circuitry to access the information in order to write and read data to the array. Therefore, having access circuitry between a first pad and array would be beneficial to making use of memory device.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Ma to the teachings of Brannigan to produce a method of operating a semiconductor device, using two connected probe pads to evaluate the operations of the pad, and then disconnect the two probe pads after the evaluation is complete, wherein one of the probe pads is connected to the circuitry used to access the semiconductor array.
Regarding Claim 10, Brannigan and Ma teach the limitations of Claim 8. Ma further teaches melting least a portion of the conductor portion based at least in part on applying a laser to the conductor portion. (col 8 lines 66-67 and col 9 lines 1-2 “The lead 38 can be severed at position "A" using the reconfiguration etch, laser ablation, or by an electrical fuse if the capacitance of the intermediate Vcc (or Vcc2) bond pad 13 is undesirable”)
Regarding Claim 11, Brannigan and Ma teach the limitations of Claim 8. Brannigan further teaches wherein evaluating the operations is associated with deforming a surface of the second conductive pad based at least in part on a probe contacting the second conductive pad. (col 2 lines 26-28 “During parallel testing of the device, the side pad is effectively tested when the configurable probe pad is probed and tested.”; col 4 lines 44-46 “Pad 36 may be connected to any number of functional pin types of the. device, such as an Address pin, a Chip Enable pin, a Write pin, etc.”)
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Brannigan et al (US 5896040) and Ma (US 6054334) in view of Graf et al (US 20060267721).
Regarding Claim 9, Brannigan and Ma teach the limitations of claim 8. Brannigan and Ma fail to teach wherein breaking the electrical continuity through the conductor portion comprises:
melting least a portion of the conductor portion based at least in part on applying a current through the conductor portion.
Graf teaches melting least a portion of the conductor portion based at least in part on applying a current through the conductor portion. (para 43 “Due to the thus selected arrangement of the fuse and the switch, the triggering of the fuse is dependent on the thermal energy generated at the switch rather than on the power dissipation generated at the fuse element, and/or rather than on the current flowing through, as is the case in conventional blow-out fuses.”)
Claims 13-15, 17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Brannigan et al (US 5896040) in view of Ma (US 6054334) and Eghan et al (US 7064450).
Regarding Independent Claim 13, Brannigan teaches an apparatus (fig. 1: 300 MIL I. C. Device), comprising:
a memory array (fig. 1: 300 MIL I. C. Device; cols 1 lines 66-67 and col 2 line 1 “The assembly demands for a larger density integrated circuit device, such as a 1 Meg SRAM (Static Random Access Memory) shown in FIG. 1.”) of a semiconductor component;
a first conductive pad (Fig. 3a 36) at a surface of the semiconductor component
a second conductive pad (Fig. 3a: 12) at the surface of the semiconductor component and electrically connected (Fig. 3a: Fuse Circuitry) with the first conductive pad (Fig. 3a: 36) via a conductor portion,
However, Brannigan fails to teach circuitry of the semiconductor component that is configured for accessing the memory array, and
Fails to teach the conductor portion having a third cross-sectional area that is less than a first cross-sectional area of the first conductive pad and less than a second cross-sectional area of the second conductive pad.
Ma Teaches circuitry (Fig. 1: 6) of the semiconductor component that is configured for accessing the memory array (Fig. 1: 4);
Memory arrays require circuitry to access the information in order to write and read data to the array. Therefore, having access circuitry between a first pad and array would be beneficial to making use of memory device.
Eghen teaches the conductor portion having a third cross-sectional area (Fig. 8: 801C) that is less than a first cross-sectional area (Fig. 8: 801P) of the first conductive pad and less than a second cross-sectional (Fig. 8: 801B) area of the second conductive pad.
Connecting pads via a conductor portion allows for the pads to be tiled more densely on the surface of a semiconductor die. Thus this would allow for more larger pads on smaller chips and making it easier for probes to make contact with the necessary electrical connections.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Ma and Eghen to the teachings of Brannigan to produce a first and second pad that are electrically connected to one another and where the first pad is connected to circuitry that is used to access a memory array.
Regarding Claim 14, Brannigan, Ma, and Eghen teach the limitations of claim 13. Eghen further teaches wherein the first conductive pad (Fig. 8: 801P), the second conductive pad (Fig. 8: 801B), and the conductor portion (Fig. 8: 801C) comprise a conductor material that is contiguous at the surface of the semiconductor component.
Regarding Claim 15, Brannigan, Ma, and Eghen teach the limitations of claim 13. Brannigan further teaches wherein the conductor portion (Fig. 3a: FUSE CIRCUITRY) comprises a first material and the first conductive pad (Fig. 3a: 12) and the second conductive pad (Fig. 3a: 36) comprise a second material that is different than the first material.
Its understood by those of ordinary skill in the art that fuses contain a material that will change when exposed to some extreme conditions such as high heat and current which will alter the state of the material of the fuse but leave the surrounding circuitry intact. This can only be accomplished if the fuse is made of a different material.
Regarding Claim 17, Brannigan, Ma, and Eghen teach the limitations of claim 13. Eghen further teaches wherein a third width of the third cross-sectional area (Fig. 8: 801C) along the surface of the semiconductor component is less than a first width (Fig. 8: d2) of the first cross-sectional area (Fig. 8: 801B) along the surface of the semiconductor component and less than a second width (Fig. 8: d2) of the second cross-sectional area (Fig. 8: 801B) along the surface of the semiconductor component.
Regarding Claim 19, Brannigan, Ma, and Eghan teach the limitations of claim 13. Brannigan further teaches wherein the first conductive pad is configured for coupling with a second component to convey command signaling, data signaling, clock signaling, or any combination thereof between the second component and the circuitry configured for accessing the memory array. (col 2 lines 26-28 “During parallel testing of the device, the side pad is effectively tested when the configurable probe pad is probed and tested.”; col 4 lines 44-46 “Pad 36 may be connected to any number of functional pin types of the. device, such as an Address pin, a Chip Enable pin, a Write pin, etc.”)
Regarding Claim 20, Brannigan, Ma, and Eghan teach the limitations of claim 13. Brannigan further teaches wherein the conductor portion comprises a fuse (Fig. 3a: FUSE CIRCUITRY).
Claims 4 is rejected under 35 U.S.C. 103 as being unpatentable over Brannigan et al (US 5896040), Ma (US 6054334) and Graf et al (US 20060267721) in view of Eghan et al (US 7064450).
Regarding Claim 4, Brannigan, Ma, and Graf teach the limitations of claim 1. However they fail to teach wherein a third width of the conductor portion along the surface of the semiconductor component is less than a first width of the first conductive pad along the surface of the semiconductor component and less than a second width of the second conductive pad along the surface of the semiconductor component.
Eghan teaches wherein a third width of the conductor portion (Fig. 8: 805C) along the surface of the semiconductor component is less than a first width (Fig. 8: d2) of the first conductive pad (Fig. 8: 805P) along the surface of the semiconductor component and less than a second width (Fig. 8: d1) of the second conductive pad (Fig. 8: 805B) along the surface of the semiconductor component.
Pads need to be as large as possible to facilitate making contact with probes and wires bonded to their surface and connections tend to be as narrow as needed to facilitate charge transfer required by the device. Thus having a connection region with a width smaller than the width of the probe pads it connects would be an obvious design decision.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to combine the teachings of Eghen with the teachings of Brannigan, Ma, and Graf in order to produce a connection region with a width less than that of the width of either probe pad to which it is connected.
Allowable Subject Matter
Claims 7, 12, 16 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 7 would be allowable for teaching that probe pad is deformed by being contacted by a probe. None of the references cited make mention that the probe pad is deformed by the probe contacting it. Therefore, this limitation would be allowable if written in independent form.
Claim 12 would be allowable for the same reasons as claim 7.
Claim 16 would be allowable for teaching the relative resistivity of the probe pads and conductive element connecting them. None of the references cited make mention of the relative resistivity of these elements. Therefore, this limitation would be allowable if written in independent form.
Claim 18 would be allowable for teaching the relative thickness of the probe pads and conductive element in relation to each other. None of the references cited mention the thickness of these elements in relation to one another. Several mention relative widths but not the thickness or that the conductive element is thinner than the probe pads. Therefore, this limitation would be allowable if written in independent form.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Byrd et al (US 20030045013) teaches pads separated by a fuse element where one pad is used to access a semiconductor die.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH FIDELIS STORMES whose telephone number is (571)272-3443. The examiner can normally be reached M-F: 6:30am-4pm CST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Sofocleous can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JOSEPH FIDELIS STORMES/ Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/ Supervisory Patent Examiner, Art Unit 2825