DETAILED ACTION
The present Office Action is in response to Applicant Arguments/Remarks and amended claims filed on 08/06/2026. Claims 17, 27, 29, 35, and 37 have been amended. Claim 28 and 40 have been cancelled. Claims 1-16, 20-23, and 34 have been previously cancelled. Claim 41-43 have been added. Claims 17-19, 24-27, 29-33, 35-39, and 41-43 are pending in the application.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application, 16/564388 filed on 09/09/2019, under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Response to Amendments and Arguments
Applicant’s amendments and remarks have been fully considered, with the examiner’s response set forth below.
(1)Applicant’s arguments are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
(2) Another iteration of claim analysis has been made. Refer to the corresponding sections of the claim analysis below for details.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 17, 24-26, 36, and 41 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 2020/0371914), hereinafter Wang in view of King (US 2014/0089631), hereinafter King, and further in view of Zubair et al. (US2020/0379854), hereinafter Zubair and Foxworth et al. (US2019/0018713), hereinafter Foxworth.
Regarding claim 17, Wang teaches a system comprising:
a stacked memory (Wang, [0074], A volatile memory … HBM (High Bandwidth Memory); Note – HBM is a 3D-stacked DRAM memory); and
a processor (Wang, [0021], cores) configured to:
access application data at a first physical memory address associated with the stacked memory (Wang, [0074], A volatile memory … HBM (High Bandwidth Memory)) to service a first memory access request for a virtual memory address received from an application (Wang, [0023], received data is stored in memory buffer 270 and not in power-loss protected memory 272 … copy the data from memory buffer 270 to a region of memory that will not be erased in the event of power loss to the region of memory (e.g., power-loss protected memory 272; Note –memory buffer 270 is a volatile memory; [0027], data has not been copied from memory buffer 270 to power-loss protected memory 272 and the communication to cause the receiver to copy the data from the memory buffer to a persistent memory or non-volatile memory can cause or request a copying of the data from buffer 270 to power-loss protected memory 272); and
in response to a change in one or more operating conditions of the system, move the application data from the first physical memory address associated with the stacked memory to a second physical memory address associated with a different memory having reduced idle power consumption or reduced power consumption in self-refresh mode than the stacked memory (Wang, [0013]; [0104], the packet processing circuitry is to cause a region of a memory buffer that stores the data, in an event of power loss to the memory buffer, to be copied to a memory device whose state is determinate even if power is interrupted to the memory device), wherein the application data remains accessible to the application via the virtual memory address after the application data is moved to the second physical memory address associated with the different memory, and wherein the application continues to execute using the application data stored in the different memory while the stacked memory is in a self-refresh mode or is powered down.
Wang does not explicitly teach a first memory access request for a virtual memory address, a different memory having reduced idle power consumption or reduced power consumption in self-refresh mode than the stacked memory; and wherein the application data remains accessible to the application via the virtual memory address after the application data is moved to the second physical memory address associated with the different memory, and wherein the application continues to execute using the application data stored in the different memory while the stacked memory is in a self-refresh mode or is powered down, as claimed.
However, Wang in view of King teaches a first memory access request for a virtual memory address (King, [0014], the translation table is used during a DMA operation to map a virtual address provided by the I/O device to a physical address in the memory modules);
wherein the application data remains accessible to the application via the virtual memory address after the application data is moved to the second physical memory address associated with the different memory (King, [0038], the memory manager may change the physical address in one of the entries that previously mapped to a quick access memory 135—the DRAM—to a physical address on the energy efficient memory 130—the PCM. Accordingly, the next time the DMA engine performs a DMA operation involving the changed entry 405B, the operation may take more time to complete but consume less power than if the entry still mapped to a DRAM module).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Wang to incorporate teachings of King to map a virtual memory address of a user data to a first physical location and the user data can be accessed via the virtual memory address after the virtual memory address has been re-mapped to a second physical location. A person of ordinary skill in the art would have been motivated to combine the teachings of Wang with King because it improves efficiency and reliability of the storage system disclosed in Wang by ensuring correct data is stored at a new physical address (King, [0035]).
The combination of Wang does not explicitly teach a different memory having reduced idle power consumption or reduced power consumption in self-refresh mode than the stacked memory and wherein the application continues to execute using the application data stored in the different memory while the stacked memory is in a self-refresh mode or is powered down, as claimed.
However, the combination of Wang in view of Zubair teaches a different memory having reduced idle power consumption or reduced power consumption in self-refresh mode than the stacked memory (Zubair, [0007], Emerging Non-Volatile Memories (NVMs), such as Phase-Change Memory (PCM), are considered promising contenders for replacing DRAM due to their … ultra-low idle power, and low latency).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Wang to incorporate teachings of Zubair to use PCM as an energy efficiency memory for its reduced idle power consumption when comparing to a stacked DRAM memory. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Wang with Zubair because it improves efficiency of the storage system disclosed in the combination of Wang by using an energy efficiency memory with ultra-low idle power consumption.
The combination of Wang does not explicitly teach wherein the application continues to execute using the application data stored in the different memory while the stacked memory is in a self-refresh mode or is powered down, as claimed.
However, the combination of Wang in view of Foxworth teaches wherein the application continues to execute using the application data stored in the different memory (NVDIMMs) while the stacked memory is in a self-refresh mode or is powered down (Foxworth, [0015], NVDIMMs combine the speed of volatile memory with the persistence of non-volatile memory; [0019]; [0047], the volatile memory 206 may approach a thermal/power limit, and may be at risk for thermal/power induced failure (e.g., as indicated by sensor data). The NVDIMM memory controller 210 may then issue a volatile memory action 224 to power down the volatile memory 206 temporarily … The data may then be accessed directly from the non-volatile memory 208 by the one or more processing circuits. During copying, the NVDIMM memory controller 210 may generate a table that maps locations in the volatile memory 206 to corresponding locations in the non-volatile memory 208 where corresponding data is moved. When memory read/write commands come in, the NVDIMM memory controller 210 may translate the address from the volatile memory 206 to the corresponding address in the non-volatile memory 208, and it may retrieve the requests data from the non-volatile memory 208. Accordingly, the host device may operate (e.g., issue commands and read/write requests) as if the volatile memory 206 were still enabled; King, [0038]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Wang to incorporate teachings of Foxworth to access a nonvolatile random access memory (NVDIMM) when a volatile random access memory (such as a stacked DRAM) is unavailable due to power outage. A person of ordinary skill in the art would have been motivated to combine the combination of Wang with Foxworth because it improves efficiency and reliability of the storage system disclosed in the combination of Wang by allowing continued I/O access to a nonvolatile random access buffer memory in case of power outage.
Regarding claim 24, the combination of Wang teaches all the features with respect to claim 17 as outlined above. The combination of Wang further teach the system of claim 17, further comprising a memory map that identifies the first physical memory address associated with the stacked memory and the second physical memory address associated with the different memory (King, [0035], the memory manager may select physical addresses that correspond to a memory location on a different RAM device; Fig.3A; Foxworth, [0047]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Wang to incorporate teachings of King to identify a first physical memory address associated with a first memory (i.e. HBM in Wang) and a second physical memory address associated with a second memory (i.e. power-loss protected memory). A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Wang with King because it improves efficiency and reliability of the storage system disclosed in the combination of Wang by ensuring correct data is stored at a new physical address (King, [0035]).
Regarding claim 25, the combination of Wang teaches all the features with respect to claim 24 as outlined above. The combination of Wang further teaches the system of claim 24, wherein the processor is configured to move the application data from the first physical memory address associated with the stacked memory to the second physical memory address associated with the different memory based on the memory map that identifies the first physical memory address and the second physical memory address (King, [0035], when updating the translation table 145 as shown, the memory manager moves any data already stored at the previous physical address to the new physical address).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Wang to incorporate teachings of King to identify a first physical memory address associated with a first memory (i.e. HBM in Wang) and a second physical memory address associated with a second memory (i.e. power-loss protected memory) and move any data already stored at the first physical address to the second physical address when needed. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Wang with King because it improves efficiency and reliability of the storage system disclosed in the combination of Wang by ensuring correct data is stored at a new physical address (King, [0035]).
Regarding claim 26, the combination of Wang teaches all the features with respect to claim 17 as outlined above. The combination of Wang further teaches the system of claim 17, wherein the processor is configured to access the application data at the second physical memory address to service a second memory access request received from the application (King, [0038], If the DMA engine is underutilized—e.g., the engine has at least some idle time where it is not performing DMA operations—the memory manager may change the physical address in one of the entries that previously mapped to a quick access memory 135—the DRAM—to a physical address on the energy efficient memory 130—the PCM. Accordingly, the next time the DMA engine performs a DMA operation involving the changed entry 405B, the operation may take more time to complete but consume less power than if the entry still mapped to a DRAM module; Foxworth, [0047]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Wang to incorporate teachings of King to identify a first physical memory address associated with a first memory (i.e. HBM in Wang) and a second physical memory address associated with a second memory (i.e. power-loss protected memory) and move any data already stored at the first physical address to the second physical address when needed. As such, the subsequent access request is directed to the second physical memory address for I/O operations. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Wang with King because it improves efficiency and reliability of the storage system disclosed in the combination of Wang by ensuring correct data is stored at a new physical address and less power is consumed for performing I/O operations on low power memory (King, [0038]).
Regarding claim 36, the combination of Wang teaches all the features with respect to claim 17 as outlined above. The combination of Wang further teaches the system of claim 17, wherein a page table is updated to associate the virtual memory address with the second physical memory address associated with the different memory after the application data is moved from the first physical memory address to the second physical memory address (King, [0028], Depending on the performance metric, the memory manger 110 may update the translation table 145 to change the mappings from the virtual addresses to the physical memory address. For example, if the utilization rate of the DMA engine 155 is above 80%, the memory manager 110 may update the table 145 such that certain virtual addresses now map to physical memory address associated with memory modules that provide quick access instead of memory modules that are more energy efficient but have slower access times; Fig. 3A, 3B).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Wang to incorporate teachings of King to map a virtual memory address of a user data to a first physical location and the user data can be accessed via the virtual memory address after the virtual memory address has been re-mapped to a second physical location. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Wang with King because it improves efficiency and reliability of the storage system disclosed in the combination of Wang by ensuring correct data is stored at a new physical address (King, [0035]).
Regarding claim 41, the combination of Wang teaches all the features with respect to claim 17 as outlined above. The combination of Wang further teaches the system of claim 17, wherein the stacked memory and the different memory are byte-addressable by the processor (Wang, [0075], A NVM device can also comprise a byte-addressable write-in-place three dimensional cross point memory device, or other byte addressable write-in-place NVM device (also referred to as persistent memory), such as single or multi-level Phase Change Memory (PCM)).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Wang, King, Zubair, and Foxworth as applied to claim 17 above, and further in view of Jha et al. (US 2017/0185292), hereinafter Jha.
Regarding claim 18, the combination of Wang teaches all the features with respect to claim 17 as outlined above. The combination of Wang does not explicitly teach the system of claim 17, wherein the stacked memory comprises at least four dynamic random access memory dies, as claimed.
However, the combination of Wang in view of Jha teaches the system of claim 17, wherein the stacked memory comprises at least four dynamic random access memory dies (Jha, [0011], Another example of 3D memory is high bandwidth memory (HBM), which is also designed with up to eight DRAM dies in a stacked configuration).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Wang to incorporate teachings of Jha to include a 3D DRAM dies in a stacked configuration as volatile memory (i.e. cache/memory buffer 270 in Wang). A person of ordinary skill in the art would have been motivated to combine the combination of Wang with Jha because it improves performance of the storage system disclosed in the combination of Wang by using high performance high bandwidth volatile memory as cache and/or memory buffer.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Wang, King, Zubair, and Foxworth as applied to claim 17 above, and further in view of Chiang et al. (US 2011/0138112), hereinafter Chiang.
Regarding claim 19, the combination of Wang teaches all the features with respect to claim 17 as outlined above. The combination of Wang does not explicitly teach the system of claim 17, wherein the different memory comprises double data rate 4 (DDR4) or Low-Power Double Data Rate 4x (LPDDR4x), as claimed.
However, the combination of Wang in view of Chiang teaches the system of claim 17, wherein the different memory comprises double data rate 4 (DDR4) or Low-Power Double Data Rate 4x (LPDDR4x) (Chiang, [0033], In some implementations, the SSD 120 includes Double Data Rate (DDR) memory with a battery backup; Wang, [0074], DDR4 (DDR version 4)).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Wang to incorporate teachings of Chiang to include a solid state drive (SSD) of Double Data Rate memory (version 4) as power-loss protected memory (i.e. memory 272 in Wang). A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Wang with Chiang because it improves reliability of the storage system disclosed in the combination of Wang by using solid state drives as power-loss protected memory , which provides lower latency (than HDD) and greater storage capacity (Chiang, [0003]).
Claim(s) 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Wang, King, Zubair, and Foxworth as applied to claim 17 above, and further in view of Guim Bernat et al. (US 2019/0095122), hereinafter Guim Bernat.
Regarding claim 27, the combination of Wang teaches all the features with respect to claim 17 as outlined above. The combination of Wang does not explicitly teach the system of claim 17, wherein the stacked memory has a higher data throughput than the different memory, as claimed.
However, the combination of Wang in view of Guim Bernat teaches the system of claim 17, wherein the stacked memory has a higher data throughput than the different memory (Guim Bernat, [0079], one or more first memories of the computing system 600 may have a first maximal data bandwidth and one or more second memories of the computing system 600 may include a second maximal data bandwidth. In this case, the first maximal data bandwidth, e.g., of the HBM memory 602a, may be greater than the second maximal data bandwidth, e.g., of the DDR memory 602b, the NVM memories 602c, 602d, and/or the remote memory 602e, etc.).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Wang to incorporate teachings of Guim Bernat to have a high bandwidth memory (HBM) which has greater bandwidth than a Double Data Rate (DDR) type of memory. A person of ordinary skill in the art would have been motivated to combine the teachings of Wang with Guim Bernat by understanding the differences between a HBM and a DDR type of memory and using HBM for high performance operations.
Claim(s) 37 and 39 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Wang, King, Zubair, and Foxworth as applied to claim 17 above, and further in view of Brandl et al. (US2017/0351450), hereinafter Brandl.
Regarding claim 37, the combination of Wang teaches all the features with respect to claim 17 as outlined above. The combination of Wang further teaches the system of claim 17, wherein the change in the one or more operating conditions of the system comprises a temperature of the stacked memory exceeding a defined temperature threshold (Foxworth, [0047], the volatile memory 206 may approach a thermal/power limit), and wherein in response to the temperature of the stacked memory exceeding the defined temperature threshold, the processor is configured to move the application data from the first physical memory address associated with the stacked memory to the second physical memory address associated with the different memory (Foxworth, [0047], the volatile memory 206 may approach a thermal/power limit, and may be at risk for thermal/power induced failure (e.g., as indicated by sensor data). The NVDIMM memory controller 210 may then issue a volatile memory action 224 to power down the volatile memory 206 temporarily, and the NVDIMM memory controller 210 may issue a non-volatile memory action 226 to copy the data over to the non-volatile memory 208. The data may then be accessed directly from the non-volatile memory 208 by the one or more processing circuits. During copying, the NVDIMM memory controller 210 may generate a table that maps locations in the volatile memory 206 to corresponding locations in the non-volatile memory 208 where corresponding data is moved. When memory read/write commands come in, the NVDIMM memory controller 210 may translate the address from the volatile memory 206 to the corresponding address in the non-volatile memory 208, and it may retrieve the requests data from the non-volatile memory 208).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Wang to incorporate teachings of Foxworth to access a nonvolatile random access memory (NVDIMM) when a volatile random access memory is unavailable due to power outage. A person of ordinary skill in the art would have been motivated to combine the combination of Wang with Foxworth because it improves efficiency and reliability of the storage system disclosed in the combination of Wang by allowing continued I/O access to a nonvolatile random access buffer memory in case of power outage.
The combination of Wang teaches determining temperature change in a volatile memory, such as DRAM, nevertheless, the combination of Wang does not explicitly teach temperature change in a stacked memory, as claimed.
However, the combination of Wang in view of Brandl teaches a change in a temperature of the stacked memory (Brandl, [0021], Each of memory channels 130 and 140 can connect to state-of-the-art DDR memories such as DDR version four (DDR4), low power DDR4 (LPDDR4), graphics DDR version five (gDDR5), and high bandwidth memory (HBM) … data processor 110 includes a memory controller that is capable of throttling power in certain circumstances to avoid overheating and to reduce the chance of thermal overload).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Wang to incorporate teachings of Brandl to track temperature of high bandwidth memory (HBM) and take appropriate actions in response to determining the temperature of HBM exceeds a threshold (i.e. overheating). A person of ordinary skill in the art would have been motivated to combine the teachings of Wang with Brandl because it improves reliability of the storage system disclosed in the combination of Wang by ensuring data is stored in a nonvolatile memory during a power loss event or system crash.
Regarding claim 39, the combination of Wang teaches all the features with respect to claim 37 as outlined above. The combination of Wang teaches the system of claim 37, wherein the stacked memory is powered down after the application data is moved to the second physical memory address associated with the different memory (Foxworth, [0047], the volatile memory 206 may approach a thermal/power limit, and may be at risk for thermal/power induced failure (e.g., as indicated by sensor data). The NVDIMM memory controller 210 may then issue a volatile memory action 224 to power down the volatile memory 206 temporarily, and the NVDIMM memory controller 210 may issue a non-volatile memory action 226 to copy the data over to the non-volatile memory 208; Brandl, [0021], high bandwidth memory (HBM); [0055], ADR is a feature used in servers to flush pending write data into a non-volatile memory during a power failure or system crash. DRAMs and PHYs are again placed into precharge power down with auto self refresh enabled;).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Wang to incorporate teachings of Brandl to power down a DRAM type memory after DRAM data is flushed into non-volatile memory during a power failure or system crash. A person of ordinary skill in the art would have been motivated to combine the teachings of Wang with Brandl because it improves reliability of the storage system disclosed in the combination of Wang by ensuring data is stored in a permanent storage during a power loss event or system crash.
Claim(s) 38 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Wang, King, Zubair, Foxworth, and Brandl as applied to claim 37 above, and further in view of Peng et al. (US2019/0235965), hereinafter Peng.
Regarding claim 38, the combination of Wang teaches all the features with respect to claim 37 as outlined above. The combination of Wang does not explicitly teach the system of claim 37, wherein the stacked memory is placed in the self-refresh mode after the application data is moved to the second physical memory address associated with the different memory, as claimed.
However, the combination of Wang in view of Peng teaches the system of claim 37, wherein the stacked memory is placed in a self-refresh mode after the application data is moved to the second physical memory address associated with the different memory (Peng, [0028], This interruption flushes the write-protected data buffers in the memory modules 160 and places the dynamic random access memory (DRAM) into a self-refresh mode).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Wang to incorporate teachings of Peng to flush data from a DRAM buffer and place the DARM buffer into a self-refresh mode in response to an hardware interruption. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Wang with Peng because it improves reliability of the storage system disclosed in the combination of Wang by ensuring data is in a permanent storage state during a power loss event or system crash (Peng, [0028]).
Claim(s) 43 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Wang, King, Zubair, and Foxworth as applied to claim 17 above, and further in view of Kumar et al. (US2018/0143678), hereinafter Kumar.
Regarding claim 43, the combination of Wang teaches all the features with respect to claim 17 as outlined above. The combination of Wang does not explicitly teach the system of claim 17, wherein the change in the one or more operating conditions of the system comprises a power connection status indicating that the system has switched from a high-availability power supply to a limited power supply, and wherein in response to the power connection status indicating the switch to the limited power supply, the processor is configured to move the application data from the first physical memory address associated with the stacked memory to the second physical memory address associated with the different memory, as claimed.
However, the combination of Wang in view of Kumar teaches the system of claim 17, wherein the change in the one or more operating conditions of the system comprises a power connection status indicating that the system has switched from a high-availability power supply to a limited power supply, and wherein in response to the power connection status indicating the switch to the limited power supply, the processor is configured to move the application data from the first physical memory address associated with the stacked memory to the second physical memory address associated with the different memory (Kumar, [0022]; [0023], Data stored in the DRAM can be copied into the NVRAM before the computer system transitions into a sleep state).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Wang to incorporate teachings of Kumar to move data stored in DRAM/HBM to a nonvolatile memory such as NVRAM or PCM when s storge system is transitioning into a sleep state. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Wang with Kumar because it improves efficiency of the storage system disclosed in the combination of Wang by moving data from volatile memory to nonvolatile memory for reduced power consumption and data persistency.
Claim(s) 29, 30, and 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 2020/0371914), hereinafter Wang in view of Brandl et al. (US 2017/0351450), hereinafter Brandl, and further in view of King (US 2014/0089631), hereinafter King, Zubair et al. (US2020/0379854), hereinafter Zubair, and Foxworth et al. (US2019/0018713), hereinafter Foxworth.
Regarding claim 29, Wang teaches a computing device comprising:
a stacked memory (Wang, [0074], A volatile memory … HBM (High Bandwidth Memory); Note – HBM is a 3D stacked DRAM); and
a processor (Wang, [0021], cores) configured to:
access application data at a first physical memory address associated with the stacked memory (Wang, [0074], A volatile memory … HBM (High Bandwidth Memory)) to service a first memory access request for a virtual memory address received from an application (Wang, [0023], received data is stored in memory buffer 270 and not in power-loss protected memory 272 … copy the data from memory buffer 270 to a region of memory that will not be erased in the event of power loss to the region of memory (e.g., power-loss protected memory 272; Note – indicating memory buffer 270 is a volatile memory; [0027], data has not been copied from memory buffer 270 to power-loss protected memory 272 and the communication to cause the receiver to copy the data from the memory buffer to a persistent memory or non-volatile memory can cause or request a copying of the data from buffer 270 to power-loss protected memory 272); and
in response to a change in a temperature of the stacked memory, move the application data from the first physical memory address associated with the stacked memory to a second physical memory address associated with a different memory having reduced idle power consumption than the stacked memory (Wang, [0013]; [0104], the packet processing circuitry is to cause a region of a memory buffer that stores the data, in an event of power loss to the memory buffer, to be copied to a memory device whose state is determinate even if power is interrupted to the memory device), wherein the application data remains accessible to the application via the virtual memory address after the application data is moved to the second physical memory address associated with the different memory, and wherein the application continues to execute using the application data stored in the different memory while the stacked memory is in a self-refresh mode or is powered down.
Wang does not explicitly teach a change in a temperature of the stacked memory; a first memory access request for a virtual memory address; a different memory having reduced idle power consumption than the stacked memory; and wherein the application data remains accessible to the application via the virtual memory address after the application data is moved to the second physical memory address associated with the different memory, and wherein the application data remains accessible to the application via the virtual memory address after the application data is moved to the second physical memory address associated with the different memory, and wherein the application continues to execute using the application data stored in the different memory while the stacked memory is in a self-refresh mode or is powered down, as claimed.
However, the combination of Wang in view of Brandl teaches a change in a temperature of the stacked memory (Brandl, [0021], Each of memory channels 130 and 140 can connect to state-of-the-art DDR memories such as DDR version four (DDR4), low power DDR4 (LPDDR4), graphics DDR version five (gDDR5), and high bandwidth memory (HBM) … data processor 110 includes a memory controller that is capable of throttling power in certain circumstances to avoid overheating and to reduce the chance of thermal overload).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Wang to incorporate teachings of Brandl to track temperature of high bandwidth memory (HBM) and take appropriate actions in response to determining the temperature of HBM exceeds a threshold (i.e. overheating). A person of ordinary skill in the art would have been motivated to combine the teachings of Wang with Brandl because it improves reliability of the storage system disclosed in Wang by ensuring data is stored in a permanent storage during a power loss event or system crash.
The combination of Wang does not explicitly teach a first memory access request for a virtual memory address, a different memory having reduced idle power consumption than the stacked memory; and wherein the application data remains accessible to the application via the virtual memory address after the application data is moved to the second physical memory address associated with the different memory and wherein the application data remains accessible to the application via the virtual memory address after the application data is moved to the second physical memory address associated with the different memory, and wherein the application continues to execute using the application data stored in the different memory while the stacked memory is in a self-refresh mode or is powered down, as claimed.
However, the combination of Wang in view of King teaches a first memory access request for a virtual memory address (King, [0014], the translation table is used during a DMA operation to map a virtual address provided by the I/O device to a physical address in the memory modules);
wherein the application data remains accessible to the application via the virtual memory address after the application data is moved to the second physical memory address associated with the different memory (King, [0038], the memory manager may change the physical address in one of the entries that previously mapped to a quick access memory 135—the DRAM—to a physical address on the energy efficient memory 130—the PCM. Accordingly, the next time the DMA engine performs a DMA operation involving the changed entry 405B, the operation may take more time to complete but consume less power than if the entry still mapped to a DRAM module).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Wang to incorporate teachings of King to map a virtual memory address of a user data to a first physical location and the user data can be accessed via the virtual memory address after the virtual memory address has been re-mapped to a second physical location. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Wang with King because it improves efficiency and reliability of the storage system disclosed in the combination of Wang by ensuring correct data is stored at a new physical address (King, [0035]).
The combination of Wang does not explicitly teach a different memory having reduced idle power consumption than the stacked memory and wherein the application continues to execute using the application data stored in the different memory while the stacked memory is in a self-refresh mode or is powered down, as claimed.
However, the combination of Wang in view of Zubair teaches a different memory having reduced idle power consumption than the stacked memory (Zubair, [0007], Emerging Non-Volatile Memories (NVMs), such as Phase-Change Memory (PCM), are considered promising contenders for replacing DRAM due to their … ultra-low idle power, and low latency).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Wang to incorporate teachings of Zubair to use PCM as the energy efficiency memory for its reduced idle power consumption when comparing to a stacked DRAM memory. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Wang with Zubair because it improves efficiency of the storage system disclosed in the combination of Wang by using an energy efficiency memory with ultra-low idle power consumption.
The combination of Wang does not explicitly teach wherein the application continues to execute using the application data stored in the different memory while the stacked memory is in a self-refresh mode or is powered down, as claimed.
However, the combination of Wang in view of Foxworth teaches wherein the application continues to execute using the application data stored in the different memory while the stacked memory is in a self-refresh mode or is powered down (Foxworth, [0015], NVDIMMs combine the speed of volatile memory with the persistence of non-volatile memory; [0019]; [0047], the volatile memory 206 may approach a thermal/power limit, and may be at risk for thermal/power induced failure (e.g., as indicated by sensor data). The NVDIMM memory controller 210 may then issue a volatile memory action 224 to power down the volatile memory 206 temporarily … The data may then be accessed directly from the non-volatile memory 208 by the one or more processing circuits. During copying, the NVDIMM memory controller 210 may generate a table that maps locations in the volatile memory 206 to corresponding locations in the non-volatile memory 208 where corresponding data is moved. When memory read/write commands come in, the NVDIMM memory controller 210 may translate the address from the volatile memory 206 to the corresponding address in the non-volatile memory 208, and it may retrieve the requests data from the non-volatile memory 208. Accordingly, the host device may operate (e.g., issue commands and read/write requests) as if the volatile memory 206 were still enabled; King, [0038]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Wang to incorporate teachings of Foxworth to access a nonvolatile random access memory (NVDIMM) when a volatile random access memory is unavailable due to power outage. A person of ordinary skill in the art would have been motivated to combine the combination of Wang with Foxworth because it improves efficiency and reliability of the storage system disclosed in the combination of Wang by allowing continued I/O access to a nonvolatile random access buffer memory in case of power outage.
Regarding claim 30, the combination of Wang teaches all the features with respect to claim 29 as outlined above. The combination of Wang further teaches the computing device of claim 29, wherein the stacked memory comprises a high bandwidth memory (Wang, [0074], A volatile memory … HBM (High Bandwidth Memory)).
Regarding claim 32, the combination of Wang teaches all the features with respect to claim 29 as outlined above. The combination of Wang further teaches the computing device of claim 29, wherein the change in the temperature comprises the temperature of the stacked memory exceeding a defined temperature threshold (Foxworth, [0047], in response to the sensor data breaching the set of threshold values, the volatile memory 206 may be powered down, and the data may be copied (e.g., read then written) to the non-volatile memory 208. In some embodiments, the volatile memory 206 may approach a thermal/power limit, and may be at risk for thermal/power induced failure (e.g., as indicated by sensor data). T).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Wang to incorporate teachings of Foxworth to monitor and determine whether a volatile memory (HBM in Wang) exceeds a thermal (i.e. temperature) limit. A person of ordinary skill in the art would have been motivated to combine the combination of Wang with Foxworth because it improves efficiency and reliability of the storage system disclosed in the combination of Wang by allowing continued I/O access to a nonvolatile random access buffer memory in case of power outage.
Claim(s) 31 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Wang, Brandl, King, Zubair, and Foxworth as applied to claim 29 above, and further in view of Jha et al. (US 2017/0185292), hereinafter Jha
Regarding claim 31, the combination of Wang teaches all the features with respect to claim 29 as outlined above. The combination of Wang does not explicitly teach the computing device of claim 29, wherein the stacked memory comprises at least four dynamic random access memory dies, as claimed.
However, the combination of Wang in view of Jha teaches the computing device of claim 29, wherein the stacked memory comprises at least four dynamic random access memory dies (Jha, [0011], Another example of 3D memory is high bandwidth memory (HBM), which is also designed with up to eight DRAM dies in a stacked configuration).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Wang to incorporate teachings of Jha to include a 3D DRAM dies in a stacked configuration as volatile memory (i.e. cache/memory buffer 270 in Wang). A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Wang with Jha because it improves performance of the storage system disclosed in the combination of Wang by using high performance high bandwidth volatile memory as cache and/or memory buffer.
Claim(s) 33 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Wang, Brandl, King, Zubair, and Foxworth as applied to claim 29 above, and further in view of Peng et al. (US2019/0235965), hereinafter Peng.
Regarding claim 33, the combination of Wang teaches all the features with respect to claim 29 as outlined above. The combination of Wang does not explicitly teach the computing device of claim 29, wherein the stacked memory is placed in the self-refresh mode after the application data is moved to the second physical memory address associated with the different memory, as claimed.
However, the combination of Wang in view of Peng teaches the computing device of claim 29, wherein the stacked memory is placed in the self-refresh mode after the application data is moved to the second physical memory address associated with the different memory (Peng, [0028], This interruption flushes the write-protected data buffers in the memory modules 160 and places the dynamic random access memory (DRAM) into a self-refresh mode).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Wang to incorporate teachings of Peng to flush data from a DRAM buffer and place the DARM buffer into a self-refresh mode in response to a hardware interruption. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Wang with Peng because it improves reliability of the storage system disclosed in the combination of Wang by ensuring data is stored in a permanent storage during a power loss event or system crash (Peng, [0028]).
Allowable Subject Matter
Claim 42 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 42 recites “[t]he system of claim 17, wherein the processor is configured to maintain the stacked memory in the self-refresh mode or powered down until a hysteresis time-out period has elapsed”.
The above-noted limitation, in combination with the other limitation of the claims, are neither disclosed nor suggested by the prior art of record. Therefore, in the context of claims 17 and 42 as a whole, the prior art does not teach the claimed subject matter. Thus, the subject matter of claim 42 is allowable.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NANCI N WONG/Primary Examiner, Art Unit 2137
