Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
This action is responsive to the application 18/745,783 filed on June 17, 2024. Claims 1-19 are pending.
Claim Objections
Claims 18-19 are objected to because of the following informalities:
Claim 18 recites “converting the instruction information into one or more Reduced Instruction Set Computer (RISC) instructions or Complex Instruction Set Computer (CISC) instructions…, and the one or more CISC instructions selected…”, the Examiner suggests to amend as “converting the instruction information into one or more Reduced Instruction Set Computer (RISC) instructions or one or more Complex Instruction Set Computer (CISC) instructions…, and the one or more CISC instructions selected…”.
Claim 19 recites “The computer program comprising a program code…”, the Examiner suggests to amend as “A computer program comprising a program code …”.
Appropriate corrections are required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 19 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter.
The claim 19 recites “The computer program comprising a program code for performing the method according to claim 18, when executed by processing circuitry”. Thus, applying the broadest reasonable interpretation in light of the specification, there is no structural element(s) to store the computer program. Therefore, the claim is directed to program/software per se which does/do not fall within at least one of the four categories of patent eligible subject matter because program/software per se is not a useful process, a machine, a manufacture, or a composition of matter. Therefore, claim 19 is directed towards non-statutory subject matter.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 10-12, 17-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by van Koren et al. (US 2012/0263462) hereinafter “Koren”.
Claim 1
Koren teaches a device for a gateway controller of a user equipment [i.e. network processors operable in residential gateway] (Koren, 0001), the device comprising processing circuitry configured to:
receive one or more input frames of bits, wherein the one or more input frames comprise data and instruction information that indicates one or more processing tasks to be executed on the data [i.e. the ingress handler 380 performs the tasks related to determining the destination memory for a payload of an incoming packet, determining which of clusters 370 should process the incoming packet and offloading tasks; the ingress handler determines the destination memory for the packet payload based on the results of the packet parsed information (e.g. protocol type, VLAN tags, priority bits); and each of packet processors 371 is designed to perform certain tasks to enable efficient and fast processing of packets, the header manipulation QoS mapping tasks are performed by the secondary packet processor] (Koren, 0022, 0024, 0038-0039);
convert the instruction information into one or more Reduced Instruction Set Computer (RISC) instructions or one or more Complex Instruction Set Computer (CISC) instructions, the one or more RISC instructions selected from an RISC instruction set, and the one or more CISC instructions selected from an CISC instruction set [i.e. the core 410 in the main packet processors 371A may be a RISC processor that is designed to execute processing tasks with a minimal latency; and the core 470 may be a RISC processor, while the execution of tasks by the core 470 is scheduled by the scheduler 480] (Koren, 0034, 0037); and
execute the one or more processing tasks on the data of the one or more input frames based on the one or more RISC instructions or the one or more CISC instructions [i.e. the scheduler 460 triggers the execution of the one or more tasks assigned to the main packet processor; and the execution of the processing tasks by the secondary packet processor takes place] (Koren, fig. 5, S530 & S550; 0046-0047).
Claim 2
Koren teaches the device according to claim 1, wherein the processing circuitry comprises: a processor configured to convert the instruction information of the input frame into the one or more RISC instructions or the one or more CISC instructions [i.e. the ingress handler 380 preprocesses an incoming packet to determine at least the destination cluster and memory 355 or 365 for the packet. The ingress handler 380 parses the incoming packet and provides the parsed data including the packet descriptor and packet headers to the data memory 430]; and one or more hardware accelerators (HWAs) configured to execute the one or more processing tasks on the data of the one or more input frames based on the one or more RISC instructions or the one or more CISC instructions received from the processor [i.e. RISC processors 410 and 470] (Koren, fig. 5; 0045).
Claim 3
Koren teaches the device according to claim 2, wherein the processor is further configured to provide a plurality of RISC instructions or a plurality of CISC instructions in parallel to a plurality of HWAs [i.e. each of the packet processors 371A and 372A supports a multitask architecture, thus at any specific time more than one packet is being processed; and the cluster of packet processors does not require completing the processing of a packet before starting to process the next packet] (Koren, 0048).
Claim 4
Koren teaches the device according to claim 2, wherein the processor is further configured to, based on the one or more RISC instructions or the one or more CISC instructions:
schedule the execution of the one or more processing tasks by the one or more HWAs [i.e. the scheduler 460 triggers the execution, at S530, of the one or more tasks assigned to the main packet processor 371A] (Koren, fig. 5, S530; 0046); and/or
select, for each respective HWA of the one or more HWAs, one input frame of a subset of the input frames allocated to the respective HWA, to execute a processing task on the data of the selected input frame [i.e. at S550, the execution of the processing tasks by the secondary packet processor 372A takes place] (Koren, fig. 5, S550; 0047).
Claim 10
Koren teaches the device according to claim 2, wherein the one or more input frames comprise: one or more data frames including the data; and one or more instruction frames, wherein each instruction frame comprises an instruction, and wherein the one or more instructions of the one or more instruction frames constitute the instruction information [i.e. the incoming packet comprises the parsed data including the packet descriptor and packet headers to the data memory 430] (Koren, 0045).
Claim 11
Koren teaches the device according to claim 10, wherein: the processor is configured to receive the one or more instruction frames and to determine the instruction information from the one or more instruction frames; and the one or more HWAs are configured to receive the one or more data frames and to execute the one or more processing tasks on the data in the one or more data frames [i.e. the ingress handler 380 preprocesses an incoming packet to determine at least the destination cluster and memory 355 or 365 for the packet. The ingress handler 380 parses the incoming packet and provides the parsed data including the packet descriptor and packet headers to the data memory 430] (Koren, 0045).
Claim 12
Koren teaches the device according to claim 11, wherein: the one or more HWAs are configured to output one or more processed data frames including processed data as a result of executing the one or more processing tasks on the data; and/or the processor is configured to perform one or more further processing tasks on the one or more instruction frames and to output as a result one or more processed instruction frames [i.e. at S560, once the processing is completed by the secondary packet processor 372A, a transmit command is sent to the broad bus handler that the processed packet is ready to be sent to its destination] (Koren, 0048).
Claim 17
Koren teaches the device according to claim 1, wherein each input frame of the one or more input frames has or is derived from one of the following frame formats: - Controller Area Network, CAN; - CAN Flexible Data Rate; - CAN XL; - Local Interconnect Network; - FlexRay; - Media Oriented System Transport; - Ethernet; - Mobile Industry Processor Interface; - Camera Serial Interface 2 [i.e. Ethernet MAC Adapter] (Koren, fig. 3).
Claim 18 does not teach or define any new limitation other than above claim 1. Therefore, claim 18 is rejected for similar reasons.
Claim 19
Koren teaches the computer program comprising a program code for performing the method according to claim 18, when executed by processing circuitry [i.e. the carious processes and functions may be either part of microinstruction code or part of the application program or any combination thereof which is executed by a CPU] (Koren, 0051).
Allowable Subject Matter
Claims 5-9, 13-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure (see PTO-892).
US 2017/0072876 issued to Rajan et al., teaches hardware accelerated protocol conversion in an automotive gateway controller.
US 2023/0168892 issued to Wang et al., teaches a RISC-V based 3D interconnected multi-core processor architecture and a working method thereof.
US 7,047,394 issued to Van Dyke et al., teaches computer for execution of RISC and CISC instruction sets.
Correspondence Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MINH CHAU N NGUYEN whose telephone number is (571)272-4242. The examiner can normally be reached on M-F 8am-4pm.
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/MINH CHAU NGUYEN/Primary Examiner, Art Unit 2459