DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Other References: Wang (US 20210374004) – Refresh management for DRAM.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9, 11-17 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 22922031) and in view of Richter (US 10141042) and Nale (US 20220293162)
Claim 1. Lee discloses An integrated circuit device (eg., col 4:24-33 - memory 100 including a semiconductor die assembly, including a 3DI device or a die-stacked package), comprising:
a high-bandwidth memory (HBM) device comprising a stack of dynamic random access memory (DRAM) dies, wherein the DRAM dies comprise respective banks of memory cells and control circuitry configured to, (eg., col 4:28-35 - memory 100 can include a DRAM (e.g., DDR4 DRAM, DDR5 DRAM, LP DRAM, HBM DRAM, etc.), or a portion thereof that includes one or more dies/chips… memory cells)
process a command directed to, wherein the command comprises an address of a target row of the memory cells within the bank (eg., col 4:9-15 - FIG. 1A can selectively communicate DRFM row address sampling commands using one or more existing commands, such as: write pattern with auto precharge (WRPA) command, a write with auto precharge (WRA) command, a read with auto precharge (RDA) command, and a precharge per bank (PREpb) command… to identify a specific bank)
and wherein the command further comprises one or more of an activate command and a first precharge command (see col 7:30-32 - an active signal (ACT) and/or a precharge signal (Pre)), and
capture the address of the target row of memory cells (eg., col 8:15-25 - generating or activating a DRFM capture signal 284, when the targeted bank is open; col 10:4-15 - (52) As illustrated in FIG. 3, a first DRFM capture 310 can be processed while the bank activation signal 302 is active)
Lee does not disclose, but Richter discloses
a directed refresh management (DRFM) flag field (eg., col 4:49-55 - bank n active flag signal on the s6 node may indicate whether bank n refresh operation is active)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the dram stack with active command and precharge commands as disclosed by Lee, with Richter, providing the benefit of schedule a combination of row precharge and refresh operations (see Richter, col 5:1-5) High data reliability, high speed of memory access, and reduced chip size are features that are demanded from semiconductor memory (col 1:6-8).
Lee in view of Richter does not disclose, but Nale discloses
one of the banks of the memory cells (eg., [0026] directed Refresh management (DRFM) commands are sent to either all banks (DRFMab) or to the same bank in all bank groups (DRFMsb)),
based on a condition that the DRFM flag field is set (eg., 0084 - The DRFM command is expected to be provided after the memory device has an address captured for the multiple banks that will be the subject of the DRFM command. As such, most or all of the banks affected by the DRFM command will have an address to use for row hammer mitigation).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the dram stack with active command and precharge commands as disclosed by Lee, with Richter, with Nale providing the benefit of memory controller can randomize the sending of the DRFM commands. The controller can generate commands to indicate the memory device should capture addresses for various banks to use for pTRR operations (see Nale, 0026) Better use of the bandwidth required to perform row hammer mitigation, increases the possibility to mitigate more types of attacks with less bandwidth loss (0028).
Claim 2. Lee does not disclose, but Richter discloses
wherein the command comprises the activate command, and wherein the control circuitry is further configured to: (eg., col 3:38-40 - access command is either ACTIVATE (ACT) )
open the bank based on the activate command (eg., col 5:15-20 - an ACT m command to select or open a row of the bank m)
receive a column command directed to the target row of memory cells, while the bank is open (eg., col 2:58-61 - semiconductor memory device 20 may include a command/address decoder 22 that may receive a command (e.g., read, write, etc.));
execute the column command on the target row of memory cells while the bank is open (eg., col 5:15-20 - a RD/WR n command to perform a read or write access to the bank n that has already been opened by the previous ACT n command); and
close the bank based on a second precharge command directed to the bank, subsequent to executing the column command (eg., col 5:20-25 - a PRE-REF m command to close the open row of the bank ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the dram stack with active command and precharge commands as disclosed by Lee, with Richter, providing the benefit of schedule a combination of row precharge and refresh operations (see Richter, col 5:1-5) High data reliability, high speed of memory access, and reduced chip size are features that are demanded from semiconductor memory (col 1:6-8).
Claim 3. Lee discloses wherein the control circuitry is further configured to: capture the address of the target row of memory cells if the DRFM flag field is set, without opening the bank (eg., col 8:11-29 - receive and temporarily retain the first command 122 and the target address 112 of FIG. 1A. While retaining the information, the RHR logic 281 can determine an opened/closed status of the memory bank… when the targeted memory bank is closed, the RHR logic 281 can be configured to block propagation of the first command 122 and/or the target address 112, such by maintaining the DRFM capture signal 284 at an inactive state. As a result, the refresh control circuit 280 can respond to the DRFM capture signal 284 by (1) latching or updating the tracked refresh address with the target address 112 when the memory bank is in the opened state and (2) ignoring the target address 112 and retaining the previously stored address when the memory bank is in the closed state.) .
Claim 4. Lee discloses wherein the control circuitry is further configured to: execute a directed refresh management (DRFM) event based on the captured address of the target row of memory cells (eg., col 8:30-33 - RHR logic 281 can include a DRFM capture register 282 and corresponding control logic configured to process the DRFM commands 110 and/or control the DRFM capture signal 284).
Claim 5. Lee discloses wherein the control circuitry is further configured to: execute the DRFM event based further on a refresh management per page command directed to the address of the bank (eg., col 5:35-45 - FIG. 3, and then may check a status of a page (or a row) in the bank, whether the page is open (S501). For this purpose, although not shown in FIG. 3, the memory controller 31 may have a plurality of bank status registers corresponding respectively to a plurality of banks provided in the semiconductor memory device. Each register of the registers may store information indicating whether any page of the bank to be refreshed is open.).
Claim 6. Lee discloses wherein the control circuitry is further configured to: receive the command while the bank is open (eg., col 10:5-10 - the memory 100 can update the DRFM register value 306 based on the corresponding active/opened bank status).
Claim 7. Lee does not disclose, but Richter discloses
wherein the control circuitry is further configured to: receive a column command directed to the target row of memory cells while the bank is open; and execute the column command on the target row of memory cells while the bank is open (eg., col 5:15-25 - he memory controller may issue or provide five commands in sequence, which include an ACT m command to select or open a row of the bank m, a RD/WR n command to perform a read or write access to the bank n that has already been opened by the previous ACT n command, a PRE-REF m command to close the open row of the bank m and then initiate a refresh operation on the bank m, another RD/WR n command to perform a read or write access to another row of the bank n, and an ACT m command to select or open a row of the bank m for performing a read or write access to the bank)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the dram stack with active command and precharge commands as disclosed by Lee, with Richter, providing the benefit of schedule a combination of row precharge and refresh operations (see Richter, col 5:1-5) High data reliability, high speed of memory access, and reduced chip size are features that are demanded from semiconductor memory (col 1:6-8).
Claim 8. Lee discloses wherein the control circuitry is further configured to: capture the address of the target row of memory cells if the DRFM flag is set, without executing a column command on the target row of memory cells (eg., col 2:12-40 - to command and initiate refresh operations, such as row hammer refreshes (RHRs), at a memory device (e.g., DRAM). The control device can use a set of commands, such as an address capture/sampling command and a service or initiation command, to command the refresh operation… refresh operation to replenish or reestablish the charge levels at the neighboring WLs).
Claim 9. Lee discloses wherein the control circuitry is further configured to: capture the address of the target row of memory cells if the DRFM flag is set and a mode register bit is set (eg., col 8:16-35 - RHR logic 281 can be configured to pass or continue processing the first command 122 and the target address 112, such as by generating or activating a DRFM capture signal 284, when the targeted bank is open… include a DRFM capture register 282 and corresponding control logic configured to process the DRFM commands 110 and/or control the DRFM capture signal 284. ).
Claim 11. Lee discloses wherein the command comprises the precharge command, and wherein the precharge command comprises one of: a multi-cycle precharge per-bank command; and a single-cycle precharge command in which a pseudo-channel field of a unit interval of the single-cycle precharge command serves as the DRFM flag field (eg., col 10:40-45 - operating the command decoder can include controlling the activation and/or precharging of a targeted bank as illustrated at block 422; col 4:9-16 - FIG. 1A can selectively communicate DRFM row address sampling commands using one or more existing commands, such as: write pattern with auto precharge (WRPA) command, a write with auto precharge (WRA) command, a read with auto precharge (RDA) command, and a precharge per bank (PREpb) command. Each of these existing commands can use a predetermined set/locations of bits to identify a specific bank. )
Claim 12. Lee discloses A system (eg., col 10 Fig. 1A - system 101 ), comprising:
a host device configured to (eg., col 2:64 Fig. 1A – host device 103).
interface with a high-bandwidth memory (HBM) device that comprises a stack of dynamic random access memory (DRAM) dies, wherein the DRAM dies comprise respective banks of memory cells (eg., col 4:25-40 - DRAM (e.g., DDR4 DRAM, DDR5 DRAM, LP DRAM, HBM DRAM, etc.), or a portion thereof that includes one or more dies/chips. In some embodiments, the memory 100 can include synchronous DRAM (SDRAM) of DDR type integrated on a single semiconductor chip… DRAM (e.g., DDR4 DRAM, DDR5 DRAM, LP DRAM, HBM DRAM, etc.), or a portion thereof that includes one or more dies/chips. In some embodiments, the memory 100 can include synchronous DRAM (SDRAM) of DDR type integrated on a single semiconductor chip), and
issue a first activate command directed to a bank of the DRAM dies (eg., col 10:23-24 - At block 401, the memory 100 can receive an activation command and a corresponding address. ),
wherein the first activate command comprises an address of the bank, an address of a target row of memory cells within the bank (eg., col 1025-27 - receive the activation command for accessing a row and a corresponding address 112 of FIG. 1A ), and
.
Lee does not disclose, but Richter discloses
a directed refresh management (DRFM) flag field (eg., col 4:49-55 - bank n active flag signal on the s6 node may indicate whether bank n refresh operation is active)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the dram stack with active command and precharge commands as disclosed by Lee, with Richter, providing the benefit of schedule a combination of row precharge and refresh operations (see Richter, col 5:1-5) High data reliability, high speed of memory access, and reduced chip size are features that are demanded from semiconductor memory (col 1:6-8).
Lee in view of Richter does not disclose, but Nale discloses
one of the banks of the memory cells (eg., [0026] directed Refresh management (DRFM) commands are sent to either all banks (DRFMab) or to the same bank in all bank groups (DRFMsb)), 0084 - The DRFM command is expected to be provided after the memory device has an address captured for the multiple banks that will be the subject of the DRFM command. As such, most or all of the banks affected by the DRFM command will have an address to use for row hammer mitigation).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the dram stack with active command and precharge commands as disclosed by Lee, with Richter, with Nale providing the benefit of memory controller can randomize the sending of the DRFM commands. The controller can generate commands to indicate the memory device should capture addresses for various banks to use for pTRR operations (see Nale, 0026) Better use of the bandwidth required to perform row hammer mitigation, increases the possibility to mitigate more types of attacks with less bandwidth loss (0028).
Claim 13. Lee discloses issue a first precharge command to close the bank; issue the first activate command subsequent to issuing the first precharge command; and (eg., col 7:30-38 - a precharge signal (Pre) from the command decoder 215, etc. The command decoder 215 can generate the active signal (ACT) (e.g., a pulse signal) when the command signals (CMD) indicates row access (e.g., active command). The command decoder 215 can generate the precharge signal (Pre) (e.g., a pulse signal) when the command signal (CMD) indicates pre-charge. ).
Lee does not disclose, but Richter discloses
a predetermined amount of time (eg., col 1:39 - minimum row access cycle time tRAS).
issue a second precharge command to close the bank, subsequent to issuing the first precharge command (eg., col 7:4-7 - a second command that is a precharge command PRE for a row in bank 0 at time T2 that is at least the minimum row access cycle time tRAS later than time T1)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the dram stack with active command and precharge commands as disclosed by Lee, with Richter, providing the benefit of schedule a combination of row precharge and refresh operations (see Richter, col 5:1-5) High data reliability, high speed of memory access, and reduced chip size are features that are demanded from semiconductor memory (col 1:6-8).
Claim 14. Lee does not disclose, but Richter discloses
wherein the host device is further configured to: issue a column command directed to the bank subsequent to issuing the first activate command; and issue the second precharge command subsequent to issuing the column command (eg., col 7:29-35 - a third command that is a precharge-refresh command PRE-REF for rows in bank 0 at time T3 that is at least the minimum row precharge time tRP later than time T2. T)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the dram stack with active command and precharge commands as disclosed by Lee, with Richter, providing the benefit of schedule a combination of row precharge and refresh operations (see Richter, col 5:1-5) High data reliability, high speed of memory access, and reduced chip size are features that are demanded from semiconductor memory (col 1:6-8).
Claim 15. Lee does not disclose, but Richter discloses
wherein the host device is further configured to: issue the second precharge command to close the bank, subsequent to issuing the first precharge command, without issuing an intervening column command directed to the target row of memory cells (eg., col 8:20-25 - provides the precharge-refresh command PRE-REF at time T6 immediately after providing the row activation command ACT at time T5,).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the dram stack with active command and precharge commands as disclosed by Lee, with Richter, providing the benefit of schedule a combination of row precharge and refresh operations (see Richter, col 5:1-5) High data reliability, high speed of memory access, and reduced chip size are features that are demanded from semiconductor memory (col 1:6-8).
Claim 16. Lee does not disclose, but Richter discloses
wherein the host device is further configured to: issue a second activate command with the DRFM flag field un-set; and issue the first activate command directed to the bank, while the bank is open (eg., col 3:44-51 - the row command decoder 33 may activate either one of command output nodes ACT, PRE, PRE-REF responsive to the determined command, ACT, PRE, or PRE-REF. For example, the bank address may be provided by the command/address decoder 32 in a plurality of bits (e.g., four), and the bank address decoder 34 may provide a bank selection signal to one bank among a plurality of banks (e.g., sixteen banks).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the dram stack with active command and precharge commands as disclosed by Lee, with Richter, providing the benefit of schedule a combination of row precharge and refresh operations (see Richter, col 5:1-5) High data reliability, high speed of memory access, and reduced chip size are features that are demanded from semiconductor memory (col 1:6-8).
Claim 17. Lee does not disclose, but Richter discloses
wherein the host device is further configured to: issue a column command directed to the target row of memory cells while the bank is open, wherein the column command is associated with the first activate command (eg., col 1:30-40 - he page is open responsive to the activation command, and a read or write access to the page occurs responsive to a read or write command, or a refresh operation of the row in a bank is performed responsive to the per-bank refresh command.);
issue a precharge command to close the bank, subsequent to issuing the column command, without issuing a column command associated with the second activate command (eg., col 4:67 – col 5:6 - a command set including a “PRECHARGE-REFRESH (PRE-REF)” command. For example, PRE-REF m command instructs a combination of a precharge operation and a refresh operation for bank m. For example, the semiconductor memory device may schedule a combination of row precharge and refresh operations for bank m, responsive to a single, combined PRE-REF command for bank m.)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the dram stack with active command and precharge commands as disclosed by Lee, with Richter, providing the benefit of schedule a combination of row precharge and refresh operations (see Richter, col 5:1-5) High data reliability, high speed of memory access, and reduced chip size are features that are demanded from semiconductor memory (col 1:6-8).
Claims 10, 18, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 22922031) and in view of Richter (US 10141042) and Nale (cited above) and further in view of Kwon (US 20210225418)
Claim 10. Lee in view of Richter and Nale does not disclose, but Kwon discloses
wherein the control circuitry is further configured to: set the mode register bit based on a mode register command from a host device (eg., 0132 - a mode register set command MRS, and a mode register read command MRR. Here, the read command RDA and the write command WRA instruct an auto precharge operation together with a read operation and a write operation. The respective commands may be received; 0040 - the host interface circuit 110 may transmit a specific command (e.g., a precharge command PRE).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the dram stack with active command and precharge commands as disclosed by Lee, with Richter, and Nale with Kwon, providing the benefit of an efficient input and output interface method is required between a host device (e.g., a memory controller) and the memory device (see Kwon, 0003).
Claim 18. Lee in view of Richter and Nale does not disclose, but Kwon discloses
issue a mode register command to the HBM device to set a mode register bit of the HBM device to signal that the address of the target row of memory is to be captured (eg., 0132 - a mode register set command MRS, and a mode register read command MRR. Here, the read command RDA and the write command WRA instruct an auto precharge operation together with a read operation and a write operation. The respective commands may be received; 0040 - the host interface circuit 110 may transmit a specific command (e.g., a precharge command PRE); 0038 - high bandwidth memory (HBM) ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the dram stack with active command and precharge commands as disclosed by Lee, with Richter, and Nale with Kwon, providing the benefit of an efficient input and output interface method is required between a host device (e.g., a memory controller) and the memory device (see Kwon, 0003).
Claim 19. Lee discloses A system (eg., col 10 Fig. 1A - system 101 ), comprising:
a host device configured to (eg., col 2:64 Fig. 1A – host device 103).
interface with a high-bandwidth memory (HBM) device that comprises a stack of dynamic random access memory (DRAM) dies, wherein the DRAM dies comprise respective banks of memory cells (eg., col 4:25-40 - DRAM (e.g., DDR4 DRAM, DDR5 DRAM, LP DRAM, HBM DRAM, etc.), or a portion thereof that includes one or more dies/chips. In some embodiments, the memory 100 can include synchronous DRAM (SDRAM) of DDR type integrated on a single semiconductor chip… DRAM (e.g., DDR4 DRAM, DDR5 DRAM, LP DRAM, HBM DRAM, etc.), or a portion thereof that includes one or more dies/chips. In some embodiments, the memory 100 can include synchronous DRAM (SDRAM) of DDR type integrated on a single semiconductor chip) and wherein the host device is configured to:
issue a precharge command, wherein the precharge command comprises an address of a target row of memory cells of the bank (eg., col 3:40-41 - PRECHARGE (PRE) to close an open row in the bank) and,
Lee does not disclose, but Richter discloses
a DRFM flag field (eg., col 4:49-55 - bank n active flag signal on the s6 node may indicate whether bank n refresh operation is active)
wherein the precharge command comprises one of, a multi-cycle precharge per-bank command, and a single-cycle precharge command in which a pseudo-channel field of a unit interval of the single-cycle precharge command serves as the DRFM flag field (eg., col 3:39-50 - determine whether the row access command is either ACTIVATE (ACT) to open a row in a bank, PRECHARGE (PRE) to close an open row in the bank …combined PRECHARGE-REFRESH (PRE-REF) command to close an open row in the bank followed by a refresh operation on the same bank. For example, the row command decoder 33 may activate either one of command output nodes ACT, PRE, PRE-REF responsive to the determined command, ACT, PRE, or PRE-REF. ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the dram stack with active command and precharge commands as disclosed by Lee, with Richter, providing the benefit of schedule a combination of row precharge and refresh operations (see Richter, col 5:1-5) High data reliability, high speed of memory access, and reduced chip size are features that are demanded from semiconductor memory (col 1:6-8).
Lee in view of Richter does not disclose, but Nale discloses
one of the banks of the memory cells (eg., [0026] directed Refresh management (DRFM) commands are sent to either all banks (DRFMab) or to the same bank in all bank groups (DRFMsb)), 0084 - The DRFM command is expected to be provided after the memory device has an address captured for the multiple banks that will be the subject of the DRFM command. As such, most or all of the banks affected by the DRFM command will have an address to use for row hammer mitigation).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the dram stack with active command and precharge commands as disclosed by Lee, with Richter, with Nale providing the benefit of memory controller can randomize the sending of the DRFM commands. The controller can generate commands to indicate the memory device should capture addresses for various banks to use for pTRR operations (see Nale, 0026) Better use of the bandwidth required to perform row hammer mitigation, increases the possibility to mitigate more types of attacks with less bandwidth loss (0028).
Lee in view of Richter and Nale does not disclose, but Kwon discloses
directed to a bank of the memory cells (eg., [0039] The memory banks of the memory bank array 220 may write or read the data DATA in or from the memory cells in response to the control signal iCTRL.; 0049 - when the precharge command PRE is sensed, the control logic circuit 230 may generate a control signal for precharging at least one memory bank).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the dram stack with active command and precharge commands as disclosed by Lee, with Richter, and Nale with Kwon, providing the benefit of an efficient input and output interface method is required between a host device (e.g., a memory controller) and the memory device (see Kwon, 0003).
Response to Arguments
Applicant's arguments filed 12/1/2025 have been fully considered but they are not persuasive.
For claims 1, 12 and 19, Applicant argues that that the cited references do not disclose the amended limitations. The Office disagrees.
In the present OA, the updated combination of references render the amended limitations as obvious.
Specifically, Lee in view of Richter does not disclose, but Nale discloses
one of the banks of the memory cells (eg., [0026] directed Refresh management (DRFM) commands are sent to either all banks (DRFMab) or to the same bank in all bank groups (DRFMsb)),
based on a condition that the DRFM flag field is set (eg., 0084 - The DRFM command is expected to be provided after the memory device has an address captured for the multiple banks that will be the subject of the DRFM command. As such, most or all of the banks affected by the DRFM command will have an address to use for row hammer mitigation).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the dram stack with active command and precharge commands as disclosed by Lee, with Richter, with Nale providing the benefit of memory controller can randomize the sending of the DRFM commands. The controller can generate commands to indicate the memory device should capture addresses for various banks to use for pTRR operations (see Nale, 0026) Better use of the bandwidth required to perform row hammer mitigation, increases the possibility to mitigate more types of attacks with less bandwidth loss (0028).
Applicant’s arguments for dependent claims 2-11, 13-18 are based on their respective base independent claims 1, 12, which are addressed above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GAUTAM SAIN whose telephone number is (571)270-3555. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared Rutz can be reached at 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/GAUTAM SAIN/Primary Examiner, Art Unit 2135