DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed 6/17/2024 fails to comply with the provisions of 37 CFR 1.97, 1.98 and MPEP § 609 because 37 C.F.R. 1.98(b)(5) states “Each publication listed in an information disclosure statement must be identified by publisher, author (if any), title, relevant pages of the publication, date, and place of publication” (emphasis added). While it is appreciated that all the required features above may not always reasonably be available, when they are, they must be included. Non-patent literature documents 1-5 do not have the requisite information listed on the IDS, and therefore have not been considered.
Furthermore, the non-patent literature document 6 has not been considered. The intent of this document is to draw attention to two related applications, but neither of which have been reasonably identified or provided. The documents listed have been identified using, as best understood, a reference number internal to IBM and not the USPTO. As such the intent of this document is to identify relevant documents, but where the documents are not readily identifiable, neither the document nor any listed information has been considered. If these documents are US applications, then applicant must list the actual US applications individually on the IDS itself should applicant wish these documents considered. If the documents have not actual US applications or are unpublished, then applicant must provide the documents in order for them to be considered.
It has been placed in the application file, but the information struck-through has not been considered as to the merits. Applicant is advised that the date of any re-submission of any item of information contained in this information disclosure statement or the submission of any missing element(s) will be the date of submission for purposes of determining compliance with the requirements based on the time of filing the statement, including all certification requirements for statements under 37 CFR 1.97(e). See MPEP § 609.05(a).
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the test head of Claim 18 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to because it is unclear what features constitute a probe head as recited in Claim 1, for example. See the 112 rejections below regarding this issue. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
As to Claim 1,
The phrase “A semiconductor testing device, comprising: N devices, wherein N is an integer; and N-1 probe heads, wherein: an M-th probe head, of the N-1 probe heads, includes devices 1 to N-M of the N devices, which are electrically connected to each other; the M-th probe head is configured to test an M-th device of the N devices; and M is an integer between 1 and N-1” on lines 1 to the end lacks proper written description.
1) The first issue here is that applicant does not reasonably disclose the manner in which applicant implements a probe head. In one instance, applicant states in paragraph [0063] that the probe heads are element 132, but element 132 are bonded interconnects as seen in Figure 1. A person of ordinary skill in the art would not reasonably recognize interconnects as probe heads, and mere interconnections between devices 110A-N are not reasonably probe heads. Further raising an issue is that paragraph [0064] then states that the probe head includes one or more devices itself, a feature also claimed above. However, a device, especially one that itself is designed to be tested, is not reasonably a probe head. Furthermore, while not expressly claimed, a probe head reasonably requires some form of probe, but where the original disclosure does not reasonably disclose the manner in which any probes are implemented. The Examiner acknowledge the probes 242 shown in Figures 2A-2C, but applicant does not reasonably disclose the manner in which these probes are implemented. For example, applicant does not explain whether these probes all exist at the same time and are merely inserted into the DUT contacts 232. This is stated because Figure 1, which discloses the claimed overall device, does not shown any probes 232. As such, it is unclear where in the final product these probes are located. Furthermore, applicant does not reasonably explain whether the different devices are physically disconnected in the manner shown in Figures 2A-2C, or if this is merely an exaggerated drawing only made to show where the probes are located. The primary issue, in light of the above, is that applicant does not reasonably disclose the manner in which any probe head, includes its probes, are implemented in the combination, and applicant does not reasonably disclose the difference between the probes themselves in contrast with the electrical interconnects found between stacked devices. A person of ordinary skill in the art would not reasonably recognize the manner in which the above probe heads are implemented, as claimed, and would therefore not reasonably recognize that applicant had possession of the above claim features.
2) The next issue here is that applicant does not reasonably disclose the manner in which any device is “configured to test an M-th device of the N devices” as claimed. What applicant discloses, as best understood, is a stack of devices that have electrical components between them. Even to the extent that applicant considers the electrical interconnects between the devices to have or be probes, applicant does not reasonably disclose the manner in which these devices themselves are configured to perform any type of testing. As best understood, the devices themselves are both a device that is intended to be tested, as well as a device intended to be used for testing by making it part of a probe head. However, applicant does not reasonably explain what specific configuration of these devices or probe heads cause them to be configured to test any component, beyond merely being electrically connected to an adjacent device or component. The original disclosure does not reasonably disclose a configuration of the probe heads that cause them to be configured to test any device, especially when one of the devices themselves is considered part of the probe head. Merely being electrically connected to another device does not reasonably mean that the device, or combination of the device an probes, are themselves configured to test any component. For example, what configures a multimeter to test a voltage across a device is not merely the fact that it has electrical probes that can be used to test a voltage. Instead, it is the combination of these electrical probes and a specific program or electrical configuration of components designed to obtain the voltage from the electrical signals from the probes that provide the configuration. However, applicant does not reasonably disclose what about the devices themselves are configured to test, such that they, in combination with an probes, are themselves configured to perform any type of test as claimed. A person of ordinary skill in the art would not reasonably recognize that applicant had possession of the claim feature “the M-th probe head is configured to test an M-th device of the N devices,” and this phrase therefore lacks proper written description.
As to Claims 7, 14, and 15,
The phrases “the handler wafer includes integrated cooling channels configured to spread and remove heat from the semiconductor wafer” on lines 1-2 of Claim 7, the phrase “spreading and removing heat from the semiconductor wafer by the semiconductor testing device via the handler wafer” on line 3-4 of Claim 14, and the phrase “forming integrated cooling channels within a handler wafer; and spreading and removing heat from the semiconductor wafer via the integrated cooling channels” on lines 2-4 of Claim 15 lack proper written description. At issue here is that the original disclosure is completely silent as to the manner in which applicant is implementing any cooling channels as claimed. Applicant neither shows nor explains the manner in which any integrated cooling channels are implemented, and a person of ordinary skill in the art would not reasonably recognize the manner in which such channels are implemented by applicant to demonstrate possession of the claim feature.
As to Claim 9,
The phrase “wherein the semiconductor testing device is configured to test the devices within a temperature range from -55 °C to 150 °C” on lines 1-2 lacks proper written description.
1) Applicant does not reasonably disclose or claim any element or component that can reasonably “test” a device as claimed. None of the devices, as best understood, are themselves configured to test another device or other component. Applicant does not disclose what about the devices causes them to have a configuration, such as by way of a stored program or physical circuit, that is specially designed/configured for the claimed purpose. There is a difference between being able to use a first device and its electrical connections to test another device, as opposed to that first device itself having a configuration for such a purpose. The original disclosure does not reasonably disclose the manner in which any device is configured to test another device, and this feature therefore lacks proper written description.
2) Applicant does not reasonably disclose any specific component of the “semiconductor testing device” that is configured to test the devices. Meaning, the only elements of the claims are the devices themselves. Applicant does not recite any other structural claim features. However, applicant is claiming that the “semiconductor testing device” is configured to test the very devices that form the semiconductor testing device. Such a recitation lacks proper written description, because there is no claim structure part of the test device that is reasonably capable of testing the devices themselves. A person of ordinary skill in the art would not reasonably recognize the manner in which the semiconductor testing device is configured in the claimed manner.
As to Claim 10,
The phrase “the semiconductor testing device is configured to power up at least one of the devices via the probe heads” on lines 1-2 lacks proper written description.
Similar to what was noted above, the only components part of the semiconductor testing device are the devices themselves. Applicant is claiming that the overall testing device is configured to power up the devices distinctly from the devices. However, no structural feature of the claim exists that can reasonably power-up the devices as the devices are the only recited claim features. Furthermore, applicant does not reasonably disclose the manner in which the devices are powered up via any portion of the semiconductor testing device. A person of ordinary skill in the art would not reasonably recognize the manner in which the devices are powered up, either by way of the actual claimed limitations, in the combination, or in light of the disclosure. This phrase therefore lacks proper written description.
As to Claim 11,
The phrase “A method of fabricating a semiconductor testing device, the method comprising: forming N devices under test coupled to each other, wherein N is an integer; forming N-1 probe heads, wherein: an M-th probe head is formed by electrically connecting a device 1 to a device N-M of the N devices under test to each other; and M is an integer between 1 and N-1, and testing an M-th device of the N devices under test by the M-th probe head” on lines 1 to the end lacks proper written description.
1) The first issue here is that applicant does not reasonably disclose the manner in which applicant implements a probe head. In one instance, applicant states in paragraph [0063] that the probe heads are element 132, but element 132 are bonded interconnects as seen in Figure 1. A person of ordinary skill in the art would not reasonably recognize interconnects as probe heads, and mere interconnections between devices 110A-N are not reasonably probe heads. Further raising an issue is that paragraph [0064] then states that the probe head includes one or more devices itself, a feature also claimed above. However, a device, especially one that itself is designed to be tested, is not reasonably a probe head. Furthermore, while not expressly claimed, a probe head reasonably requires some form of probe, but where the original disclosure does not reasonably disclose the manner in which any probes are implemented. The Examiner acknowledge the probes 242 shown in Figures 2A-2C, but applicant does not reasonably disclose the manner in which these probes are implemented. For example, applicant does not explain whether these probes all exist at the same time and are merely inserted into the DUT contacts 232. This is stated because Figure 1, which discloses the claimed overall device, does not shown any probes 232. As such, it is unclear where in the final product these probes are located. Furthermore, applicant does not reasonably explain whether the different devices are physically disconnected in the manner shown in Figures 2A-2C, or if this is merely an exaggerated drawing only made to show where the probes are located. The primary issue, in light of the above, is that applicant does not reasonably disclose the manner in which any probe head, includes its probes, are implemented in the combination, and applicant does not reasonably disclose the difference between the probes themselves in contrast with the electrical interconnects found between stacked devices. A person of ordinary skill in the art would not reasonably recognize the manner in which the above probe heads are implemented, as claimed, and would therefore not reasonably recognize that applicant had possession of the above claim features.
2) The next issue here is that applicant does not reasonably disclose the manner in which applicant implements “testing an M-th device of the N devices under test by the M-th probe head” as claimed. What applicant discloses, as best understood, is a stack of devices that have electrical components between them. Even to the extent that applicant considers the electrical interconnects between the devices to have or be probes, applicant does not reasonably disclose the manner in which these devices themselves are configured to perform any type of testing, and similarly, the manner in which any testing of the devices is implemented. As best understood, the devices themselves are both a device that is intended to be tested, as well as a device intended to be used for testing by making it part of a probe head. However, applicant does not reasonably explain what specific configuration of these devices or probe heads cause them to be configured to test any component, beyond merely being electrically connected to an adjacent device or component. The original disclosure does not reasonably disclose a configuration of the probe heads that cause them to be configured to test any device, especially when one of the devices themselves is considered part of the probe head. Merely being electrically connected to another device does not reasonably mean that the device, or combination of the device an probes, are themselves configured to test any component. For example, what configures a multimeter to test a voltage across a device is not merely the fact that it has electrical probes that can be used to test a voltage. Instead, it is the combination of these electrical probes and a specific program or electrical configuration of components designed to obtain the voltage from the electrical signals from the probes that provide the configuration. However, applicant does not reasonably disclose what about the devices themselves are configured to test, such that they, in combination with an probes, are themselves configured to perform any type of test as claimed. A person of ordinary skill in the art would not reasonably recognize that applicant had possession of the claim feature “testing an M-th device of the N devices under test by the M-th probe head” because such a person would not reasonably recognize the manner in which any test is actually implemented using the probe head / device(s) as claimed, and this phrase therefore lacks proper written description.
3) The third issue is that applicant is essentially claiming that a probe head is formed by way of an electrical connection, but where applicant does not reasonably explain the manner in which such a feature is implemented. Applicant does not reasonably disclose or explain what makes the decision to change what the probe head is considered to be or the manner in which such a decision is implemented. Applicant further does not reasonably explain what steps or features are implemented upon making such a decision. No device that is reasonably capable of implementing the above claim feature is disclosed or claimed, and no reasonable explanation of what this device would do to implement the claim features or any other reasonable explanation of the manner in which the claim features are being implemented are disclosed. A person of ordinary skill in the art would not reasonably recognize the manner in which this claim feature is being implemented in order to demonstrate possession of the claim feature, and the claim feature therefore lacks proper written description.
As to Claim 12,
The phrase “upon testing the M-th device under test by the M-th probe head, forming an M+1 probe head by electrically connecting the device 1 to a device N-M+1 of the N devices under test; and testing an M+1-th device of the N devices under test by the M+1 probe head” on lines 2 to the end lacks proper written description.
1) First, this phrase lacks proper written description for the same issues noted in the above rejection of Claim 11, where are herein incorporated as asserted against this claim. A person of ordinary skill in the art would not reasonably recognize the manner that applicant is performing any testing or forming a probe head as explained in the rejection of Claim 11, and such a person would not reasonably recognize that applicant had possession of the claim features.
2) The second issue is that applicant is essentially claiming that a new probe head is formed by way of a new electrical connection, but where applicant does not reasonably explain the manner in which such a feature is implemented. Applicant does not reasonably disclose or explain what makes the decision to change what the probe head is considered to be or the manner in which such a decision is implemented. Applicant further does not reasonably explain what steps or features are implemented upon making such a decision. No device that is reasonably capable of implementing the above claim feature is disclosed or claimed, and no reasonable explanation of what this device would do to implement the claim features or any other reasonable explanation of the manner in which the claim features are being implemented are disclosed. A person of ordinary skill in the art would not reasonably recognize the manner in which this claim feature is being implemented in order to demonstrate possession of the claim feature, and the claim feature therefore lacks proper written description.
As to Claim 17,
The phrase “powering up at least one of the N devices under test by the probe heads” on lines 1-2 lacks proper written description.
Similar to what was noted above, the only components part of the semiconductor testing device are the devices themselves. Applicant is claiming that the devices are powered up, but applicant does not reasonably disclose the manner in which the devices are powered up, what decides to power them up, or any aspect as to the manner in which they are powered up. A person of ordinary skill in the art would not reasonably recognize the manner in which the devices are powered up, either by way of the actual claimed limitations, in the combination, or in light of the disclosure. This phrase therefore lacks proper written description.
As to Claim 18,
The phrase “A semiconductor testing device, comprising: a test head comprising; one or more electrical connections; and one or more testing probes; a device under test; and a handler wafer connected to the device under test, wherein the semiconductor testing device is configured to power up the device under test during testing” on lines 1 to the end lacks proper written description.
1) The first issue is that applicant does not reasonably disclose a test head or the manner in which it is implemented. While a “test head” is mentioned in the disclosure, no test head is ever identified in the figures or any other part of the disclosure. A “probe head” is identified, but applicant never states that the test head is the probe head. As such, this phrase lacks proper written description because applicant does not reasonably disclose the manner in which any test head is implemented.
2) To the extent that the test head is intended to be the probe head of the disclosure, applicant does not reasonably disclose the manner in which applicant implements a probe head. In one instance, applicant states in paragraph [0063] that the probe heads are element 132, but element 132 are bonded interconnects as seen in Figure 1. A person of ordinary skill in the art would not reasonably recognize interconnects as probe heads, and mere interconnections between devices 110A-N are not reasonably probe heads. Further raising an issue is that paragraph [0064] then states that the probe head includes one or more devices itself, a feature also claimed above. However, a device, especially one that itself is designed to be tested, is not reasonably a probe head. Furthermore, while not expressly claimed, a probe head reasonably requires some form of probe, but where the original disclosure does not reasonably disclose the manner in which any probes are implemented. The Examiner acknowledge the probes 242 shown in Figures 2A-2C, but applicant does not reasonably disclose the manner in which these probes are implemented. For example, applicant does not explain whether these probes all exist at the same time and are merely inserted into the DUT contacts 232. This is stated because Figure 1, which discloses the claimed overall device, does not shown any probes 232. As such, it is unclear where in the final product these probes are located. Furthermore, applicant does not reasonably explain whether the different devices are physically disconnected in the manner shown in Figures 2A-2C, or if this is merely an exaggerated drawing only made to show where the probes are located. The primary issue, in light of the above, is that applicant does not reasonably disclose the manner in which any probe head, includes its probes, are implemented in the combination, and applicant does not reasonably disclose the difference between the probes themselves in contrast with the electrical interconnects found between stacked devices. A person of ordinary skill in the art would not reasonably recognize the manner in which the above probe heads are implemented, as claimed, and would therefore not reasonably recognize that applicant had possession of the above claim features.
3) The next issue is that applicant is claiming “a test head comprising; one or more electrical connections; and one or more testing probes,” but where applicant does not reasonably disclose the manner in which the electrical connections and probes are distinctly implemented, nor disclosure what the distinction is between the probes and electrical connections. As explained above, the probe head is identified as element 132, but this element is the electrical connections themselves (the interconnects). As best understood, the electrical connections are the probes, but where applicant is distinctly reciting these features. Applicant shows probes and DUT test contacts in Figures 2A-2C, but as explained above, the manner in which applicant implements such a feature is not reasonably explained, because as best understood, the actual device is what is shown in Figure 1, and where no probes are shown or explained in this figure. As such, the manner in which any probes that are distinct from the electrical connections are implemented is not reasonably disclosed, and a person of ordinary skill in the art would not reasonably recognize the manner in which applicant implements the claim feature.
4) The next issue here is that applicant does not reasonably disclose the manner in which any device is powered up. Similar to what was noted above, the only disclosed and claimed components that are part of the semiconductor testing device are the devices themselves (i.e. the test head and device under test). Applicant is claiming that the overall testing device is configured to power up the device under test, but no structural feature of the claim exists that can reasonably power-up the devices as the devices are the only recited claim features. Furthermore, applicant does not reasonably disclose the manner in which any device under test is powered up via any portion of the semiconductor testing device. A person of ordinary skill in the art would not reasonably recognize the manner in which the devices are powered up, either by way of the actual claimed limitations, in the combination, or in light of the disclosure. This phrase therefore lacks proper written description.
As to Claim 19,
The phrase “the test head further comprises heating and cooling channels, and wherein the test head is configured to heat up and cool down the test head from -55 °C to 150 °C” on lines 1-3 lacks proper written description.
1) Applicant does not reasonably disclose the manner in which the test head itself comprises heating and cooling channels. While such a feature is stated in the disclosure, applicant never identifies nor discloses the manner in which such a feature is implemented. Applicant does not disclose any aspect of the test head itself that comprises such channels, the manner in which these channels are implemented, or provide any reasonable detail regarding such features such that a person of ordinary skill in the art would recognize the manner in which these features are implemented. A person of ordinary skill in the art would not reasonably recognize the manner in which applicant implemented a test head having heating and cooling channels in order to establish possession of the claim feature.
2) Applicant does not reasonably disclose the manner in which the test head itself is configured to heat up or cool itself down. Applicant is claiming that the test head can heat or cool the test head, which means that applicant is claiming that the test head can heat or cool itself. However, applicant does not reasonably disclose any mechanism within any device that can reasonably perform this feature, or the manner in which such a feature is controlled or configured to perform heating or cooling. The original disclosure is completely silent as to the manner in which such feature is implemented. A person of ordinary skill in the art would not reasonably recognize the manner in which applicant implemented a test head that can heat or cool itself in order to establish possession of the claim feature.
As to Claims 2-10, 12-17, 19, and 20,
These claims stand rejected for incorporating and reciting the above rejected subject matter of their respective parent claim(s) and therefore stand rejected for the same reasons.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As to Claim 1,
The phrase “A semiconductor testing device, comprising: N devices, wherein N is an integer; and N-1 probe heads, wherein: an M-th probe head, of the N-1 probe heads, includes devices 1 to N-M of the N devices, which are electrically connected to each other; the M-th probe head is configured to test an M-th device of the N devices; and M is an integer between 1 and N-1” on lines 1 to the end is indefinite.
1) The first issue here is that applicant does not reasonably disclose the manner in which applicant implements a probe head, and it is unclear what a probe head is in light of the disclosure. In one instance, applicant states in paragraph [0063] that the probe heads are element 132, but element 132 are bonded interconnects as seen in Figure 1. A person of ordinary skill in the art would not reasonably recognize interconnects as probe heads, and mere interconnections between devices 110A-N are not reasonably probe heads. Further raising an issue is that paragraph [0064] then states that the probe head includes one or more devices itself, a feature also claimed above. However, a device, especially one that itself is designed to be tested, is not reasonably a probe head. Furthermore, while not expressly claimed, a probe head reasonably requires some form of probe, but where the original disclosure does not reasonably disclose the manner in which any probes are implemented. The Examiner acknowledge the probes 242 shown in Figures 2A-2C, but applicant does not reasonably disclose the manner in which these probes are implemented. For example, applicant does not explain whether these probes all exist at the same time and are merely inserted into the DUT contacts 232. This is stated because Figure 1, which discloses the claimed overall device, does not shown any probes 232. As such, it is unclear where in the final product these probes are located. Furthermore, applicant does not reasonably explain whether the different devices are physically disconnected in the manner shown in Figures 2A-2C, or if this is merely an exaggerated drawing only made to show where the probes are located. The primary issue, in light of the above, is that applicant does not reasonably disclose the manner in which any probe head, includes its probes, are implemented in the combination, and applicant does not reasonably disclose the difference between the probes themselves in contrast with the electrical interconnects found between stacked devices. As evidence, the Examiner notes US 2009/0201038 to Knickerbocker which explains that the probe head (2), which is the test head itself, is what holds the probes (4b) used for testing (see Figure 1B, Paragraphs [0039],[0040],[0062]). A person of ordinary skill in the art would therefore not reasonably understand the what applicant is considering a probe or probe head to be, and would not reasonably understand the metes and bounds for the full scope of what a probe head or probe to be in light of the disclosure. For the purpose of compact prosecution, as applicant is indicating that the interconnects between devices can be considered to be probe heads and claims/disclosure that the devices under test can be considered part of the probe heads, the Examiner is interpreting that the combination of any device and the interconnects for that device can be considered a probe head, with the interconnects themselves reasonably considered to be probes, in light of the disclosure.
2) The second issue is whether a device is part of a probe head or a device under test. In one instance, a device can be, as best understood, part of a probe head, but in another, it is not, making it unclear how to treat each device in light of the disclosure. While the Examiner acknowledges that applicant my intend in one instance to have one of the devices used as or part of the probe head, from a final product perspective, a device either is or is part of a probe head, or not, making it unclear how the probe head and devices should be interpreted.
3) The next issue here is that applicant does not reasonably disclose the manner in which any device is “configured to test an M-th device of the N devices” as claimed. What applicant discloses, as best understood, is a stack of devices that have electrical components between them. Even to the extent that applicant considers the electrical interconnects between the devices to have or be probes, applicant does not reasonably disclose the manner in which these devices themselves are configured to perform any type of testing. As best understood, the devices themselves are both a device that is intended to be tested, as well as a device intended to be used for testing by making it part of a probe head. However, applicant does not reasonably explain what specific configuration of these devices or probe heads cause them to be configured to test any component, beyond merely being electrically connected to an adjacent device or component. The original disclosure does not reasonably disclose a configuration of the probe heads that cause them to be configured to test any device, especially when one of the devices themselves is considered part of the probe head. Merely being electrically connected to another device does not reasonably mean that the device, or combination of the device an probes, are themselves configured to test any component. For example, what configures a multimeter to test a voltage across a device is not merely the fact that it has electrical probes that can be used to test a voltage. Instead, it is the combination of these electrical probes and a specific program or electrical configuration of components designed to obtain the voltage from the electrical signals from the probes that provide the configuration. However, applicant does not reasonably disclose what about the devices themselves are configured to test, such that they, in combination with an probes, are themselves configured to perform any type of test as claimed. As such, in light of the disclosure, a person of ordinary skill in the art would not reasonably what applicant means by claiming “the M-th probe head is configured to test an M-th device of the N devices” beyond merely being electrically connected to an adjacent device. For the purpose of compact prosecution, the Examiner is interpreting that a device that is electrically connected to another device is reasonably configured to test that device, in light of the disclosure.
As to Claims 7, 14, and 15,
The phrases “the handler wafer includes integrated cooling channels configured to spread and remove heat from the semiconductor wafer” on lines 1-2 of Claim 7, the phrase “spreading and removing heat from the semiconductor wafer by the semiconductor testing device via the handler wafer” on line 3-4 of Claim 14, and the phrase “forming integrated cooling channels within a handler wafer; and spreading and removing heat from the semiconductor wafer via the integrated cooling channels” on lines 2-4 of Claim 15 are indefinite At issue here is that the original disclosure is completely silent as to the manner in which applicant is implementing any cooling channels as claimed. Applicant neither shows nor explains the manner in which any integrated cooling channels are implemented, and a person of ordinary skill in the art would not reasonably recognize the manner in which such channels are implemented by applicant to demonstrate possession of the claim feature. To that extent, a person of ordinary skill in the art would not reasonably understand whether such channels are physical grooves within the handler, or merely sections of the handler designed in some manner to spread or remove heat. It is therefore unclear, in light of the disclosure, what an integrated cooling channel is considered to be.
As to Claim 9,
The phrase “wherein the semiconductor testing device is configured to test the devices within a temperature range from -55 °C to 150 °C” on lines 1-2 is indefinite.
1) Applicant does not reasonably disclose or claim any element or component that can reasonably “test” a device as claimed. None of the devices, as best understood, are themselves configured to test another device or other component. Furthermore, the only elements of the claims are the devices themselves. Applicant does not recite any other structural claim features. However, applicant is claiming that the “semiconductor testing device” is configured to test the very devices that form the semiconductor testing device. Such a recitation is therefore indefinite because it is unclear what structural feature of the semiconductor testing device is itself “configured” to perform any type of testing.
2) Claim 1 already recites that a probe head is configured to test a device, but where this testing is distinctly recited from the testing of Claim 9. The difference and relationship between these two distinct test recitations is unclear, as it is unclear if they are intended to refer to the same or different testing.
As to Claim 10,
The phrase “the semiconductor testing device is configured to power up at least one of the devices via the probe heads” on lines 1-2 is indefinite.
Similar to what was noted above, the only components part of the semiconductor testing device are the devices themselves. Applicant is claiming that the overall testing device is configured to power up the devices distinctly from the devices. However, no structural feature of the claim exists that can reasonably power-up the devices as the devices are the only recited claim features. Furthermore, applicant does not reasonably disclose the manner in which the devices are powered up via any portion of the semiconductor testing device. It is therefore unclear what structural feature of the claim is configured to perform the power-up as claimed. For the purpose of compact prosecution, the Examiner is interpreting this phrase to mean that the devices are configured such that they can be powered-up, but that there is no required structural feature of the claim that is actually configured to perform such a function.
As to Claim 11,
The phrase “A method of fabricating a semiconductor testing device, the method comprising: forming N devices under test coupled to each other, wherein N is an integer; forming N-1 probe heads, wherein: an M-th probe head is formed by electrically connecting a device 1 to a device N-M of the N devices under test to each other; and M is an integer between 1 and N-1, and testing an M-th device of the N devices under test by the M-th probe head” on lines 1 to the end is indefinite.
1) Applicant’s claim is directed to two different types of methods, and is therefore indefinite because it is unclear which type of method this claim is directed towards. In one instance, the claim is directed towards a method of manufacture, which is expressly recited in the preamble where applicant claims a method of fabricating. However, applicant then claims that the devices are “under test” and “testing an M-th device of the N devices under test by the M-th probe head,” but where testing is not a method of fabricating and is instead a method of using. While testing may be part of the overall method of fabricating, it is indefinite to recite both as part of the same claim and to recite both in the same positive manner, because it renders it is unclear whether this claim is directed towards a method a manufacture or a method of using, similar to the IPXL case recited in MPEP 2173.05(p)(II). As such, it is unclear whether this claim should be treated as a method of manufacture or method of using, and is unclear how the claim limitations should therefore be treated.
2) The phrases “forming N devices under test coupled to each other” and “an M-th probe head is formed by electrically connecting a device 1 to a device N-M of the N devices under test to each other” are indefinite. 1) These phrases are indefinite because Claim 11 is an apparatus claim, but reciting “under test” is not clearly a method step of testing. This is further evidenced by the fact that applicant later positively recites a method step of testing. As such, it is unclear how the phrase “under test” should be interpreted, as it is unclear if the testing occurs while the device is being manufactured, and it is unclear if any testing is required during the forming. 2) These phrases are also indefinite because applicant first recites that the devices are “under test,” but then the recites “testing an M-th device,” making it unclear whether applicant is performing two distinct steps of testing, and making it unclear what the relationship is between the step with the devices under test and the later positively recited step of testing. For the purpose of compact prosecution, the Examiner is interpreting that only one step of testing is being implemented, and that the devices need to be formed and connected as claimed, but not while testing is occurring.
3) The phrase “an M-th probe head is formed by electrically connecting a device 1 to a device N-M of the N devices under test to each other; and M is an integer between 1 and N-1, and testing an M-th device of the N devices under test by the M-th probe head” is indefinite, because applicant first recites that the devices are “under test,” but then the recites “testing an M-th device,” making it unclear whether applicant is performing two distinct steps of testing, and making it unclear what the relationship is between the step with the devices under test and the later positively recited step of testing. For the purpose of compact prosecution, the Examiner is interpreting that only one step of testing is being implemented.
4) At issue here is that, as best understood, all devices are always electrically connected as seen in Figure 1. While applicant may intend to use specific electrical connections at different times, applicant is not, as best understood, disconnecting any electrical connections as seen in Figure 1. As such, it is unclear what applicant means by reciting that the probe head is formed by electrically connecting the device as claimed, as this device would already be electrically connected to the N-M device.
As to Claim 12,
The phrase “upon testing the M-th device under test by the M-th probe head, forming an M+1 probe head by electrically connecting the device 1 to a device N-M+1 of the N devices under test; and testing an M+1-th device of the N devices under test by the M+1 probe head” on lines 2 to the end is indefinite.
1) At issue here is that, as best understood, all devices are always electrically connected as seen in Figure 1. While applicant may intend to use specific electrical connections at different times, applicant is not, as best understood, disconnecting any electrical connections as seen in Figure 1. As such, it is unclear what applicant means by reciting that the probe head is formed by electrically connecting the device as claimed, as this device would already be electrically connected to the N-M+1 device.
2) Applicant’s claim is directed to two different types of methods, and is therefore indefinite because it is unclear which type of method this claim is directed towards. In one instance, the claim is directed towards a method of manufacture, which is expressly recited in the preamble where applicant claims a method of fabricating. However, applicant then claims that the devices are “under test” and “testing an M+1-th device of the N devices under test by the M+1 probe head” but where testing is not a method of fabricating and is instead a method of using. While testing may be part of the overall method of fabricating, it is indefinite to recite both as part of the same claim and to recite both in the same positive manner, because it renders it is unclear whether this claim is directed towards a method a manufacture or a method of using, similar to the IPXL case recited in MPEP 2173.05(p)(II). As such, it is unclear whether this claim should be treated as a method of manufacture or method of using, and is unclear how the claim limitations should therefore be treated.
As to Claim 16,
The phrase “forming through-silicon via (TSV)” on line 2 is indefinite. At issue here is that the TSV is claimed be formed distinctly from any previously disclosed component. A via cannot exist unless it is formed in something, but where the above phrase does not reasonably disclose any component, claimed or otherwise, that the TSV is formed in. Furthermore, to the extent that the TSV is intended to be formed in one of the claimed structures, such as the handler, this phrase is distinctly recited from any of the claimed structures, rendering its relationship to any claimed structural unclear. It is therefore unclear what component has the claimed TSV, and the relationship between this TSV and any previously claimed structure is unclear.
As to Claim 18,
The phrase “A semiconductor testing device, comprising: a test head comprising; one or more electrical connections; and one or more testing probes; a device under test; and a handler wafer connected to the device under test, wherein the semiconductor testing device is configured to power up the device under test during testing” on lines 1 to the end is indefinite.
1) The first issue here is that applicant does not reasonably disclose the manner in which applicant implements a test head, and it is unclear what a test head is in light of the disclosure. The original disclosure does not reasonably identify any test head or the manner in which it is implemented to reasonably identify what applicant means by a test head. To the extent that applicant intends a test head to be the probe head of the disclosure, such a feature is still indefinite. In one instance, applicant states in paragraph [0063] that the probe heads are element 132, but element 132 are bonded interconnects as seen in Figure 1. A person of ordinary skill in the art would not reasonably recognize interconnects as probe heads, and mere interconnections between devices 110A-N are not reasonably probe heads. Further raising an issue is that paragraph [0064] then states that the probe head includes one or more devices itself, a feature also claimed above. However, a device, especially one that itself is designed to be tested, is not reasonably a probe head. Furthermore, while not expressly claimed, a probe head reasonably requires some form of probe, but where the original disclosure does not reasonably disclose the manner in which any probes are implemented. The Examiner acknowledge the probes 242 shown in Figures 2A-2C, but applicant does not reasonably disclose the manner in which these probes are implemented. For example, applicant does not explain whether these probes all exist at the same time and are merely inserted into the DUT contacts 232. This is stated because Figure 1, which discloses the claimed overall device, does not shown any probes 232. As such, it is unclear where in the final product these probes are located. Furthermore, applicant does not reasonably explain whether the different devices are physically disconnected in the manner shown in Figures 2A-2C, or if this is merely an exaggerated drawing only made to show where the probes are located. The primary issue, in light of the above, is that applicant does not reasonably disclose the manner in which any probe head, includes its probes, are implemented in the combination, and applicant does not reasonably disclose the difference between the probes themselves in contrast with the electrical interconnects found between stacked devices. As evidence, the Examiner notes US 2009/0201038 to Knickerbocker which explains that the probe head (2), which is the test head itself, is what holds the probes (4b) used for testing (see Figure 1B, Paragraphs [0039],[0040],[0062]). A person of ordinary skill in the art would therefore not reasonably understand the what applicant is considering a probe or probe head to be, and would not reasonably understand the metes and bounds for the full scope of what a probe head or probe to be in light of the disclosure. For the purpose of compact prosecution, as applicant is indicating that the interconnects between devices can be considered to be probe heads and claims/disclosure that the devices under test can be considered part of the probe heads, the Examiner is interpreting that the combination of any device and the interconnects for that device can be considered a probe head, with the interconnects themselves reasonably considered to be probes, in light of the disclosure, and that a test head is intended to be a probe head.
2) Similar to what was noted above, the only components part of the semiconductor testing device are the devices themselves. Applicant is claiming that the overall testing device is configured to power up the device under test, however, no structural feature of the claim exists that can reasonably power-up the device under test as the test head and device under test are the only recited claim features, and neither are disclosed for this purpose. Furthermore, applicant does not reasonably disclose the manner in which the devices are powered up via any portion of the semiconductor testing device. It is therefore unclear what structural feature of the claim is configured to perform the power-up as claimed. For the purpose of compact prosecution, the Examiner is interpreting this phrase to mean that the devices are configured such that they can be powered-up, but that there is no required structural feature of the claim that is actually configured to perform such a function.
As to Claim 19,
The phrase “the test head further comprises heating and cooling channels, and wherein the test head is configured to heat up and cool down the test head from -55 °C to 150 °C” on lines 1-3 is indefinite.
1) First, it is unclear, in light of the disclosure, what applicant means by claiming that the test head comprises heating and cooling channels. No test head is readably identified in the disclosure, and no test head with the claimed channels is disclosed. To the extent that applicant is referring to the probe head, no probe head is disclosed to comprise heating and cooling channels. As such, it is unclear how such a feature should be interpreted in light of the disclosure. For the purpose of compact prosecution, the Examiner is interpreting that any device that has TSVs includes the claim feature.
2) Second, it is unclear, in light of the disclosure, how applicant’s test head (or presumed probe head) is configured to heat or cool itself in the claimed temperature range. Applicant does not originally disclose any head having a heating or cooling ability, and thus it is unclear how such a feature should be interpreted in light of the disclosure. For the purpose of compact prosecution, the Examiner is interpreting that any device that has TSVs includes the claim feature.
As to Claims 2-10, 12-17, 19, and 20,
These claims stand rejected for incorporating and reciting the above rejected subject matter of their respective parent claim(s) and therefore stand rejected for the same reasons.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Knickerbocker (US 2011/0042820 A1).
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As to Claim 1,
Knickerbocker discloses A semiconductor testing device, comprising: N devices (note the above three devices), wherein N is an integer (note N can be 3 as seen in Figures 5a,c) (see above figure); and N-1 probe heads (see above figure / note that a probe head is defined, in light of the disclosure, to be a combination of a device and one of the two sets of probes, and thus there are 3 devices and 2 probe heads), wherein: an M-th probe head, of the N-1 probe heads, includes devices 1 to N-M of the N devices, which are electrically connected to each other (see above figure / note that the devices and probes can be selected in the same manner as disclosed by applicant, such as if the bottom device is to be tested, then the top two devices and the top two sets of probes form the Mth probe head, ); the M-th probe head is configured to test an M-th device of the N devices (see above figure / note probe head can reasonably test the remaining device because it is electrically connected to it); and M is an integer between 1 and N-1 (see above figure), (Figures 5a-c), (Paragraphs [0048],[0074] / note that while a marked-up Figure 5a is shown above, all of Figures 5a-c are asserted to disclose the claim features as all disclose a similar chip stack).
(Note: What Knickerbocker discloses is substantially similar to applicant, in that like applicant, multiple devices as part of a chip stack are electrically connected to each other by electrical interconnects. While applicant may intend the interconnects of the instant application to be used for a testing purpose, structurally, the device of Knickerbocker is substantially similar to that of applicant, and thus would be reasonably capable of the same type of use. That stated, the structure of Knickerbocker, being substantially similar to that of applicant, reasonably discloses the features of the claims.)
As to Claim 2,
Knickerbocker discloses the N devices are chiplets or die (Figure 5a / note the stack of chips, which is a stack of dies).
As to Claim 3,
Knickerbocker discloses the N devices are coupled to each other (Figure 5a).
As to Claim 4,
Knickerbocker discloses wherein: at least one of the devices is a semiconductor wafer; and the semiconductor wafer is one of: a functional wafer, a full thickness wafer, or a thinned wafer (Paragraph [0027] / note the dies can be thin wafer dies).
As to Claim 5,
Knickerbocker discloses wherein: the semiconductor wafer is coupled to a handler wafer (Paragraphs [0028],[0032]); and the semiconductor testing device is further configured to spread and remove heat from the semiconductor wafer via the handler wafer (Figures 5b,c / note heat spreader or cooling plate), (Paragraphs [0074],[0075]).
As to Claim 6,
Knickerbocker discloses wherein the handler wafer is one of: a silicon handler wafer, or a thermally conductive handler wafer (Paragraph [0061] / note the handler can be a thick piece of silicon or glass).
As to Claim 7,
Knickerbocker discloses wherein the handler wafer includes integrated cooling channels configured to spread and remove heat from the semiconductor wafer (Paragraphs [0018], [0054] / note that glass is considered to include cooling channels as it naturally dissipates heat, and note the TSVs).
As to Claim 8,
Knickerbocker discloses wherein the handler wafer includes through-silicon via (TSV) configured to spread and remove heat from the semiconductor wafer (Paragraph [0018], [0027], (Figure 3 / note the handler is interpreted to include the TSV).
As to Claim 9,
Knickerbocker discloses wherein the semiconductor testing device is configured to test the devices within a temperature range from -55 °C to 150 °C (note this is a property of the system as the device is substantially similar to that of applicants, and thus must reasonably include such a feature (Figures 5-a).
As to Claim 10,
Knickerbocker discloses wherein the semiconductor testing device is configured to power up at least one of the devices via the probe heads (Paragraph [0074] / note the chips can be powered-up).
As to Claim 11,
Knickerbocker discloses A method of fabricating a semiconductor testing device, the method comprising: forming N devices (note the above three devices), under test coupled to each other (Figures 5a-c), wherein N is an integer (see above figure / note N can be three for example in Figures 5a,c); forming N-1 probe heads (see above figure / note that a probe head is defined, in light of the disclosure, to be a combination of a device and one of the two sets of probes, and thus there are 3 devices and 2 probe heads), wherein: an M-th probe head is formed by electrically connecting a device 1 to a device N-M of the N devices under test to each other (see above figure / note that the devices and probes can be selected in the same manner as disclosed by applicant, such as if the bottom device is to be tested, then the top two devices and the top two sets of probes form the Mth probe head); and M is an integer between 1 and N-1 (see above figure), and testing an M-th device of the N devices under test by the M-th probe head (Paragraphs [0028],[0059] / note that as best understood, having the probe head electrically connected to one of the devices and where those connections of the probe head to the device under test are used for testing, reasonably meets this claim feature when an overall test is performed, which is disclosed in at least the above paragraphs).
(Note: What Knickerbocker discloses is substantially similar to applicant, in that like applicant, multiple devices as part of a chip stack are electrically connected to each other by electrical interconnects. While applicant may intend the interconnects of the instant application to be used for a testing purpose, structurally, the device of Knickerbocker is substantially similar to that of applicant, and thus would be reasonably capable of the same type of use. That stated, the structure of Knickerbocker, being substantially similar to that of applicant, reasonably discloses the features of the claims.)
As to Claim 12,
Knickerbocker discloses upon testing the M-th device under test by the M-th probe head, forming an M+1 probe head by electrically connecting the device 1 to a device N-M+1 of the N devices under test; and testing an M+1-th device of the N devices under test by the M+1 probe head (Paragraphs [0028],[0059] / note that as best understood, having the probe head electrically connected to the devices similar to that disclosed by applicant, and where those connections of the probe head to the device under test are used for testing, reasonably meets this claim feature when an overall test is performed, which is disclosed in at least the above paragraphs).
As to Claim 13,
Knickerbocker discloses wherein: at least one of the N devices under test is a semiconductor wafer; and the semiconductor wafer is one of: a functional wafer, a full thickness wafer, or a thinned wafer (Paragraph [0027] / note the dies can be thin wafer dies).
As to Claim 14,
Knickerbocker disclose connecting the semiconductor wafer to a handler wafer (Paragraphs [0028],[0032]); and spreading and removing heat from the semiconductor wafer by the semiconductor testing device via the handler wafer (Figures 5b,c / note heat spreader or cooling plate), (Paragraphs [0074],[0075]).
As to Claim 15,
Knickerbocker discloses forming integrated cooling channels within a handler wafer; and spreading and removing heat from the semiconductor wafer via the integrated cooling channels (Paragraphs [0018], [0054] / note that glass is considered to include cooling channels as it naturally dissipates heat, and note the TSVs).
As to Claim 16,
Knickerbocker discloses forming through-silicon via (TSV); and spreading and removing heat from the semiconductor wafer via the TSV (Paragraph [0018], [0027], (Figure 3 / note the handler is interpreted to include the TSV).
As to Claim 17,
Knickerbocker powering up at least one of the N devices under test by the probe heads (Paragraph [0074] / note the chips can be powered-up and must be in order for testing by applying some current from a test device).
As to Claim 18,
Knickerbocker discloses A semiconductor testing device, comprising: a test head (any combination devices and probes but where one of the devices is not part of the test head) comprising; one or more electrical connections; and one or more testing probes (Paragraphs [0074],[0075]), (see above figure), (Figures 5a-c); a device under test (one of the devices not part of the test head), (see above figure); and a handler wafer connected to the device under test (Paragraphs [0028],[0065]), wherein the semiconductor testing device is configured to power up the device under test during testing (Paragraph [0074] / note the chips can be powered-up).
As to Claim 19,
Knickerbocker discloses the test head further comprises heating and cooling channels, and wherein the test head is configured to heat up and cool down the test head from -55 °C to 150 °C (Figure 5B / note TSV and note that as best understood and in light of applicant’s disclosure, the TSV will allow for the above claimed temperature range).
As to Claim 20,
Knickerbocker discloses the device under test is one of: a functional wafer, a full thickness wafer, or a thinned wafer (Paragraph [0027] / note the dies can be thin wafer dies).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. 1) US 2013/0015440 to Dang et al. which discloses an integrated circuit test probe, 2) US 2013/0344694 to Audette et al. which discloses a probe on substrate, and 3) US 2015/0192633 to Garibay et al. which discloses a 3D chip testing through micro-c4 interface.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID M. SCHINDLER whose telephone number is (571)272-2112. The examiner can normally be reached 8am-4:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lee Rodak can be reached at 571-270-5628. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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DAVID M. SCHINDLER
Primary Examiner
Art Unit 2858
/DAVID M SCHINDLER/Primary Examiner, Art Unit 2858
Prosecution Insights