DETAILED ACTION
This Office Action is in response to claims filed on 06/18/2024.
Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: "a memory allocation unit" and "a memory return unit" in claim 10.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
A review of the specification finds no explicit support for the structures of the limitations. Examiner notes that for computer-implemented technologies, structural support may be derived from a “computer” + “algorithm”, see MPEP 2181. Examiner does not find support for specific structures nor general computers that are specially programmed by algorithms in the specification corresponding to the limitations above which invoke 35 U.S.C. 112(f). For the purposes of compact prosecution and applying art, Examiner will interpret the limitations as generic computer/processor for performing the instructions for carrying out the claimed functionality.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 10-17 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim limitations “a memory allocation unit” and “a memory return unit” invoke 35 U.S.C. 122(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure material, or acts, to the function. A review of the specification finds no support for the structure of these limitations. Examiner does not fund support for a specific structure nor a general computer that is specially programmed by an algorithm in the specification corresponding to the limitations above which invoke 35 U.S.C. 112(f). See MPEP § 2181(II)(B). For the purpose of compact prosecution and applying art, Examiner will interpret the limitations as a generic computer/processor for performing instructions for carrying out the claimed functionality. See claim interpretation under 35 U.S.C 112(f) above and rejection under 35 U.S.C. 112(b) below. Therefore, are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10-17 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim limitation “a memory allocation unit” and “a memory return unit” invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. A review of the specification finds no support for the structure of these limitations. Examiner does not find support for a specific structure nor a general computer that is specially programmed by an algorithm in the specification corresponding to the limitations above which invoke 35 U.S.C. 112(f). Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
For the purpose of compact prosecution and applying art, Examiner will interpret the limitations
as a generic computer/processor for performing instructions for carrying out the claimed functionality.
See claim interpretation under 35 U.S.C. 112(f) and rejection under 35 U.S.C. 112(a) above.
Claims 11-17 depend upon claim 10, therefore are additionally rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement and under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph, as being indefinite.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 5, 7-11, 13, 14, and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Stabrawa et al. Patent No. US 10,372,335 B2 (hereinafter Stabrawa) in view of van Riel et al. Patent No. US 10,956,216 B2 (hereinafter van Riel).
With regard to claim 1, Stabrawa teaches a method for improving performance of a hypervisor in a memory disaggregation environment (Abstract, Methods and systems for providing a virtualization instance on an apparatus to external primary memory), comprising:
allocating memory pages to a virtual machine in preset units (Col. 1, The host machine may also contain a fixed amount of memory that may be allocated to the virtual machines; Col. 6, The size of the portion of the memory may be related to the size of the expanded region minus the size of the existing region 214 rounded up to the nearest unit of allocation, such as a page, a huge page, a slab, and/or any other unit of allocation.);
…
removing an address space mapping for the page frame to be returned (Col. 46, Causing the portions of the file data to be invalidated and/or reclaimed may be performed upon multiple portions in a batched invalidation and/or reclaim operation. For example, the client logic may unmap one or more page table entries for multiple portions and then flush the affected translation lookaside buffers, such as the translation lookaside buffers for any processors that are using the address space containing the page table entries at the time the page table entries are reclaimed.)
However, Stabrawa does not explicitly teach comparison of page frame address ranges to be utilized in address space removal range threshold.
van Riel teaches comparing an address range of a page frame to be returned with a preset page size (Col. 19, The determination may involve the guest operating system determining an address of the hypervisor memory page containing the guest memory page in view of memory page size of the hypervisor. This may involve identifying a location (e.g., virtual, logical, or physical address) of one or more of the guest memory pages and comparing it to a location (e.g., virtual, logical, or physical address) of one or more hypervisor memory pages.); and
…
depending on a result of comparison with the preset page size (Col. 10, Memory page identifiers 236A may include offset data (numeric or non-numeric values), address data (virtual, logical, or physical addresses), length data, link data (e.g., a pointer or link), other data, or a combination thereof),
wherein removing the address space mapping comprises removing the address space mapping on a basis of contiguous page frames (Col. 8, Indication 119B may be a batched message that is similar to indication 119A and may include multiple memory pages, memory page ranges, or a combination thereof.) when the range of the page frame to be returned is equal to or greater than the preset page size (Col. 11, Guest page set updating module 216 may determine whether to add, modify, or merge elements by analyzing the location of the newly released memory page relative to one or more memory pages already in the set … A memory page may be adjacent to another memory page when there are no other memory pages between them. Guest page set updating module 216 may merge multiple elements of guest set 234 into a single element when module 216 determines that the multiple elements correspond to memory pages that are adjacent to one another. The single element may include multiple adjacent memory pages as a contiguous range of memory pages (Examiner notes: Such that adjacent memory pages are greater than the preset page and are therefore contiguous.).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to apply the teachings of Stabrawa with the teachings of van Riel in order to provide a method that teaches comparison of a page frame against a preset page size in order to perform address space removal of contiguous page frames greater than the preset page size. The motivation for applying Stabrawa teaching with van Riel teaching is to provide a method that allows for a guest operating system to batch memory page release operations in order to achieve the advantage of reducing communication overhead between the guest operating system and the hypervisor (van Riel, Col. 11). van Riel and Stabrawa are analogous art directed towards memory management arrangements. Therefore, it would have been obvious for one of ordinary skill in the art to combine Stabrawa with van Riel to teach the claimed invention in order to provide page size comparison.
With regard to claim 2, Stabrawa and van Riel teach the method of claim 1
Stabrawa further teaches wherein removing the address space mapping comprises removing the address space mapping for each page frame (Col. 46-Col. 47, FIG. 11A illustrates a flow diagram of example logic of the system 100 performing a batch portion unmap 1102. The client logic may begin by selecting (1104) a portion to unmap; Col. 48, If the client logic determines that more portions are to be unmapped, the process may restart by selecting (1104) the next portion to unmap.)
However, Stabrawa does not explicitly teach address space removal on the basis that the range of the page frame to be returned is less than the preset page.
van Riel teaches when the range of the page frame to be returned is less than the preset page size (Col. 8, Indication 119A may be a message transmitted from virtual machine 110A to hypervisor 120 that includes identification data (e.g., identifier) … Indication 119A may be one of a series of indications and each indication in the series may identify an individual memory page or an individual range of memory pages.)
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to apply the teachings of van Riel with the teachings of Stabrawa in order to provide a method that teaches per frame removal for page frames less than the preset page size. The motivation for applying van Riel teaching with Stabrawa teaching is to provide a method that allows for releasing of memory pages in association with a threshold, such that enables a threshold size quantity to release memory at particular size intervals (van Riel, Col. 6). Stabrawa and van Riel are analogous art directed towards memory management arrangements. Therefore, it would have been obvious for one of ordinary skill in the art to combine van Riel with Stabrawa to teach the claimed invention in order to provide per frame removal for pages ranges less than the preset page size.
With regard to claim 4, Stabrawa and van Riel teach the method of claim 2
Stabrawa further teaches wherein allocating the memory pages to the virtual machine comprises allocating physically contiguous memory pages in preset units (Col. 27, For example, the size of the portion of memory may be the size of the expanded region minus the size of the existing region 214 rounded up to the nearest unit of allocation, such as a page, a huge page, a slab, and/or any other unit of allocation. The units of allocation may have predetermined sizes; Col. 35, A slab of memory may include one or more pages. The one or more pages included in the slab may be contiguous in a physical address space and/or in a virtual address space.).
With regard to claim 5, Stabrawa and van Riel teach the method of claim 2
van Riel further teaches wherein comparing the address range with the preset page size includes determining whether the address range of the page frame to be returned corresponds to contiguously allocated pages (Col. 11, The single element may include the multiple adjacent memory pages a contiguous range of memory pages and may be newly created element or may be one of the existing elements that has had its range expanded to represent the multiple adjacent memory pages; Col. 12, Indication providing module 226 may notify the hypervisor of the memory pages that have been released by guest operating system … Indication providing module 226 may combine (e.g., batch) the identifiers for each of the released memory pages).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to apply the teachings of van Riel with the teachings of Stabrawa in order to provide a method that teaches contiguous page determination. The motivation for applying van Riel teaching with Stabrawa teaching is to provide a method that allows for the determination of contiguously allocated pages such that enables batch execution of memory page releasing (van Riel, Col. 12). Stabrawa and van Riel are analogous art directed towards memory management arrangements. Therefore, it would have been obvious for one of ordinary skill in the art to combine van Riel with Stabrawa to teach the claimed invention in order to contiguous memory page determination.
With regard to claim 7, Stabrawa and van Riel teach the method of claim 1
Stabrawa further teaches when a memory page in the virtual machine corresponds to a free page, delivering a virtual address of the memory page corresponding to the free page to a virtual machine tool module at a kernel level (Col. 38, The balloon logic implements part of a memory reclamation technique referred to as “virtual memory ballooning”. Virtual machine ballooning is a technique in which the hypervisor may retrieve unused memory form one or more guest virtual machines and share unused memory with one or more other guest virtual machines. The balloon logic may be included in the guest operating system of the virtual machine and may interact with the hypervisor; Col. 38, The balloon logic may include logic which allocates and/or releases memory in order to decrease and/or increase the amount of memory available to the virtual machine. The memory allocated within the balloon logic may be returned to the hypervisor.).
With regard to claim 8, Stabrawa and van Riel teach the method of claim 7
van Riel further teaches wherein delivering the virtual address to the virtual machine tool module at the kernel level includes:
delivering a physical address corresponding to the virtual address to the hypervisor (Col. 14, Indication receiving module 312 may be a portion of hypervisor that receives indications from the virtual machine. The indications may include memory page identification data 332 for identifying one or more hypervisor memory pages or ranges of hypervisor memory pages … Memory page identification data 332 may include an offset value (numeric or non-numeric value), an address (virtual, logical, or physical address), a point, a link, other data, or a combination thereof.); and
marking the physical address with a free page flag (Col. 6, Hypervisor set 334B is another example set and includes one or more memory page identifiers 336B … In one example, hypervisor set 334B may be an array of binary elements and the array may function as a bitmap. Each memory page identifier 336B may correspond to one of the binary elements (e.g., bit, flag, marker) and indicate whether the corresponding hypervisor or guest memory page is in a first state (e.g., released) or in a second state (e.g., unreleased).).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to apply the teachings of van Riel with the teachings of Stabrawa in order to provide a method that teaches hypervisor management of released memory pages. The motivation for applying van Riel teaching with Stabrawa teaching is to provide a method that allows for visibility of released memory pages by the guest operating system such that enables a hypervisor to reuse the released portion without persistent storage overhead (van Riel, Col. 2). Stabrawa and van Riel are analogous art directed towards memory management arrangements. Therefore, it would have been obvious for one of ordinary skill in the art to combine van Riel with Stabrawa to teach the claimed invention in order to provide hypervisor control over released physical address space.
With regard to claim 9, Stabrawa and van Riel teach the method of claim 8,
Stabrawa teaches wherein, when a page fault occurs for a page marked with the free page flag (Col. 39, FIG. 8 illustrates a flow diagram of an example logic of the system 100 handling a page fault 802 for a virtual machine. A page fault 802 may be triggered with the client logic, starting the process. In one example, the processor may trap an operation in the context of the virtual machine which access a guest physical address that maps to an offset of the file which is not contained in the file data.), an initialized page in local memory is used (Col. 40, The client logic may begin by optionally starting (804) an asynchronous read from the file to a portion of memory. The portion of memory may be in file data and/or may be associated it the offset of the file; Col. 41, Upon marking the portion up to date, the client logic may install (814) the portion into the address space of the faulting logic. For example, the client logic may install a page table entry into the virtual address space associated with the virtual machine).
With regard to claim 10, Stabrawa teaches an apparatus for improving performance of a hypervisor in a memory disaggregation environment (Abstract, Methods and systems for providing a virtualization instance on an apparatus access to external primary memory), comprising:
a memory allocation unit for allocating memory pages to a virtual machine in preset units (Col. 35, The data interface may include a memory allocation interface … The memory allocation interface may utilize a memory-mapped interface. For example, allocating the individual buffers and/or allocating the slabs of memory may include mapping all of or a portion of an external memory allocation and/or of one or more regions reference by the external memory allocation in a virtual address space, such as the virtual address space of the application.); and
a memory return unit for comparing an address range of a page frame to be returned with a preset page size and removing an address space mapping for the page frame to be returned (Col. 46, Causing the portions of the file data to be invalidated and/or reclaimed may be performed upon multiple portions in a batched invalidation and/or reclaim operation. For example, the client logic may unmap one or more page table entries for multiple portions and then flush the affected translation lookaside buffers, such as the translation lookaside buffers for any processors that are using the address space containing the page table entries at the time the page table entries are reclaimed.) depending on a result of a comparison with the preset page size,
However, Stabrawa does explicitly teach the memory return unit comparing an address range of a page frame to be returned with a preset page size, performing address space removal depending on a result of a comparison with the preset page size, or removing address space on a basis of contiguous page frames of page frames equal to or greater than the preset page size.
van Riel teaches a memory return unit for comparing an address range of a page frame to be returned with a preset page size (Col. 19, The determination may involve the guest operating system determining an address of the hypervisor memory page containing the guest memory page in view of memory page size of the hypervisor. This may involve identifying a location (e.g., virtual, logical, or physical address) of one or more of the guest memory pages and comparing it to a location (e.g., virtual, logical, or physical address) of one or more hypervisor memory pages.)
wherein the memory return unit removes the address space on a basis of contiguous page frames (Col. 8, Indication 119B may be a batched message that is similar to indication 119A and may include multiple memory pages, memory page ranges, or a combination thereof.) when the range of the page frame to be returned is equal to or greater than the preset page size (Col. 11, Guest page set updating module 216 may determine whether to add, modify, or merge elements by analyzing the location of the newly released memory page relative to one or more memory pages already in the set … A memory page may be adjacent to another memory page when there are no other memory pages between them. Guest page set updating module 216 may merge multiple elements of guest set 234 into a single element when module 216 determines that the multiple elements correspond to memory pages that are adjacent to one another. The single element may include multiple adjacent memory pages as a contiguous range of memory pages (Examiner notes: Such that adjacent memory pages are greater than the preset page and are therefore contiguous.) which is substantially similar to claim 1 and therefore rejected with similar rationale.
Examiner notes: It would be obvious for one of ordinary skill in the art to recognize that the method of claim 1 is being substantially recited again as limitations for the apparatus of claim 10.
With regard to claim 11, it is an apparatus having similar limitations to claim 2. Thus, claim 11 is rejected for the same rationale as applied to claim 2.
With regard to claim 13, it is an apparatus having similar limitations to claim 4. Thus, claim 13 is rejected for the same rationale as applied to claim 4.
With regard to claim 14, it is an apparatus having similar limitations to claim 5. Thus, claim 14 is rejected for the same rationale as applied to claim 5.
With regard to claim 16, it is an apparatus having similar limitations to claim 7. Thus, claim 16 is rejected for the same rationale as applied to claim 7.
With regard to claim 17, it is an apparatus having similar limitations to claim 8. Thus, claim 17 is rejected for the same rationale as applied to claim 8.
With regard to claim 18, Stabarawa teaches a method for improving performance of a hypervisor in a memory disaggregation environment (Abstract, Methods and systems for providing a virtualization instance on an apparatus to external primary memory), comprising:
allocating memory pages to a virtual machine in preset units (Col. 27, For example, the size of the portion of memory may be the size of the expanded region minus the size of the existing region 214 rounded up to the nearest unit of allocation, such as a page, a huge page, a slab, and/or any other unit of allocation. The units of allocation may have predetermined sizes; Col. 35, A slab of memory may include one or more pages. The one or more pages included in the slab may be contiguous in a physical address space and/or in a virtual address space.);
when a memory pages to a virtual machine corresponds to a free page, delivering a virtual address of the memory page corresponding to the free page to a virtual machine tool module at a kernel level (Col. 38, The balloon logic implements part of a memory reclamation technique referred to as “virtual memory ballooning”. Virtual machine ballooning is a technique in which the hypervisor may retrieve unused memory form one or more guest virtual machines and share unused memory with one or more other guest virtual machines. The balloon logic may be included in the guest operating system of the virtual machine and may interact with the hypervisor; Col. 38, The balloon logic may include logic which allocates and/or releases memory in order to decrease and/or increase the amount of memory available to the virtual machine. The memory allocated within the balloon logic may be returned to the hypervisor.); and
However, Stabrawa does not explicitly teach delivering a physical address corresponding to the virtual address to the hypervisor.
van Riel teaches delivering a physical address corresponding to the virtual address to the hypervisor (Col. 14, Indication receiving module 312 may be a portion of hypervisor that receives indications from the virtual machine. The indications may include memory page identification data 332 for identifying one or more hypervisor memory pages or ranges of hypervisor memory pages … Memory page identification data 332 may include an offset value (numeric or non-numeric value), an address (virtual, logical, or physical address), a point, a link, other data, or a combination thereof; Col. 15, Hypervisor page set updating module 316 may update a set of memory pages based on data of indication receiving module 312) which is substantially similar to claim 8 and therefore rejected with similar rationale.
Examiner notes: It would be obvious for one of ordinary skill in the art to recognize that the method of 8 is being substantially recited again as limitations for the method of claim 18.
With regard to claim 19, Stabrawa and van Riel teach the method of claim 18
Stabrawa further teaches marking the physical address with a free page flag (Col. 6, Hypervisor set 334B is another example set and includes one or more memory page identifiers 336B … In one example, hypervisor set 334B may be an array of binary elements and the array may function as a bitmap. Each memory page identifier 336B may correspond to one of the binary elements (e.g., bit, flag, marker) and indicate whether the corresponding hypervisor or guest memory page is in a first state (e.g., released) or in a second state (e.g., unreleased).).
With regard to claim 20, it is an apparatus having similar limitations to claim 9. Thus, claim 20 is rejected for the same rationale as applied to claim 9.
Claims 3, 6, 12, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Stabrawa in view of van Riel as applied to claim 2 and 11 above, and further in view of Subrahmanyam et al. Patent No. US 7,984,264 B2 (hereinafter Subrahmanyam).
With regard to claim 3, Stabrawa and van Riel teaches the method of claim 2
Stabrawa further teaches wherein removing the address space mapping comprises, when the address space mapping is removed for each page frame, removing a mapping of an address space mapped to the page frame (Col. 47, Upon selecting the portion to unmap, the client logic may unmap (1106) page table entries for the portion. Unmapping page tables for the portion may include clearing page table entries, shooting-down one or more entries with one or more translation lookaside buffers (TLB’s), flushing one or more translation lookaside buffers (TLB’s) for processors using the address space, and/or updating data structures associated with the portion.)
However, Stabrawa and van Riel do not explicitly teach an address space mapping removal based on a data structure in a form of a reverse map.
Subrahmanyam teaches based on a data structure in a form of a reverse map (Col. 6, The reverse mapping is used in various ways. For example, reverse mappings may be used to implement Copy On Write for guest physical memory or to swap out guest physical memory. For another example, “invalidating backing store” is the ability to remove or change the machine page that is used by the VMM 300 to back a particular guest physical page in the VM 200. This changes the guest physical page to machine page mapping that the VMM 300 uses. When the guest physical page to machine page mapping is changed, the VMM 300 needs to remove all mappings based on the old guest physical page to machine page mapping.).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to apply the teachings of Subrahmanyam with the teachings of Stabrawa and van Riel in order to provide a method that teaches address space mapping removal based on a reverse map data structure. The motivation for applying Subrahmanyam teaching with Stabrawa and van Riel teaching is to provide a method that allows for storing, tracking, and maintaining writable reverse mappings (Subrahmanyam, Col. 10). Stabrawa and van Riel and Subrahmanyam are analogous art directed towards memory management arrangements. Therefore, it would have been obvious for one of ordinary skill in the art to combine Subrahmanyam with Stabrawa and van Riel to teach the claimed invention in order to provide a reverse map data structure.
With regard to claim 6, Stabrawa, van Riel, and Subrahmanyam teaches the method of claim 3
Stabrawa further teaches wherein removing the address space mapping comprises removing the address space mapping Col. 46, Causing the portions of the file data to be invalidated and/or reclaimed may be performed upon multiple portions in a batched invalidation and/or reclaim operation. For example, the client logic may unmap one or more page table entries for multiple portions and then flush the affected translation lookaside buffers, such as the translation lookaside buffers for any processors that are using the address space containing the page table entries at the time the page table entries are reclaimed.)
However, Stabrawa does not explicitly teach perofmrance of removing the address space occurring when the range of the page frame to be returned is equal to or greater than the preset page size.
van Riel teaches when the range of the page frame to be returned is equal to or greater than the preset page size (Col. 11, Guest page set updating module 216 may determine whether to add, modify, or merge elements by analyzing the location of the newly released memory page relative to one or more memory pages already in the set … A memory page may be adjacent to another memory page when there are no other memory pages between them. Guest page set updating module 216 may merge multiple elements of guest set 234 into a single element when module 216 determines that the multiple elements correspond to memory pages that are adjacent to one another. The single element may include multiple adjacent memory pages as a contiguous range of memory pages (Examiner notes: Such that adjacent memory pages are greater than the preset page and are therefore contiguous.).
Rationale to claim 1 applied here.
However, Stabrawa and van Riel do not explicitly teach address space mapping removal through contiguously allocated head information of the page table entry lists of the reverse map.
Subrahmanyam further teaches wherein removing the address space mapping comprises removing the address space mapping using contiguously allocated head information of page table entry lists of the reverse map (Col. 6, The backmap is shared between all guest physical pages, and typically holds linked lists of fixed sized blocks, one list per guest physical page. Each block stores a fixed number of reverse mappings. Each physical page descriptor has a pointer to the start of the linked list holding its reverse mappings in the backmap.; Col. 6, The reverse mapping is used in various ways … For another example, “invalidating backing store” is the ability to remove or change that machine page that is used by the VM 300 … Removing such old mappings is accomplished by iterating over all of the reverse mappings 394 for the virtual physical page and removing the mappings they point to.)
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to apply the teachings of Subrahmanyam with the teachings of Stabrawa and van Riel in order to provide a method that teachesaddress space mapping removal through allocated head pointers of a reverse map data structure. The motivation for applying Subrahmanyam teaching with Stabrawa and van Riel teaching is to provide a method that allows for combining known prior art elements of removing head pointers of address space mappings with the known methods of determining contiguous memory pages to yield predictable results, with reasonable expectation of success. Stabrawa and van Riel and Subrahmanyam are analogous art directed towards memory management arrangements. Therefore, it would have been obvious for one of ordinary skill in the art to combine Subrahmanyam with Stabrawa and van Riel to teach the claimed invention in order to head pointer address space mapping removal.
With regard to claim 12, it is an apparatus having similar limitations to claim 3. Thus, claim 12 is rejected for the same rationale as applied to claim 3.
With regard to claim 15, it is an apparatus having similar limitations to claim 6. Thus, claim 15 is rejected for the same rationale as applied to claim 6.
Conclusion
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/I.A.C./Examiner, Art Unit 2195
/Aimee Li/Supervisory Patent Examiner, Art Unit 2195
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