DETAILED ACTION
Claims 1-20 are presented for examination.
The present application is being examined the AIA (America Invents Act) First Inventor to File.
This Office Action is Non-Final.
Claims 1, 13 and 17 are independent claims. Claims 2-12, 14-16, 18-20 are dependent claims.
This action is responsive to the following communication: corresponding claims filed on 06-18-2024.
Claims Objections
Claim 20 is objected to because of the following informalities: The use of acronyms without first defining them, for example, ”EC”. An acronym must be first defined before using it as the meaning of the acronym may change with time or depending on the context in which is used.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 20 recites the limitation "EC" . There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 17-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter.
Claim 17 recites “hardware memory”. However, under the broadest reasonable interpretation of a claim drawn to a memory mediums cover non-transitory tangible media and transitory propagating signals per se in view of the ordinary and customary meaning of computer media. The Specification fails to describe the hardware memory in such a way that excludes transitory propagating signals. For that reason, it is reasonable to interpret under the BRI to include all possible mediums, including transitory mediums.
Therefore, since a signal is not one of the four statutory categories “process, machine, manufacture or composition of matter”. Energy is not one of the four categories of invention and therefore this/these claim(s) is/are not statutory .Thus, the claims are non-statutory. See MPEP 2106.01.
To overcome a rejection under 35 U.S.C. 101 a claim drawn to a hardware memory that cover both non-transitory and transitory embodiments may be amended to cover only statutory embodiments by adding the limitation "non-transitory" before “hardware memory". Such an amendment is not considered new matter. See the "Subject Matter Eligibility of Computer Readable Media" memo dated January 26, 2010 (OG Cite: 1351 OG 212; OG Date: 23 Feb 2010).
As per dependent 18-20 claims, these claims do not cure the deficiencies found in each of their respective independent claims, thus are rejected for their dependency on a rejected claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3, 10-11, 13-14, 16-19 are rejected under 35 U.S.C. 102 (a)(1)/(a)(2) as being anticipated by U.S. Patent No. 9,372,731 (hereinafter, “Marr”).
As per claims 1, 13, 17, Marr discloses an Information Handling System (IHS), comprising:
a processor; and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution, cause the IHS to: (inter alia: Claim 1 states “computing system comprising at least one processor and at least one memory in communication with the at least one processor, the at least one memory having stored therein computer instructions, that upon execution by the at least one processor”)
transmit a first request for a processor or memory diagnostic to a Basic Input/Output System (BIOS) protocol driver to transform the request into a second request, (Fig. 4 illustrates a system for generating a request “as part of a test workflow for verifying performance and operation of different firmware configurations” (Col 2 lines 26-26) for a computing resource (i.e. , computer resource is a general-purpose computer that contains a processor and a memory) to a firmware setting framework that may include either a “BIOS” or “abstraction framework” (Col 9 lines 57-65/Col 10 lines 0-24 & Col 5 lines 10-23, respectively) by “translating the requested computing attribute to corresponding hardware-specific firmware settings on the identified computing device”. (col 13 lines 39-46))
wherein the BIOS protocol driver is configured to communicate the second request to the processor or memory; and (the firmware abstraction framework may map requests for computing settings to actual settings that can be implemented in firmware settings. ( Col 4 lines 34-37) Stated differently, the mappings are performed based on “queries”, that determine “predetermined associations between vendor-specific firmware settings and abstracted firmware settings” (abstract & Col 2 line 20) for a plurality of computer devices that may have “a number of specific configurations”. Marr’s teaching is similar to the teaching described by ¶ [0116] of Applicant’s specification that discloses transforming requests that are vendor-specific based on different CPU architectures.
receive a response to the second request. (selecting one of the mappings to provide the requested computing attribute; Col 14 lines 40-43)
As per claims 3, 14, 18, Marr discloses an IHS, wherein the first request comprises an Original Equipment Manufacturer (OEM) Application Programming Interface (API) call, and wherein the second request comprises a processor or memory specific API call. (Col 5 lines 10-23 discloses Marr’s computer system generating “application programming interface (API)” call to provide an interface that is “vendor-specific” and that can be an be translated or “mapped” into a set of abstracted settings that are not vendor specific, for example, “Non-Uniform Memory Access (NUMA), memory speed”. Col 2 lines 12)
As per claims 10, 16 Marr discloses an IHS, wherein the BIOS protocol driver is configured to transform the first request into the second request based, at least in part, upon a policy. (Fig. 4 illustrates a system for generating a request “as part of a test workflow for verifying performance and operation of different firmware configurations” (Col 2 lines 26-26) for a computing resource (i.e. , computer resource is a general-purpose computer that contains a processor and a memory) to a firmware setting framework that may include either a “BIOS” or “abstraction framework” (Col 9 lines 57-65/Col 10 lines 0-24 & Col 5 lines 10-23, respectively) by “translating the requested computing attribute to corresponding hardware-specific firmware settings on the identified computing device”. (col 13 lines 39-46) and policy Col 12 lines 50-67)
As per claim 11, Marr discloses an IHS, wherein the policy comprises one or more rules usable by the BIOS protocol driver to select the second request based, at least in part, upon context information. (col 4 lines 49-53 discloses a firmware abstraction framework that may also be configured to optimize the placement for requested resources “based on various factors such as minimization of disruption to existing services”. )
As per claim 19, Marr discloses an IHS, wherein the processor is part of a heterogenous computing platform selected from the group consisting of: a System-On-Chip (SoC), a Field-Programmable Gate Array (FPGA), and an Application-Specific Integrated Circuit (ASIC). (FPGA, ASICs, standard integrated circuits, col 15 lines 45-67)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 4-9, 15 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent No. 9,372,731 (hereinafter, “Marr”) in view of U.S. Publication No. 2005/0160159 (hereinafter, “Zimmer”).
As per claim 2, Marr discloses an IHS, wherein the first request is transmitted during a boot sequence. (col 10 lines 0-3)
Marr does not distinctly disclose a Driver Execution Environment (DXE) phase.
However, Zimmer discloses wherein the first request is transmitted during a Driver Execution Environment (DXE) phase of a boot sequence. (Zimmer discloses a set of services that incudes “drivers” that are used during the DXE; ¶s [0035]-[0041] )
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Marr and Zimmer because both references are in the same field of endeavor. Zimmer’s teaching of managing driver during a DXE phase would enhance Marr's system by allowing a dispatcher system to be more flexible, secure and faster, thus enhancing booting operation of a computer system.
As per claim 4, Marr as modified discloses an IHS, wherein the processor comprises: a Reduced Instruction Set Computer (RISC) processor, or a comprises a Complex Instruction Set Computer (CISC) processor. (Zimmer: ¶ [0079] )
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Marr and Zimmer because both references are in the same field of endeavor. Zimmer’s teaching of a Reduced Instruction Set Computer (RISC) processor would enhance Marr's system by allowing the computer system to reduce power consumption thus improving battery level availibity.
As per claims 5, 15, Marr as modified discloses an IHS wherein the BIOS protocol driver comprises is configured to select the second request based, at least in part, upon a Look-Up Table (LUT). (Zimer: ¶ [0075] )
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Marr and Zimmer because both references are in the same field of endeavor. Zimmer’s teaching of a lookup table would enhance Marr's system by allowing the computer system to perform memory retrievals that are faster, more flexible and more efficient.
As per claim 6, Marr as modified discloses an IHS wherein the LUT comprises, for two or more different processors, and indication of whether a given processor supports the first request. (Marr: Col 4 lines 34-37 disclose: “queries” that determine “predetermined associations between vendor-specific firmware settings and abstracted firmware settings” (abstract & Col 2 line 20) for a plurality of computer devices that may have “a number of specific configurations”. These different configurations may based on the type of processors disclosed as FPGAs and ASICs (Col 15)Lastly, Col 14 further discloses a determination “none of the mappings corresponds to the requested computing attribute”. ) & (Zimmer: loading drivers for processor like RISC and CISC ¶ [0079])
As per claim 7, Marr as modified discloses an IHS wherein an entry in the LUT points to processor or memory specific diagnostic operation corresponding to the first request, and wherein the second request comprises the processor or memory specific diagnostic operation. (Marr: Col 5 lines 10-23 discloses Marr’s computer system generating “application programming interface (API)” call to provide an interface that is “vendor-specific” and that can be an be translated or “mapped” into a set of abstracted settings that are not vendor specific, for example, “Non-Uniform Memory Access (NUMA), memory speed”. Col 2 lines 12)
As per claim 8, Marr as modified discloses an HIS wherein the processor or memory specific diagnostic operation comprises at least one of: a Central Processing Unit (CPU) functional test, a Graphics Processing Unit (GPU) functional test, a processor core test, brand identification, operating frequency, cache size, registers, temperature, or memory controller. (Marr: “firmware controlled settings include the enabling of clock frequency scaling”; Col 3)
As per claim 9, Marr as modified discloses an IHS 9. The IHS of claim 7, wherein the processor or memory specific diagnostic operation comprises a memory integrity test.(Marr: “data integrity”; Col 15)
Claim(s) 12 rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent No. 9,372,731 (hereinafter, “Marr”) in view of U.S. Patent No. 9,836,295 (hereinafter, “Hoffman”).
As per claim 12, Marr does not distinctly discloses an IHS, wherein the context information comprises at least one of: a location of the IHS, an identity of a user of the IHS, an entitlement, or a license.
However, Hoffman explicitly discloses an IHS wherein the context information comprises at least one of: a location of the IHS, an identity of a user of the IHS, an entitlement, or a license. (Col 5 lines 55-65 and Col 10 lines 51-63)
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Marr and Hoffman because both references are in the same field of endeavor. Hoffman’s teaching of software entitlements would enhance Marr's system by allowing the computer system to implement certain software functionalities based on vendor’s authorization, thus preventing unauthorized access.
Claim(s) 20 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent No. 9,372,731 (hereinafter, “Marr”) in view of U.S. Publication No. 2020/0202004 (hereinafter, “Montero”).
As per claim 20. Marr discloses a hardware memory device, wherein the heterogenous computing platform. (FPGAs and ASICs; Col 15)
Marr does not distinctly disclose a system comprises a Reduced Instruction Set Computer (RISC) processor coupled to the EC via an interconnect, and wherein the interconnect comprises at least one of: an Advanced Microcontroller Bus Architecture (AMBA) bus, a QuickPath Interconnect (QPI) bus, or a HyperTransport (HT) bus.
However, Montero explicitly discloses a system comprises a Reduced Instruction Set Computer (RISC) processor coupled to the EC via an interconnect, and wherein the interconnect comprises at least one of: an Advanced Microcontroller Bus Architecture (AMBA) bus, a QuickPath Interconnect (QPI) bus, or a HyperTransport (HT) bus. (Fig. 1 illustrates an EC 107 couple to processor 101 that may be a RISC processor ¶ [0017] further couple by quicpath interconnect ¶ [0018] )
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Marr and Montero because both references are in the same field of endeavor. Monterro’s teaching of embedded contoller couple to RISC processor via a quickpath interconnect would enhance Marr's system by allowing the computer system to computer system to perform computer functions that are faster, more flexible and more efficient.
Conclusion
With respect to any newly added or amended claims, applicant should show support in the original disclosure for the new or amended claims. See MPEP §714.02 and § 2163.06. For example, when responding to this office action, applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AUREL PRIFTI whose telephone number is (571)270-1743. The examiner can normally be reached on M-F 8 a.m.- 6 p.m..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J. Jung can be reached on 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AUREL PRIFTI/Primary Examiner, Art Unit 2175
Aurel Prifti
Primary Examiner
Art Unit 2175
Tel. (571) 270-1743
Fax (571) 270-2743
aurel.prifti@uspto.gov