Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office acknowledges receipt of the following items from the Applicant:
Information Disclosure Statement (IDS) filed on 3/6/26, 1/7/26, 4/16/25 and
7/15/24 are considered.
Claims 1-20 are presented for examination.
Specification
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5, 8-16 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Roy et al, U.S. Patent 9,583,209.
With regard to claim 1 and 12, Roy discloses claimed is: an apparatus (fig. 2, memory architecture 200) comprising: a word line (fig. 2, WL0-WLn) (col. 5, line 20-23) coupled to a first plurality of memory cells (fig. 2, Upper bank Array 220) and second plurality of memory cells (fig. 2, Lower Bank Array 240); a first peripheral region (fig. 2, Upper Segment of Bitcells 224) comprising a first plurality of local input-output (LIO) lines (fig. 2, Local IO 262) and a first sense amplifier group on a first side of the word line (col. 1, Line 28-30 discloses each of the banks has sensing circuit); a first plurality of bit lines (fig. 2, BL upper) coupled to ones of the first plurality of memory cells (fig.2, Upper segment 224) and the first sense amplifier group (col. 1, L28-30), wherein the first plurality of bit lines extends through a break in the first plurality of LIO lines (fig. 2, local I/O 262) (also with regard to claim 13); and a second plurality of bit lines (fig. 2, BL Lower) coupled to ones of the second plurality of memory cells (fig. 2, Lower Segment of Bitcells 222) and the first sense amplifier group (col. 1, Line 28-30 discloses each of the banks has sensing circuit), wherein the second plurality of bit lines (fig. 2, BL Lower) extends over the first plurality of LIO lines (fig. 2, local I/O 262) (also with regard to claim 14).
With regard to claim 2 and 15, Roy discloses wherein a sense amplifier of the first sense amplifier group (each bank has a sense circuit (col. 1, line 28-30) is coupled to a bit line of the first plurality of bit lines (fig. 2, BL Upper) and a bit line of the second plurality of bit lines (fig. 2, Lower BL).
With regard to claim 3 and 16, Roy discloses wherein the first and second plurality of bit lines (fig. 2, BL Upper and BL Lower) are coupled to sense amplifiers of the first sense amplifier group on a same side of the first sense amplifier group (col. 1, Line 28-30).
With regard to claim 5, Roy discloses wherein at least one dummy bit line is disposed in the break of the LIO (col. 6, Line 12-23) (fig 4A, Isolation Bitcell 416).
With regard to claim 8, Roy discloses a column select on at least one side of the break in the first plurality of LIO lines (col.1, line 26-33).
With regard to claim 9, 10 and 11, Roy discloses the apparatus further comprising: a second sense amplifier group on the first side of the word line, wherein the first sense amplifier group and the second sense amplifier group are on opposite sides of the break in the first plurality of LIO lines; a third plurality of bit lines coupled to ones of the first plurality of memory cells and the second sense amplifier group, wherein the third plurality of bit lines extends through the break in the first plurality of LIO lines; and a fourth plurality of bit lines coupled to ones of the second plurality of memory cells and the second sense amplifier group, wherein the fourth plurality of bit lines extends over the first plurality of LIO lines (fig. 1, discloses multiple I/O sensing region, wherein the sense amplifier is part of the Local I/O) (col. 1, line 26-39).
With regard to claim 18, Roy further discloses a plurality of truncated bitlines routed off the diffusion layer coupling the plurality of sense amplifiers to the plurality of LIO lines (col. 2, line 37-67).
Allowable Subject Matter
Claims 4, 6-7, 17, 19 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With regard to claim 4, the prior art of record does not show the limitation of wherein the first plurality of memory cells are a first polarity and the second plurality of memory cells are a second polarity complementary to the first polarity.
With regard to claims 6, the prior art of record does not show the limitation of an apparatus further comprising: a second peripheral region comprising a second plurality of LIO lines and a second sense amplifier group on a second side of the word line; a third plurality of bit lines coupled to other ones of the first plurality of memory cells and the second sense amplifier group, wherein the third plurality of bit lines extends through a break in the second plurality of LIO lines; and a fourth plurality of bit lines coupled to other ones of the second plurality of memory cells and the second sense amplifier group, wherein the fourth plurality of bit lines extends over the second plurality of LIO lines
With regard to claim 17, the prior art of record does not show the limitation of wherein a second plurality of sense amplifiers are coupled to a third plurality and a fourth plurality of memory cells coupled to a second word line on an opposite of the first peripheral region from the word line.
With regard to claim 19 and 20, the prior art of record does not show the limitation of the apparatus further comprising: a third plurality of memory cells coupled to the word line; and a third plurality of bit lines coupled to ones of the third plurality of memory cells, wherein the third plurality of bit lines are routed off the diffusion layer.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicants’ disclosure. Tobori et al (2012/0039144) disclose a memory device includes: a plurality of memory cell arrays arranged along a predetermined direction; a plurality of bit lines to read data stored in a plurality of memory elements; a plurality of sense amplifier sections that amplify potentials appearing on selected bit lines, that amplify potentials in opposite phase to the potentials, and that output data signals and inverted data signals; a data output circuit that outputs the data to an external circuit based on the data signals and the inverted data signals; and a plurality of local signal lines extending parallel to the predetermined direction, to transmit the data signal and the inverted data signals to the data output circuit, wherein the local signal lines include two adjacent signal lines which are positionally switched around in a direction perpendicular to the predetermined direction alternately at predetermined intervals.
Tobori does not discloses the claimed invention having Single (1T) and multi (MT) memory cell architectures may be included in a same memory array, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.
When responding to the office action, Applicants’ are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs.
A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the date of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Connie Yoha, whose telephone number is (571) 272-1799. The examiner can normally be reached on Mon. - Fri. from 8:00 A.M. to 5:30 PM. The examiner's supervisor, Alexander Sofocleous, can be reached at (571) 272-0635. The fax phone number for this Group is (571) 273-8300.
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/CONNIE C YOHA/Primary Examiner, Art Unit 2825
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