Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office acknowledges receipt of the following items from the Applicant:
Information Disclosure Statement (IDS) filed on 7/14/26, 6/16/26, 3/6/26, 1/7/26,
4/16/25, 7/15/24 are considered.
Claims 1-20 are presented for examination.
Claims 1-8 are elected for examination.
Claims 9-20 are canceled.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Vimercati, U.S. Patent No. US 2022/059151.
With regard to claim 1, Vimercati discloses an apparatus (fig. 1, 100) comprising: a memory array (fig. 1, 118) (Page 2, [0021]) comprising a first region (Page 3, [0030]) including a first plurality of memory cells (Page 3, [0030]) coupled to a first plurality of word lines and a second plurality of memory cells coupled to a second plurality of word lines (Page 5, [0047]), wherein the first region further includes a first plurality of bit lines coupled to at least two memory cells of the first plurality of memory cells located in individual ones of the first plurality of word lines (Page 6, [0064]), and wherein the first region further includes a second plurality of bit lines coupled to at least two memory cells of the first plurality of memory cells located in individual ones of the second plurality of word lines (Page 4, [0064]).
With regard to claim 2, Vimercati discloses wherein the first plurality of bit lines are folded and the second plurality of bit lines are folded in a location disposed between the first plurality of word lines and the second plurality of word lines (Page 6, [0057]-[0062]).
With regard to claim 4, Vimercati discloses wherein the at least two memory cells of the first plurality of memory cells of the individual ones of the first plurality of word lines coupled to corresponding ones of the first plurality of bit lines have a same polarity (Fig. 4B)(Page 6, [0061]), and wherein the at least two memory cells of the second plurality of memory cells of the individual ones of the second plurality of word lines coupled to corresponding ones of the second plurality of bit lines have the same polarity (Page 7, [0066]).
With regard to claim 5, Vimercati discloses further comprising: a first peripheral region disposed on a first side of the first and second plurality of word lines comprising a first sense amplifier group, wherein the first plurality of bit lines are further coupled to the first sense amplifier group (Page 10, [0105]); and a second peripheral region on a second side of the first and second plurality of word lines comprising a second sense amplifier group, wherein the second plurality of bit lines are further coupled to the second sense amplifier group (Page 6, [0067]).
With regard to claim 6 Vimercati discloses further comprising a second region, wherein the second region comprises a third plurality of memory cells coupled to the first and second plurality of word lines (Page 3, [0030]) and a third plurality of bit lines, wherein the third plurality of bit lines is coupled to memory cells of the third plurality of memory cells in the first and second plurality of word lines (Page 5, [0047] and [0051]).
With regard to claim 7, Vimercati discloses, wherein a first portion of the third plurality of bit lines are coupled to a third sense amplifier group in the first peripheral region (Page 10, [0105]) and a second portion of the third plurality of bit lines are coupled to a fourth sense amplifier group in the second peripheral region (Page 5, [0047] and Page 7, [0067]).
With regard to claim 8, Vimercati discloses further comprising a first column select in the first region (Page 2, [0025]-[0026])and a second column select in the second region (Page 5, [0052]), wherein the first column select accesses half a number of bits the second column select accesses (Page 3, [0029]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Vimercati et al (Pat. Publication No. US 20220059151) in view of Hidaka et al (US 5416734).
With regard to claim 3, Vimercati, as applied in prior rejection, disclosed all claimed subject matter except wherein the location comprises at least one dummy word line. However, Hidaka teaches wherein the location comprises at least one dummy word line at a location associated with the bit line arrangement. In particular, Hidaka teaches an arrangement having dummy word line DWL0, DWL1, DWL2 and DWL3 disposed on both side of the cross points CP4 of bit-line pairs (fig. 9), wherein each dummy word line is provided with dummy cells at intersections with respective bit lines.
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the memory array of Vimercati to provide at least one dummy word line at the location, at taught by Hidaka, in order to provide dummy cells supplying a reference potential to a reference bit line during sensing and thereby facilitate reliable operation of the sense amplifier. Hidaka expressly teaches that the dummy cells can be reliably connected to the reference bit line by selection of the appropriate dummy word line, thereby preventing malfunction of the memory device.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicants’ disclosure. Takahashi et al (20230186971) disclose a memory device having a 1T/T2 memory cell architecture, including memory cells, word lines, bit/digit lines, and sense amplifiers. However, Takahashi does not teach the specific first/second bit line and first/second word line arrangement within the first region as claimed.
When responding to the office action, Applicants’ are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs.
A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the date of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Connie Yoha, whose telephone number is (571) 272-1799. The examiner can normally be reached on Mon. - Fri. from 8:00 A.M. to 5:30 PM. The examiner's supervisor, Alexander Sofocleous, can be reached at (571) 272-0635. The fax phone number for this Group is (571) 273-8300.
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/CONNIE C YOHA/Primary Examiner, Art Unit 2825
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