DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/18/2024, 06/03/2025 and 06/17/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 13 and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites the limitation "the first level" in page 4, line 8.
Claim 18 recites the limitation "the first level" in page 6, line 3.
There are insufficient antecedent basis for these limitation in the claim. For the purpose of compact prosecution, the limitation is interpreted as “a first level”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1-20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Park et al. (US 2022/0165857 A1, Park hereinafter).
Regarding claim 1, Park teaches a semiconductor device (Fig. 4A, flipping the direction of the device upside down for purpose of reading) comprising:
a substate (190);
a power distribution network layer (VDD/VSS in Fig. 20A) disposed on a lower surface of the substrate (P[0199]: “The ground line VSS and the power line VDD may be formed at a level which is higher than a top surface of each of the plurality of source/drain contacts 874 and the plurality of gate contacts 894”; Fig. 4A, top surface of 194 (same as 894) is on the lower surface of 190);
a source/drain pattern (SD1) disposed on the substrate (Fig. 4A);
a backside conductive structure (174/192) configured to penetrate the substrate (Fig. 4A, 192 penetrate 190) and to electrically connect the source/drain pattern and the power distribution network layer to each other (P[0199]: “ a ground line VSS may be connected to a fin-type active region FB through some of the plurality of source/drain contacts 874, and a power line VDD may be connected to a fin-type active region FB through the other source/drain contacts 874 of the plurality of source/drain contacts 874”);
and a remaining pattern (144) covering a side surface of an upper portion of the backside conductive structure (see annotated Fig. 4A for upper portion, 144 covers the side surface of 174. The annotated figure was flipped based on the direction of reading.).
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Regarding claim 2, Park teaches the semiconductor device of claim 1, wherein the remaining pattern includes silicon (Si). (P[0068]: insulation layer 144 may include silicon nitride)
Regarding claim 3, Park teaches the semiconductor device of claim 1, wherein a level of a lower surface of the remaining pattern is substantially constant (see annotated Fig. 4A, lower surface of 144 is constant).
Regarding claim 4, Park teaches the semiconductor device of claim 1, wherein a lower surface of the remaining pattern extends on a side surface (Fig. 4A, left side surface of 174B) of the backside conductive structure in a direction parallel to the lower surface of the substrate (see annotated Fig. 4A, lower surface of 144 extends in X direction).
Regarding claim 5, Park teaches the semiconductor device of claim 1, wherein a lower surface and a side surface (see annotated Fig. 4A) of the remaining pattern meet each other to form an angle of 90 degrees or more (see annotated Fig. 4A), and wherein the side surface of the remaining pattern is opposite to the side surface of the upper portion of the backside conductive structure (see annotated Fig. 4A, side surface of 114 is opposite to the right side surface of the upper portion).
Regarding claim 6, Park teaches the semiconductor device of claim 1, wherein the remaining pattern covers at least part of a side surface of a lower portion of the backside conductive structure (see annotated Fig. 4A for lower portion).
Regarding claim 7, Park teaches the semiconductor device of claim 1, wherein the backside conductive structure has a step (Fig. 4A, step between 174 and 192) at a first level (annotated Fig. 4A, same level as the lower surface of 144), and wherein a lower surface of the remaining pattern is positioned at a level substantially the same as or lower than the first level (annotated Fig. 4A).
Regarding claim 8, Park teaches the semiconductor device of claim 1, wherein the remaining pattern is a first remaining pattern, wherein the source/drain pattern is a first pattern of the source/drain pattern, wherein the semiconductor device further includes a second source/drain pattern (SD2) adjacent to the first pattern (Fig. 2D), and wherein the semiconductor device further includes a backside alignment pattern (see annotated Fig. 2D) and a second remaining pattern (176), wherein the backside alignment pattern is disposed below the second source/drain pattern (Fig. 2D), and the second remaining pattern covers a side surface of the backside alignment pattern (Fig. 2D).
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Regarding claim 9, Park teaches the semiconductor device of claim 8, wherein the first remaining pattern and the second remaining pattern are spaced apart from each other (Fig. 2D, 144 and 176 are spaced apart).
Regarding claim 10, Park teaches the semiconductor device of claim 8, further comprising a gate electrode (160AM) disposed on the substrate (Fig. 4A), wherein a side surface of the first remaining pattern (1st side in annotated Fig. 4A) and a side surface of the second remaining pattern (2nd side in annotated Fig. 4A), which faces the side surface of the first remaining pattern (annotated Fig. 4A), vertically overlap the gate electrode (annotated Fig. 4A, 1st side and 2nd side are vertically overlapped 160A).
Regarding claim 11, Park teaches the semiconductor device of claim 8, wherein a distance between the first remaining pattern and the second remaining pattern becomes smaller as the first remaining pattern and the second remaining pattern extend in a direction perpendicular to the lower surface of the substrate (see annotated Fig. 4A, distance D2 is smaller than D1 as 176 and 144 extends in Z direction).
Regarding claim 12, Park teaches the semiconductor device of claim 8, wherein a lower surface of the second remaining pattern is positioned at a level substantially equal to or lower than a lower surface of the backside alignment pattern (see annotated Fig. 2D).
Regarding claim 13, Park teaches a semiconductor device (Fig. 4A, flipping the direction of the device upside down for purpose of reading) comprising:
a substrate (190):
a power distribution network layer (VDD/VSS in Fig. 20A) disposed on a lower surface of the substrate (P[0199]: “The ground line VSS and the power line VDD may be formed at a level which is higher than a top surface of each of the plurality of source/drain contacts 874 and the plurality of gate contacts 894”; Fig. 4A, top surface of 194 (same as 894) is on the lower surface of 190);
a source/drain pattern (SD1) disposed on the substrate (Fig. 4A);
a backside conductive structure (174/192) penetrating the substrate (Fig. 4A, 192 penetrate 190) and electrically connecting the source/drain pattern and the power distribution network layer to each other (P[0199]: “ a ground line VSS may be connected to a fin-type active region FB through some of the plurality of source/drain contacts 874, and a power line VDD may be connected to a fin-type active region FB through the other source/drain contacts 874 of the plurality of source/drain contacts 874”);
and a remaining pattern (144) disposed on a side surface of the backside conductive structure (Fig. 4A), wherein the backside conductive structure has a step (Fig. 4A, step between 174 and 192) at the first level, and wherein a lower surface of the remaining pattern is positioned at a level substantially the same as or lower than the first level (see annotated Fig. 4A, lower surface is at the same level as the step).
Regarding claim 14, Park teaches the semiconductor device of claim 13, wherein the remaining pattern includes silicon (Si). (P[0068]: insulation layer 144 may include silicon nitride)
Regarding claim 15, Park teaches the semiconductor device of claim 13, wherein a level of the lower surface of the remaining pattern is substantially constant (see annotated Fig. 4A, lower surface of 144 is constant).
Regarding claim 16, Park teaches the semiconductor device of claim 13, wherein the lower surface of the remaining pattern extends on the side surface of the backside conductive structure in a direction parallel to the lower surface of the substrate (see annotated Fig. 4A, lower surface extends in direction X).
Regarding claim 17, Park teaches the semiconductor device of claim 13, wherein the remaining pattern is a first remaining pattern, wherein the source/drain pattern is a first pattern of the source/drain pattern, wherein the semiconductor further includes a second source/drain pattern (SD2) adjacent to the first pattern (Fig. 2D), wherein the semiconductor further includes a backside alignment pattern (see annotated Fig. 2D) and a second remaining pattern (176), wherein the backside alignment pattern is disposed below the second source/drain pattern (Fig. 2D), and the second remaining pattern is disposed on a side surface of the backside alignment pattern (Fig. 2D), and wherein the first remaining pattern and the second remaining pattern are spaced apart from each other (Fig. 2D, 176 and 144 are spaced apart).
Regarding claim 18, Park teaches a semiconductor device (Fig. 4A) comprising:
a substrate (190):
a power distribution network layer (VDD/VSS in Fig. 20A) disposed on a lower surface of the substrate (P[0199]: “The ground line VSS and the power line VDD may be formed at a level which is higher than a top surface of each of the plurality of source/drain contacts 874 and the plurality of gate contacts 894”; Fig. 4A, top surface of 194 (same as 894) is on the lower surface of 190);
an insulating pattern (FA) disposed on the substrate (Fig. 4A);
a source/drain pattern (SD1) disposed on the insulating pattern (Fig. 4A);
a channel pattern (nanosheet stack NSS) disposed on a side surface of the source/drain pattern (Fig. 4A), and including a plurality of semiconductor patterns (semiconductor oxide pieces 420B) stacked and spaced apart from each other (Fig. 4A, Fig. 15);
a gate electrode (160) disposed between the plurality of semiconductor patterns (Fig. 4A);
a backside conductive structure (174/192) penetrating the substrate (Fig. 4A, 192 penetrate 190) and electrically connecting the source/drain pattern and the power distribution network layer to each other (P[0199]: “ a ground line VSS may be connected to a fin-type active region FB through some of the plurality of source/drain contacts 874, and a power line VDD may be connected to a fin-type active region FB through the other source/drain contacts 874 of the plurality of source/drain contacts 874”);
and a remaining pattern (144) disposed on a side surface of the backside conductive structure (Fig. 4A), wherein the backside conductive structure has a step (Fig. 4A, step between 174 and 192) at the first level, and wherein a lower surface of the remaining pattern is positioned at a level substantially the same as or lower than the first level (see annotated Fig. 4A, lower surface is at the same level as the step).
Regarding claim 19, Park teaches the semiconductor device of claim 18, wherein the remaining pattern includes silicon (Si). (P[0068]: insulation layer 144 may include silicon nitride)
Regarding claim 20, Park teaches the semiconductor device of claim 18, wherein the lower surface of the remaining pattern extends on the side surface of the backside conductive structure in a direction parallel to the lower surface of the substrate (see annotated Fig. 4A, lower surface extends in direction X).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ganguly et al. (US 2021/0408246 A1) teaches a Si remaining pattern surrounding the S/D contacts.
Lu et al. (US 2022/0359679 A1) teaches a backside source/drain contact and a backside alignment structure.
Yu et al. (US 11,482,594 B2) teaches a backside source/drain contact and a backside alignment structure.
Van Dal et. al. (US 2022/0077062 A1) teaches a backside source/drain contact.
Cheng (US 2022/0293750 A1) teaches a stepped backside contact.
Wei et al. (US 2022/0139911 A1) teaches a stepped backside source/drain contact.
Kim et al. (US 2020/0373331 A1) teaches a backside S/D contact surrounded by a remaining pattern.
Yoon et al. (US 2022/0238689 A1) teaches the stepped S/D contacts surrounded by remaining patterns.
Ferng (US 2022/0359766 A1) teaches the stepped S/D contacts surrounded by remaining patterns.
Na et al. (US 12,635,218 B2) teaches the backside S/D contacts and the remaining patterns.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MO LI whose telephone number is (571)272-0395. The examiner can normally be reached Mon-Fri: 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Mo Li/Examiner, Art Unit 2818
/EVA Y MONTALVO/Supervisory Patent Examiner, Art Unit 2818
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