MEMORY SYSTEMS HAVING MEMORY DEVICES THEREIN WITH ENHANCED ERROR CORRECTION CAPABILITY AND METHODS OF OPERATING SAME

Application No. 18/746,565

• Filed: Jun 18, 2024
• Priority: Aug 30, 2021 — continuation of 11/605,441
  • Feb 03, 2023 — continuation of 12/057,184
• Examiner: YANG, HAN
• Art Unit: 2824
• Tech Center: 2800 — Semiconductors & Electrical Systems
• Assignee: Samsung Electronics Co., Ltd.
• OA Round: 1 (Non-Final)

Office Action

Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .

DETAILED ACTION

Claim Rejections - 35 USC § 102
1. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –

(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.

2. Claim(s) 1-7, 9, is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by HALBERT et al (Pub. No.: US 2017/0286197).
3. Regarding independent claim 1, HALBERT et al teaches a memory device (Fig. 1), comprising: a memory cell array (Fig. 2, #210) including memory cells (Fig. 2, #210, Read data 128b, paragraph [0018]) arranged into a plurality of nibbles (Fig. 2, #210, paragraph [0043], lines 6-7), each of the plurality of nibbles (Fig. 2, #210, paragraph [0043], lines 6-7) including a plurality of data lines (DQs) (Fig. 2, #210, Read data 128b, paragraph [0018]); and an error correction code (ECC) circuit (Fig. 2, #220) configured to perform error correction on data read (Fig. 2, paragraph [0045]) from the plurality of DQs (Fig. 2, #210, Read data 128b, paragraph [0018]), wherein the ECC circuit (Fig. 2, #220) is configured such that one or more miscorrections (Fig. 3, #320, paragraph [0079]) are bounded to at least one of the plurality of DQs (Fig. 2, #210, Read data 128b, paragraph [0018]) in one of the plurality of nibbles (Fig. 2, #210, paragraph [0043], lines 6-7).
4. Regarding claim 2, HALBERT et al teaches the one or more miscorrections (Fig. 3, #320, paragraph [0079]) are a second error (Fig. 3, #320) that results from the ECC circuit (Fig. 2, #220) attempting to correct a first error (Fig. 3, #308) in the data read from at least one of the plurality of DQs (Fig. 2, #210, Read data 128b, paragraph [0018]).
5. Regarding claim 3, HALBERT et al teaches a control logic circuit (Fig. 1, #130) configured to generate a control signal to perform a read operation on 128 bits of data (Fig. 1, Fig. 2, see paragraph [0044]) from the memory cell array (Fig. 2, #210).
6. Regarding claim 4, HALBERT et al teaches a size of each of the plurality of DQs (Fig. 2, #210, Read data 128b, paragraph [0018]) is a predetermined number of bits (see Fig. 2, Read data 128b, paragraph [0018]).
7. Regarding claim 5, HALBERT et al teaches the predetermined number of bits is 16 bits (see Fig. 2, Read data 128b, paragraph [0018]).
8. Regarding claim 6, HALBERT et al teaches the ECC circuit (Fig. 2, #220) is configured such that the one or more miscorrections (Fig. 3, #320, paragraph [0079]) are bounded to one DQ (Fig. 3, #314) among the plurality of DQs (Fig. 2, #210, Read data 128b, paragraph [0018]).
9. Regarding claim 7, HALBERT et al teaches the ECC circuit (Fig. 2, #220) is configured such that the one or more miscorrections (Fig. 3, #320, paragraph [0079]) are bounded to two DQs (Fig. 2, paragraph [0079]) among the plurality of DQs (Fig. 2, #210, Read data 128b, paragraph [0018]).
10. Regarding claim 9, HALBERT et al teaches the ECC circuit (Fig. 2, #220) is configured to perform the error correction on a single bit error (Fig. 3, #314) or an adjacent 2-bit error (Fig. 2, #318) in the memory cell array (Fig. 2, #210).
Claim Rejections - 35 USC § 103
11. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.

12. Claim(s) 8, 10-18, is/are rejected under 35 U.S.C. 103 as being unpatentable over HALBERT et al (Pub. No.: US 2017/0286197) in view of TAKAHASHI (Pub. No.: US 2019/287640).
13. Regarding claim 8, HALBERT et al teaches the one or more miscorrections (Fig. 3, #320, paragraph [0079]) in the at least one of the plurality of DQs (Fig. 2, #210, Read data 128b, paragraph [0018]) is corrected by a ECC circuit (Fig. 2, #220) of a memory controller.
HALBERT et al is silent with respect to first and second ECC circuits.
TAKAHASHI et al teaches first and second ECC circuits (Fig. 1, #15A, #15B).
It would have been obvious to one of ordinary skill in the art at the time of the invention to apply the teachings of TAKAHASHI to the teaching of HALBERT et al such that the second ECC circuit can perform a second errors corrections in case of a hard error occurred (TAKAHASHI paragraph [0024]).

10. Regarding independent claim 10, HALBERT et al teaches a memory system (Fig. 1), comprising: a memory controller (Fig. 2A, #240) comprising a error correction code (ECC) circuit (Fig. 2, #220) configured to perform a error correction; and a memory device (Fig. 1) connected to the memory controller (Fig. 2A, #240), and comprising: a memory cell array (Fig. 2, #210) including memory cells (Fig. 2, #210, Read data 128b, paragraph [0018]) arranged into a plurality of nibbles (Fig. 2, #210, paragraph [0043], lines 6-7), each of the plurality of nibbles (Fig. 2, #210, paragraph [0043], lines 6-7) including a plurality of data lines (DQs) (Fig. 2, #210, Read data 128b, paragraph [0018]); and a ECC circuit (Fig. 2, #220) configured to perform second error correction on data read from the plurality of DQs (Fig. 2, #210, Read data 128b, paragraph [0018]), wherein the ECC circuit (Fig. 2, #220) is configured such that one or more miscorrections (Fig. 3, #320, paragraph [0079]) are bounded to at least one of the plurality of DQs (Fig. 2, #210, Read data 128b, paragraph [0018]) in one of the plurality of nibbles (Fig. 2, #210, paragraph [0043], lines 6-7).
HALBERT et al is silent with respect to first and second ECC circuits.
TAKAHASHI et al teaches first and second ECC circuits (Fig. 1, #15A, #15B).
It would have been obvious to one of ordinary skill in the art at the time of the invention to apply the teachings of TAKAHASHI to the teaching of HALBERT et al such that the second ECC circuit can perform a second errors corrections in case of a hard error occurred (TAKAHASHI paragraph [0024]).
2. Regarding claim 11, HALBERT et al teaches the one or more miscorrections (Fig. 3, #320, paragraph [0079]) are a second error (Fig. 3, #320) that results from the ECC circuit (Fig. 2, #220) attempting to correct a first error (Fig. 3, #308) in the data read from at least one of the plurality of DQs (Fig. 2, #210, Read data 128b, paragraph [0018]).
3. Regarding claim 12, HALBERT et al teaches a control logic circuit (Fig. 1, #130) configured to generate a control signal to perform a read operation on 128 bits of data (Fig. 1, Fig. 2, see paragraph [0044]) from the memory cell array (Fig. 2, #210).
4. Regarding claim 13, HALBERT et al teaches a size of each of the plurality of DQs (Fig. 2, #210, Read data 128b, paragraph [0018]) is a predetermined number of bits (see Fig. 2, Read data 128b, paragraph [0018]).
5. Regarding claim 14, HALBERT et al teaches the predetermined number of bits is 16 bits (see Fig. 2, Read data 128b, paragraph [0018]).
6. Regarding claim 15, HALBERT et al teaches the ECC circuit (Fig. 2, #220) is configured such that the one or more miscorrections (Fig. 3, #320, paragraph [0079]) are bounded to one DQ (Fig. 3, #314) among the plurality of DQs (Fig. 2, #210, Read data 128b, paragraph [0018]).
7. Regarding claim 16, HALBERT et al teaches the ECC circuit (Fig. 2, #220) is configured such that the one or more miscorrections (Fig. 3, #320, paragraph [0079]) are bounded to two DQs (Fig. 2, paragraph [0079]) among the plurality of DQs (Fig. 2, #210, Read data 128b, paragraph [0018]).
17. Regarding claim 17, HALBERT et al teaches the one or more miscorrections (Fig. 3, #320, paragraph [0079]) in the at least one of the plurality of DQs (Fig. 2, #210, Read data 128b, paragraph [0018]) is corrected by the first ECC circuit (Fig. 2, #220) of the memory controller (Fig. 2, #220) performing the first error correction (Fig. 3, #310).
18. Regarding claim 18, HALBERT et al teaches teaches the ECC circuit (Fig. 2, #220) is configured to perform the error correction on a single bit error (Fig. 3, #314) or an adjacent 2-bit error (Fig. 2, #318) in the memory cell array (Fig. 2, #210).
HALBERT et al is silent with respect to first and second ECC circuits.
TAKAHASHI et al teaches first and second ECC circuits (Fig. 1, #15A, #15B).
It would have been obvious to one of ordinary skill in the art at the time of the invention to apply the teachings of TAKAHASHI to the teaching of HALBERT et al such that the second ECC circuit can perform a second errors corrections in case of a hard error occurred (TAKAHASHI paragraph [0024]).

Conclusion

22. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure, YIM et al (Pub. No.: US 2008/0163033).
YIM et al (Pub. No.: US 2008/0163033) shows ECC circuits.
23. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Han Yang whose telephone is [phone]. The examiner can normally be reached on Monday-Friday 8am-5pm with alternate Friday off. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on [phone]. The fax phone number for the organization where this application or proceeding is assigned is [phone].
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HY
12/05/2025
/HAN YANG/
Primary Examiner, Art Unit 2824

Prosecution Timeline

• Jun 18, 2024: Application Filed
• Dec 10, 2025: Non-Final Rejection mailed — §102, §103 (current)