DETAILED ACTION
Claim Objections
Claim 1 is objected to because of “to” in the phrase “wherein the logic unit is structured to…to supply” is repeated (second occurrence “to” should be deleted). Clarification or Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 6-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Schmalzl (US 10,761,135).
Regarding claim 1, Schmalzl (Figs. 1-6) discloses a successive approximation register A/D converter (SAR ADC; col. 6, lines 1-45) having redundancy structured to convert an analog input voltage (an input voltage received by sampling elements 110, 510 or 610) into a digital output (ADC result), the successive approximation register A/D converter comprising:
an analog unit (including elements 510, 514, 520 and 530 shown in Fig. 5) structured to sample the analog input voltage (an input voltage received by sampling elements 110, 510 or 610) and generate a comparison signal (output of the comparator 530) indicating a magnitude relationship between a threshold voltage (reference signal 522) corresponding to a control code and the analog input voltage (col. 5, lines 55-67); and
a logic unit (540) structured to generate the control code of a next cycle corresponding to the comparison signal for each cycle,
wherein the logic unit is structured to generate, in an i-th (i ≥1) cycle, a first value obtained by adding a weight of an (i + 1)-th cycle to the control code of the i-th cycle and a second value obtained by subtracting the weight of the (i + 1)-th cycle from the control code of the i-th cycle, and wherein the logic unit is structured to, when the comparison signal of the i-th cycle is determined, to supply one of the first value and the second value corresponding to the comparison signal to the analog unit as the control code of the (i + 1)-th cycle (“…BIST control 542, through control 562, causes adder 566 to add or subtract bit weights 564 from the previous control value. Latch 568 then holds and delivers the updated control value to DAC array 520”).
Regarding claim 6, Schmalzl (Figs. 1-6) discloses the successive approximation register A/D converter according to claim 1, wherein the analog unit includes a capacitance array D/A converter (col. 6, lines 60-66) structured to sample the analog input voltage (col. 7, lines 20-24), convert the control code into a threshold voltage (122, 522 or 622), and output a signal (of the comparator) corresponding to the analog input voltage (112) and the threshold voltage (122), and a comparison circuit (130, 530 or 630) structured to receive the output of the capacitance array D/A converter and perform comparison processing (col. 6, lines 48-59).
Regarding claim 7, Schmalzl (Figs. 1-6) discloses the successive approximation register A/D converter according to claim 1, wherein the successive approximation register A/D converter is integrally integrated on one semiconductor substrate (“Arrays 410, 420 and processing circuitry 440 may be integrated on a single semiconductor substrate”; col. 9, lines 14-15).
Allowable Subject Matter
Claims 2-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 2, Schmalzl fails to anticipate “a first limiter structured to limit the first value to a predetermined upper limit value”.
Regarding claim 3, Schmalzl fails to anticipate “a second limiter structured to limit the second value to a predetermined lower limit value”.
Regarding claims 4-5, Schmalzl fails to anticipate “the logic unit includes a flip-flop structured to hold the comparison signal, a calculation unit structured to calculate the first value and the second value, and a multiplexer structured to receive the first value and the second value and output one of the first value and the second value corresponding to an output of the flip-flop as the control code”.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAI M NGUYEN whose telephone number is (571)272-1809. The examiner can normally be reached Mon-Fri: 8:00 am - 4:30pm.
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/KHAI M NGUYEN/Primary Examiner, Art Unit 2845