DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawings
Figures 1-5 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action.
The objection to the drawings will not be held in abeyance.
The drawings are objected to because Figure 7 shows ERROR AMPLIFIER 710 is shown receiving the negative feedback voltage at the inverting terminal, which disagrees with the specification and is incorrect, for if the output voltage were low, VEA_OUT would be high which would turn on MN1 which would pull down the gate of MCTRL which would further pull down the output voltage. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action.
The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities: the specification alternately uses the terminology ‘flip voltage follower’ and ‘flipped voltage follower’ which should be ‘flipped voltage follower’. The specification also alternately uses the terminology ‘rectifier circuit’ and ‘regulator circuit’ which should be ‘regulator circuit’.
Appropriate correction is required.
Claim Objections
Claims 3-5 and 6-7 are objected to because of the following informalities:
In claim 3, line 1, “further comprises” should be ‘further comprising’.
In claim 5, line 5, “the gate node” lacks antecedent basis for transistor MN2, and to differentiate from ‘a gate node’ recited in claims 1 and 2, should be ‘a gate node of transistor MN2’.
In claim 6, line 1, “further comprises” should be ‘further comprising’.
In claim 7, line 3, “a supply voltage” has already been recited and should be ‘the supply voltage’.
In claim 7, line 7, “a contact node” has already been recited and should be ‘the contact node’.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Where Applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The term “flip voltage follower rectifier circuit” in claims 1 and 8 is used by the claim to mean “flipped voltage follower regulator circuit,” while the accepted meaning is “an AC/DC rectifier.” Examiner notes ‘flip’ does not have the same meaning as ‘flipped’, and the accepted term in the art is ‘flipped voltage follower’, not ‘flip voltage follower’; the terminology must be used consistently throughout the drawings and the specification. Examiner reminds Applicant that a rectifier circuit converts AC/DC by permitting only unidirectional current flow such as with a diode, that ‘rectifier’ has a different meaning from ‘regulator’, and that the terminology must be consistent throughout the specification and the claims. The term is indefinite because the specification does not clearly redefine the term.
In claim 1, lines 5-6, as well as in claim 8, lines 5-6, the claim limitation “an error amplifying circuit unit configured to receive and compare a reference signal and a feedback voltage, wherein the feedback voltage is fed back through the output voltage through a feedback loop” when interpreted in light of the specification is indefinite because the feedback voltage is not fed back through the output voltage. It is not possible to feedback through the output voltage, instead, the output voltage is fed back through the feedback loop. For the purpose of examination, the claim shall be interpreted as ‘an error amplifying circuit unit configured to receive and compare a reference signal and a feedback voltage, wherein the feedback voltage is fed back from the output voltage through a feedback loop’.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 and 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Lu (“A 312 ps response-time LDO with enhanced super source follower in 28 nm CMOS”) in view of Magod (US 2019/0258282).
With respect to claim 1, Lu discloses an LDO regulator circuit apparatus capable of attenuating supply voltage noise comprising: a flip voltage follower regulator circuit unit (Fig. 2 MP,M1,IB1) having a pass transistor MPASS (Fig. 2 MP) configured to adjust a supply voltage (Fig. 2 VIN) to output an output voltage (Fig. 2 VOUT); an error amplifying circuit unit (Fig. 2 M8-M13, IB2, IB3) configured to receive and compare a reference signal (Fig.2 VREF) and a feedback voltage (Fig. 2 VMIR), wherein the feedback voltage is fed back through the output voltage through a feedback loop (Fig. 2 R1,R2); a common gate circuit unit (Fig. 2 M2, IB4) configured to amplify a feedback loop gain of the flip voltage follower rectifier circuit unit; and a super source follower circuit unit (Fig. 2 IB6, IB7, IB8,M4,M5,M6,M7) configured to buffer an output of the CG circuit unit and transmit it to a gate node (Fig. 2 VG) of the pass transistor MPASS. Lu discloses wherein the feedback voltage is a mirrored version of the output voltage and does not disclose wherein the feedback voltage is fed back through the output voltage through a feedback loop. It was very well known before the time of filing of the claimed invention to implement wherein the feedback voltage is fed back through the output voltage through a feedback loop.
Magod discloses an LDO regulator wherein the feedback voltage (Fig. 2 Vout) is fed back through the output voltage through a feedback loop (Fig. 2 Vout feedback to MN2). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement wherein the feedback voltage is fed back through the output voltage through a feedback loop, in order to improve response to disturbances in the output voltage.
With respect to claim 2, Lu in view of Magod make obvious the LDO regulator circuit apparatus of claim 1, wherein the flip voltage follower regulator circuit unit comprises, a transistor MCTRL (Fig. 2 M1) whose gate node is an input terminal of the flipped voltage follower regulator circuit unit; and a current source (Fig. 2 IB1), wherein a drain node of the pass transistor is connected (Fig. 2 connected at VOUT) to a source node of a transistor MCTRL, a drain node of the transistor MCTRL is connected to the current source which is connected to ground (Fig. 2 ground symbol). Lu discloses wherein the current source is represented by a current source symbol and does not display the current source as a transistor. It was very well known before the filing of the claimed invention to implement a current source as a biased transistor.
Magod discloses a transistor MBIAS (Fig. 10 MN7) operating as a current source, wherein a drain node of the transistor MCTRL (Fig.10 MP8) is connected to a drain node of a transistor MBIAS (Fig. 10 MN7), and a source node of the transistor MBIAS is connected to ground (Fig. 10 ground symbol). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement a transistor MBIAS operating as a current source, wherein a drain node of the pass transistor MPASS is connected to a source node of a transistor MCTRL, a drain node of the transistor MCTRL is connected to a drain node of a transistor MBIAS, and a source node of the transistor MBIAS is connected to ground, in order to improve response to disturbances in the output voltage, in order to implement the bias current as a transistor which can be integrated with the LDO regulator circuit transistors.
With respect to claim 3, Lu in view of Magod make obvious the LDO regulator circuit apparatus of claim 2 as set forth above. Lu discloses a control circuit unit (Fig. 2 M13, M8, IB2) configured to transmit an output (Fig. 2 output to gate of M13) of the error amplifying circuit unit to a gate node of the transistor MCTRL (Fig. 2 M1) according to a bias (Fig. IB2). Lu discloses the current source IB2 without showing the transistor implementation which was well known before the filing of the claimed invention.
Magod discloses implementing a current source with a transistor (Fig. 10 MN1) and a bias voltage (Fig. 10 gate voltage of MN0). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement a control circuit unit configured to transmit an output of the error amplifying circuit unit to a gate node of the transistor MCTRL according to a bias voltage, in order to implement the current source with an integratable circuit technology of a transistor to provide the desired bias voltage.
With respect to claim 5, Lu in view of Magod make obvious the LDO regulator circuit apparatus of claim 2, wherein the CG circuit unit comprises a transistor MN2 (Fig. 2 M2) wherein a source node of the transistor MN2 is connected to a drain node of the transistor MCTRL (Fig. 2 M1) and an output of the drain node of the transistor MCTRL is amplified according to a bias voltage (Fig. 2 VB1) applied to a gate node of the transistor MN2 and transmitted (Fig. 2 VA2) to the super source follower circuit unit.
With respect to claim 6, Lu in view of Magod make obvious the LDO regulator circuit apparatus of claim 2 further comprises, a transistor MN4 (Fig. 2 M3) configured to buffer an output of the CG circuit unit to an input of the super source follower circuit unit.
With respect to claim 7, Lu in view of Magod make obvious the LDO regulator circuit apparatus of claim 6, wherein the super source follower circuit unit comprises, a current source MP4 (IB7) and MP5 (Fig. 2 M7) configured to receive a supply voltage (Fig. 2 VIN) at a source node, current source MN5 (Fig. 2 IB6) and MN6 (Fig. 2 M6) whose source nodes are connected to ground, and a transistor MP3 (Fig. 2 M4) whose gate node is connected to a source node of the transistor MN4 (Fig. 2 M3) wherein a contact node (Fig. 2 VG), in which the current source MP4 and a source node of the transistor MP3 are connected, and a contact node, in which a drain node of the transistor MP5 and a drain node of the transistor MN6 are connected, are respectively connected to a gate node of the pass transistor MPASS. Lu discloses wherein the transistor MP4 is depicted as a current source and Lu does not explicitly depict the current source as a transistor.
It was very well known before the filing of the claimed invention to implement a current source as a biased transistor.
Magod discloses implementing a current source as a transistor (Fig. 10 MP9) configured to receive a supply voltage (Fig. 10 Vcp) and a drain of the transistor is connected to the contact node (Fig. 10 Vgate) and the source node of the transistor MP3 are connected (Fig. 10 MP8). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement wherein the super source follower circuit unit comprises, transistors MP4 and MP5 configured to receive a supply voltage at a source node, transistors MN5 and MN6 whose source nodes are connected to ground, and a transistor MP3 whose gate node is connected to a source node of the transistor MN4, wherein a contact node, in which a drain node of the transistor MP4 and a source node of the transistor MP3 are connected, and a contact node, in which a drain node of the transistor MP5 and a drain node of the transistor MN6 are connected, are respectively connected to a gate node of the pass transistor MPASS, in order to implement the bias current as a transistor which can be integrated with the LDO regulator circuit transistors.
Allowable Subject Matter
Claims 8-9 are rejected as indefinite as stated above, but claims 8-9 would be allowed if the indefiniteness type rejections stated above were overcome. The following is an examiner’s statement of reasons for allowance: Lu in view of Magod make obvious the LDO regulator circuit apparatus capable of attenuating supply voltage noise comprising as detailed above in claim 1, but the prior art does not disclose or suggest, a class AB circuit unit located between the pass transistor MPASS and the super source follower circuit unit and configured to pull up or pull down a gate node of the pass transistor MPASS in an overshoot or undershoot situation of the output voltage.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 4 is rejected as being indefinite, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if the indefiniteness type rejections stated above were overcome.
With respect to claim 4, the prior art does not disclose or suggest, in combination with the limitations of the base claim and any intervening claims, primarily, wherein the control circuit unit has a transistor MN1 and a transistor MP1, wherein a bias voltage is applied to a source node of the transistor MP1, and a gate node of the transistor MP1 is connected to the gate node of the transistor MCTRL, wherein a gate node of the transistor MN1 receives an output signal of the error amplifying circuit unit, the source node is connected to the ground, and the drain node is connected to a drain node of the transistor MP1.
The aforementioned limitations in combination with all remaining limitations of the respective claims are believed to render the aforementioned indicated claim and any dependent claims thereof patentable over the art of record.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HARRY RAYMOND BEHM whose telephone number is (571)272-8929. The examiner can normally be reached M-F: 8-5 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu Tran can be reached at 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HARRY R BEHM/Primary Examiner, Art Unit 2838