DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for examination.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4,7-14,17-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ku (Patent No. U.S. 10,600,493).
Regarding claim 1, Ku discloses a shift circuit (Figure 1,10), comprising:
a data selector (Figure 1, 11-14), comprising: a first input terminal, a second input terminal, a third input terminal, a fourth input terminal (Figure IN0-IN3), and an output terminal (Figure 1, OUT0-OUT3), wherein
the first input terminal is configured to access a first control signal (Figure 1, M0), the third input terminal is configured to access a second control signal (Figure 1, M1), and the first control signal and the second control signal are inverse signals to each other (Column 4, lines 54-60),
the fourth input terminal is configured to access a first bit in input data Figure 1, IN3),
the second input terminal is configured to access a second bit in the input data (Figure 1, IN1);
when the first control signal is in a first state, the output terminal outputs an inverted value of the second bit (Column 4, lines 43-53, M0 at high level); and
when the first control signal is in a second state, the output terminal outputs an inverted value of the first bit (Column 4, lines 64-67, Column 5, lines 1-19, M0 at low level).
Regarding claim 2, Ku discloses comprising a plurality of data selectors (Figure 1, 11-14), wherein the second input terminal of the data selector (Figure 1, IN1) is configured to access a corresponding second bit of the input data after being shifted by 2i bits, (Column 7, lines 64-67) wherein i comprises any integer greater than or equal to 0 (Column 7, lines 64-67).
Regarding claim 3, Ku discloses comprising: n levels of sub-shift circuits, wherein each of the sub-shift circuits comprises the plurality of data selectors and is configured to: receive the input data, and shift the input data by 2i bits, wherein the input data comprises output data of a previous level of sub-shift circuit or original input data , and a value of i of any level of sub-shift circuit of the n levels of sub-shift circuits comprises any integer from 0 to n-1, wherein a value of n comprises any integer greater than or equal to 1 (Figure 1, Ku discloses level shift integer n equal to 1).
Regarding 4, Ku discloses wherein the sub-shift circuit is configured to: receive the input data, and shift the input data by 2i bits under control of one bit in a shift factor, wherein a bit in the shift factor is to generate a first control signal (Figure 1, M0) and a second control signal (Figure 1, M1) for a corresponding level (Column 4, lines 33-40, Column 5, lines 20-22).
Regarding claim 7, Ku discloses wherein a number of the plurality of data selectors of the shift circuit is equal to a number of bits of the input data multiplied by a number of levels (Figure 1, Column 3, lines 42-57).
Regarding claim 8, Ku discloses further comprising an inverter circuit (Column 4, lines 44-45) coupled with the third input terminal, wherein the first input terminal and the inverter circuit are configured to access a high level, the first control signal at the high level is in the first state, and the third input terminal is configured to access a low level output by the inverter circuit; or the first input terminal and the inverter circuit are configured to access a low level, the first control signal at the low level is in the second state (Column 4, lines 64-67, Column 5, lines 1-19), and the third input terminal is configured to access a high level output by the inverter circuit (Column 5, lines 5-20).
Regarding claim 9, Ku discloses further comprising an inverter circuit coupled with the first input terminal, wherein the inverter circuit and the third input terminal are configured to access a high level (Column 6, lines 12-20) , the first input terminal is configured to access a low level output by the inverter circuit (Column 4, lines 28-33), and the first control signal at the low level is in the first state (Figure 2, M0 is 0); or the inverter circuit and the third input terminal are configured to access a low level, the first input terminal is configured to access a high level output by the inverter circuit, and the first control signal at the high level (Figure 2, M is 1) is in the second state.
Regarding claim 10, Ku discloses a memory controller (Figure 8, 320), wherein the memory controller is configured to perform an encoding operation according to program data in response to a program operation to generate a check code (Figure 2) and comprises a shift circuit (Figure 1), wherein the shift circuit comprises:
a data selector (Figure 1, 11-14), comprising: a first input terminal, a second input terminal, a third input terminal, a fourth input terminal (Figure IN0-IN3), and an output terminal (Figure 1, OUT0-OUT3), wherein
the first input terminal is configured to access a first control signal (Figure 1, M0), the third input terminal is configured to access a second control signal (Figure 1, M1), and the first control signal and the second control signal are inverse signals to each other (Column 4, lines 54-60), the fourth input terminal is configured to access a first bit in input data Figure 1, IN3) , the second input terminal is configured to access a second bit in the input data (Figure 1, IN1);
when the first control signal is in a first state, the output terminal outputs an inverted value of the second bit (Column 4, lines 43-53, M0 at high level); and
when the first control signal is in a second state, the output terminal outputs an inverted value of the first bit (Column 4, lines 64-67, Column 5, lines 1-19, M0 at low level).
wherein the shift circuit is configured to output the inverted value of the second bit or the inverted value of the first bit in response to the encoding operation (Column 5, lines 5-19).
Regarding claim 11, KU discloses further configured to: perform a decoding operation according to the check code (Column 13, lines 19-47, SHIFT_WR high level, read operation is performed) in response to a read error to readout data, wherein the shift circuit is configured to output the inverted value of the second bit or the inverted value of the first bit in response to the decoding operation (Column 4, lines 34-67, Column 5, lines 1-20).
Regarding claim 12, Ku discloses wherein the shift circuit comprises a plurality of data selectors (Figure 1, 11-14), and the second input terminal of the data selector is configured to access a corresponding second bit of a shift of 2i bits of the input data, wherein i comprises any integer greater than or equal to 0 (Column 5, lines 48-55, four bits).
Regarding claim 13, Ku discloses wherein the shift circuit comprises: n levels of sub-shift circuits, wherein each of the sub-shift circuits comprises the plurality of data selectors and is configured to: receive the input data, and shift the input data by 2i bits, wherein the input data comprises output data of a previous level of sub-shift circuit or original input data, and a value of i of any level of sub-shift circuit of the n levels of sub-shift circuits comprises any integer from 0 to n-1, wherein a value of n comprises any integer greater than or equal to 1 (Figure 1, n=1).
Regarding claim 14, Ku discloses wherein the sub-shift circuit is configured to: receive the input data, and shift the input data by 2i bits under control of one bit in a shift factor (Figure 2), wherein a bit in the shift factor is to generate a first control signal and a second control signal (Figure 2, M0, M1) for a corresponding level (Column 5, lines 20-22).
Regarding claim 17, Ku discloses wherein a number of the plurality of data selectors of the shift circuit is equal to a number of bits of the input data multiplied by a number of levels (Column 8, lines 8-10, Figure 1, four shift circuits, four bits).
Regarding claim 18, Ku discloses wherein the shift circuit further comprises an inverter circuit coupled with the third input terminal, wherein the first input terminal and the inverter circuit are configured to access a high level, the first control signal at the high level is in the first state, and the third input terminal is configured to access a low level output by the inverter circuit; or the first input terminal and the inverter circuit are configured to access a low level, the first control signal at the low level is in the second state, and the third input terminal is configured to access a high level output by the inverter circuit (Column 4, lines 34-67, Column 5, lines 1-22).
Regarding claim 19, Ku discloses wherein the shift circuit further comprises an inverter circuit coupled with the first input terminal, wherein the inverter circuit and the third input terminal are configured to access a high level, the first input terminal is configured to access a low level output by the inverter circuit, and the first control signal at the low level is in the first state; or the inverter circuit and the third input terminal are configured to access a low level, the first input terminal is configured to access a high level output by the inverter circuit, and the first control signal at the high level is in the second state (Column 4, lines 26-76, Column 5, lines 1-22).
Regarding claim 20, Ku discloses a memory system (Figure 8), comprising:
a memory device (Figure 8, 310); and
a memory controller (Figure 8, 320) coupled with the memory device and configured to control the memory device, wherein the memory controller is configured to perform an encoding operation (Figure 8, 322) according to program data in response to a program operation to generate a check code (Column 13, lines 19-47, depend SHIFT_WR logic high level, read operation is performed) and comprises a shift circuit (Figure 1), wherein the shift circuit comprises:
a data selector (Figure 1, 11-14), comprising a first input terminal, a second input terminal, a third input terminal, a fourth input terminal (Figure 1, IN0-IN3), and an output terminal (Figure 5, SEL_IN1), wherein the first input terminal is configured to access a first control signal, the third input terminal is configured to access a second control signal, the first control signal and the second control signal (Figure 2) are inverse signals to each other (Figure 1,M1, M2), the fourth input terminal is configured to access a corresponding first bit in input data, and the second input terminal is configured to access a corresponding second bit in the input data (Figure 3), and
when the first control signal is in a first state (Figure 2, M1, M2), the output terminal outputs an inverted value of the second bit (Figure 5, Column 8, lines 61-67, Column 9, lines 1-23); and when the first control signal is in a second state, the output terminal outputs an inverted value of the first bit (Figure 5, Column 8, lines 61-67, Column 9, lines 1-23);
wherein the shift circuit is configured to output the inverted value of the second bit or the inverted value of the first bit in response to the encoding operation (Figure 5, Column 8, lines 61-67, Column 9, lines 1-23).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-6,15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Ku as applied to claims 5-6, 15-16 above, and further in view of Babin (Patent No. 5,941,974).
Regarding claims 5-6, 15-16, Ku discloses the claimed invention except for n is an even number, Babin teaches that it is know in the art to provide the n levels is an even number of sub-shift circuits in Figure 1, 57, 59. It would have been obvious to one having ordinary skill in the art at the time the invention was made to arrange the sub-shift circuits is an even number levels, since it has been held that arrangements of an element and its function and general conditions in a combination where the remaining elements perform the same functions as before involves only routine skill in the art.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THONG QUOC LE whose telephone number is (571)272-1783. The examiner can normally be reached 7:30AM-5:30PM.
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/THONG Q LE/ Primary Examiner, Art Unit 2827