DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim 16 is objected to because of the following informalities:
16. The semiconductor memory device of claim 15, wherein each of the tunneling insulating layer and the blocking insulating layer includes a silicon oxide layer, and the charge storage layer includes a silicon nitride layer.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 5, 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang et al. US 2023/0099107.
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Zhang et al. US 2023/0099107
Regarding claim 1, Zhang et al. in Fig. 27 disclose a semiconductor memory device comprising:
a first stacked structure including a plurality of first gate electrodes 146 [0124] sequentially stacked and spaced apart from each other;
a second stacked structure on the first stacked structure, the second stacked structure including a plurality of second gate electrodes 246 [0124] sequentially stacked and spaced apart from each other; and
a channel structure extended in a vertical direction to pass through the first stacked structure 160L [0089] and the second stacked structure 260L [0117], wherein the channel structure includes, a channel layer including a first pillar portion 160L crossing the plurality of first gate electrodes, a second pillar portion 260L crossing the plurality of second gate electrodes, and
a horizontal portion 363 [0096] extended along a plane crossing the vertical direction, the horizontal portion 363 connecting the first pillar portion 160L and the second pillar portion 260L, and
a data storage layer 50 [0172] extending along an outer side of the channel layer.
Regarding claim 2, Zhang et al. in Fig. 27 disclose the semiconductor memory device of claim 1, wherein a width of the first pillar portion 160L is reduced as the first pillar portion is directed toward the second stacked structure, and a width of the second pillar portion 260L is reduced as the second pillar portion is directed toward the first stacked structure Figs. 25A-Fig. 27.
Regarding claim 5, Zhang et al. in Fig. 27 disclose the semiconductor memory device of claim 1, wherein the channel structure further includes:
a first filling insulating layer 162 at least partially filling an inside of the first pillar portion 160L; and
a second filling insulating layer 262 at least partially filling an inside of the second pillar portion; and
wherein the horizontal portion 363 separates the first filling insulating layer 162 from the second filling insulating layer 262.
Regarding claim 9, Zhang et al. in Fig. 27 disclose the semiconductor memory device of claim 1, further comprising:
a source structure 114 [0139] connected to the first pillar portion 160L, on the first stacked structure; and a bit line 98 connected to the second pillar portion 260L, on the second stacked structure.
Claim(s) 1, 3, 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang et al. US 2023/0099107.
Regarding claim 1, Zhang et al. in Fig. 27 disclose a semiconductor memory device comprising:
a first stacked structure including a plurality of first gate electrodes 246 [0124] sequentially stacked and spaced apart from each other;
a second stacked structure on the first stacked structure, the second stacked structure including a plurality of second gate electrodes 146 [0124] sequentially stacked and spaced apart from each other; and
a channel structure extended in a vertical direction to pass through the first stacked structure 260L [0089] and the second stacked structure 160L [0117], wherein the channel structure includes, a channel layer including a first pillar portion 260L crossing the plurality of first gate electrodes, a second pillar portion 160L crossing the plurality of second gate electrodes, and
a horizontal portion 363 [0096] extended along a plane crossing the vertical direction, the horizontal portion 363 connecting the first pillar portion 260L and the second pillar portion 160L, and
a data storage layer 50 [0172] extending along an outer side of the channel layer.
Regarding claim 3, Zhang et al. in Fig. 27 disclose the semiconductor memory device of claim 1, wherein the plurality of first gate electrodes 246 are stacked on an upper surface of the second stacked structure in a stepwise shape, and the plurality of second gate electrodes 146 are stacked on a lower surface of the first stacked structure in a stepwise shape Fig. 21.
Regarding claim 10, Zhang et al. in Fig. 27 disclose the semiconductor memory device of claim 1, further comprising: a peripheral circuit structure Fig. 1A [0051] including a peripheral circuit substrate 8 [0051] and a peripheral circuit element on the peripheral circuit substrate, wherein the second stacked structure 146 is interposed between the first stacked structure 246 and the peripheral circuit structure Fig. 21.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. as applied to claim 1 above, and further in view of Lee et al. US 2023/0058819.
Regarding claim 4, Zhang et al. disclose the semiconductor memory device of claim 1 but do not expressly disclose wherein the first stacked structure includes a first stack and a second stack, the first stack and the second stack being sequentially stacked on the second stacked structure, each of the first stack and the second stack includes the plurality of first gate electrodes, and a width of the channel structure in the first stack is greater than a width of the channel structure VS_U in the second stack, at a boundary surface between the first stack and the second stack.
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Lee et al. US 2023/0058819
However, Lee et al. in Fig. 28 teach a first stacked structure including a first stack and a second stack, the first stack and the second stack being sequentially stacked on a second stacked structure, each of the first stack and the second stack includes the plurality of first gate electrodes, and a width of the channel structure in the first stack is greater than a width of the channel structure in the second stack, at a boundary surface between the first stack and the second stack (annotated above).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Lee et al. in the memory device of Chen et al. and Zhang et al. to increase the degree of integration of semiconductor devices while providing excellent performance and low price required by consumers.
Claim(s) 6 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. as applied to claims 1 and 5 above, and further in view of Xiao US 2020/0303399.
Regarding claim 6, Zhang et al. disclose the semiconductor memory device of claim 5 but do not expressly disclose wherein the channel structure further includes: a first channel pad connected to one end of the first pillar portion, on the first filling insulating layer; and a second channel pad connected to one end of the second pillar portion, on the second filling insulating layer.
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Xiao US 2020/0303399
However, Xiao in Fig. 2 and [0031]-[0051] teaches a channel structure further includes: (annotated above) a first channel pad connected to one end of a first pillar portion 204A, on a first filling insulating layer; and a second channel pad connected to one end of a second pillar portion 204B, on a second filling insulating layer.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Xiao in the memory device of Zhang for the purpose of increasing device integration and enhancing the reliability and performance.
Regarding claim 8, Zhang et al. disclose the semiconductor memory device of claim 1 but do not expressly disclose the semiconductor device, further comprising: a pad insulating layer interposed between the first stacked structure and the second stacked structure, wherein the channel layer further includes a pad portion extended along a plane crossing the vertical direction in the pad insulating layer, a width of the pad portion is greater than a width of the first pillar portion, and the second pillar portion is connected to the pad portion.
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Xiao US 2020/0303399
However, Xiao Fig. 1A and [0027] teaches a 3D memory device including a pad insulating layer 113, interposed between a first stacked structure 104B [0027] and a second stacked structure 104A [0027], wherein a first semiconductor layer (annotated above) includes a pad portion 110 extending along a plane crossing the vertical direction in the pad insulating layer Fig. 1B, a width of the pad portion is greater than a width of the second semiconductor layer at the plane, and the second semiconductor layer is connected to the pad portion (annotated above).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Xiao in the memory device of Zhang for the purpose of increasing device integration and enhancing the reliability and performance.
Claim(s) 11, 12, 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. US 2020/0058669 in view of Zhang et al. US 2023/0099107.
Regarding claim 11, Chen et al. in Fig. 1 and [0048]-[0093] disclose a semiconductor memory device comprising:
a peripheral circuit structure 222 [0051] including a peripheral circuit substrate 202 [0050] and a peripheral circuit element 206 [0051] on the peripheral circuit substrate 202;
a first stacked structure 242 on the peripheral circuit structure 222, the first stacked structure including a plurality of first gate electrodes 234 sequentially stacked and spaced apart from each other 236;
a second stacked structure 242 between the peripheral circuit structure and the first stacked structure 242, the second stacked structure including a plurality of second gate electrodes 234 sequentially stacked and spaced apart from each other 236;
a channel layer 228 extending in a vertical direction and passing through the first stacked structure 242 and the second stacked structure 242, the channel layer 228 including a first semiconductor layer crossing the plurality of first gate electrodes and a second semiconductor layer crossing the plurality of second gate electrodes;
a data storage layer 229 [0054] including a first dielectric layer interposed between the first stacked structure and the first semiconductor layer, and a second dielectric layer interposed between the second stacked structure and the second semiconductor layer;
a source structure 251 [0056] connected to the first semiconductor layer, on the first stacked structure; and
a bit line 271 [0060] connected to the second semiconductor layer and between the peripheral circuit structure and the second stacked structure,
wherein a width of the first semiconductor layer is reduced as the first semiconductor layer is directed toward the second stacked structure, a width of the second semiconductor layer is reduced as the second semiconductor layer is directed toward the first stacked structure, and the second semiconductor layer includes a horizontal portion, the horizontal portion extending along a plane crossing the vertical direction and connected to the first semiconductor layer.
Chen et al. do not expressly disclose a second stacked structure 242 between the peripheral circuit structure and the first stacked structure 242,
the channel layer 228 including a first semiconductor layer crossing the plurality of first gate electrodes and a second semiconductor layer crossing the plurality of second gate electrodes;
wherein a width of the first semiconductor layer is reduced as the first semiconductor layer is directed toward the second stacked structure, a width of the second semiconductor layer is reduced as the second semiconductor layer is directed toward the first stacked structure, and the second semiconductor layer includes a horizontal portion, the horizontal portion extending along a plane crossing the vertical direction and connected to the first semiconductor layer.
However, Zhang et al. Figs 21-27 and related text teach a vertical semiconductor channel that provides a current path through a vertical NAND device including a second stacked structure 132 [0124] between a peripheral circuit structure and a first stacked structure 232 [0124], the second stacked structure including a plurality of second gate electrodes 146 sequentially stacked and spaced apart from each other 132 Fig. 21;
a channel layer 228 extending in a vertical direction and passing through the first stacked structure 260L [0117] and the second stacked structure 160L[0089], the channel layer 228 including a first semiconductor layer 260L crossing a plurality of first gate electrodes and a second semiconductor layer 160L crossing the plurality of second gate electrodes 146;
wherein a width of the first semiconductor layer 260L is reduced as the first semiconductor layer 260L is directed toward the second stacked structure, a width of the second semiconductor layer 160L is reduced as the second semiconductor layer 160L is directed toward the first stacked structure, and the second semiconductor layer includes a horizontal portion 363 [0096], the horizontal portion 363 extending along a plane crossing the vertical direction and connected to the first semiconductor layer 260L Figs. 25A-Fig. 27.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Zhang et al. in the memory device of Chen et al. for the purpose of improving the GIDL erase performance and reliability of the device.
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Zhang et al. US 2023/0099107
Regarding claim 12, Chen et al. in view of Zhang et al. teach the semiconductor memory device of claim 11. Zhang et al. Fig. 27 teach wherein the horizontal portion 363 is in the first stacked structure (annotated above).
Regarding claim 14, Chen et al. in view of Zhang et al. teach the semiconductor memory device of claim 11. Chen et al. [0054] teach wherein each of the first semiconductor layer 228 and the second semiconductor layer 228 includes a polysilicon (poly-Si) layer.
Regarding claim 15, Chen et al. in view of Zhang et al. teach the semiconductor memory device of claim 11. Zhang et al. Figs 9A-9F teach wherein each of a first dielectric layer 250 and a second dielectric layer 150 includes a tunneling insulating layer 256, 156 [0089], a charge storage layer 254, 154 and a blocking insulating layer 252, 152 that are sequentially stacked on an outer side of the channel layer 260, 160 [0089].
Regarding claim 16, Chen et al. in view of Zhang et al. teach the semiconductor memory device of claim 15. Zhang et al. Figs 9A-9F teach wherein each of the tunnel insulating layer [0091] and the blocking insulating layer includes a silicon oxide layer [0089], and the charge storage layer includes a silicon nitride layer [0090].
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Zhang et al. US 2023/0099107
Regarding claim 18, Chen et al. in view of Zhang et al. teach the semiconductor memory device of claim 11. Zhang et al. in Fig. 21 (annotated above) [0165] teach the semiconductor memory device of claim 11, further comprising: a first contact plug 488 extending in the vertical direction on a side of the first stacked structure; and a second contact plug 488 extending in the vertical direction on a side of the second stacked structure, the second contact plug electrically connecting the peripheral circuit structure and the first contact plug.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. in view of Zhang et al. as applied to claim 11 above, and further in view of Lee et al. US 2023/0058819.
Regarding claim 17, Chen et al. in view of Zhang et al. teach the semiconductor memory device of claim 11 but do not expressly teach the semiconductor memory device, further comprising: a cutting structure extending in a first horizontal direction crossing the vertical direction, the cutting structure cutting the first stacked structure and the second stacked structure, wherein the bit line extends in a second horizontal direction crossing the vertical direction and the first horizontal direction.
However, Lee et al. in Fig. 12 teach a cutting line trench WLC_T extending in a first horizontal direction crossing a vertical direction, the cutting structure WLC_T cutting a first stacked structure BST and a second stacked structure UST, wherein a bit line BL extends in a second horizontal direction crossing the vertical direction and the first horizontal direction (e.g. the bit line BL has a length and a width).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Lee et al. in the memory device of Chen et al. and Zhang et al. to increase the degree of integration of semiconductor devices while providing excellent performance and low price required by consumers.
Claim(s) 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. US 2023/0058819 in view of Zhang et al. US 2023/0099107.
Regarding claim 19, Lee et al. in Figs. 3-33 and [0047]-[0159] teach an electronic system 2000 comprising:
a main board 2001[0154];
a semiconductor memory device 2003 including a peripheral circuit structure and a cell structure Fig. 28 that are sequentially stacked on the main board; and
a controller 2002 on the main board and electrically connected to the semiconductor memory device 2003, 2004, wherein the cell structure includes, a first stacked structure BST [0099] including a plurality of first gate electrodes GSL sequentially stacked and spaced apart from each other 120, a second stacked structure UST between the peripheral circuit structure PERI and the first stacked structure BST Fig. 28, the second stacked structure including a plurality of second gate electrodes SSL sequentially stacked and spaced apart from each other 120, and
a channel structure VS [0067] extending in a vertical direction and passing through the first stacked structure VS_U and the second stacked structure VS_B, and wherein the channel structure includes, a channel layer VS_U including a first pillar portion crossing the plurality of first gate electrodes GSL, a second pillar portion VS_B crossing the plurality of second gate electrodes SSL, and a data storage layer 132_BGI [0090] extending along an outer side of the channel layer VS.
Lee et al. do not expressly disclose a channel structure including a horizontal portion extending along a plane crossing the vertical direction, the horizontal portion connecting the first pillar portion with the second pillar portion.
However, Zhang et al. teach a semiconductor memory device that includes a horizontal portion 363 [0096] extending along a plane crossing the vertical direction, the horizontal portion 363 connecting a first pillar portion 260L and a second pillar portion 160L.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Zhang et al. in the memory device of Lee et al. for the purpose of improving the GIDL erase performance and reliability of the device.
Regarding claim 20, Chen et al. in view of Zhang et al. teach the semiconductor memory device of claim 19. Zhang et al. in Fig. 27 teach wherein a width of the first pillar portion 160L is reduced as the first pillar portion is directed toward the second stacked structure, and a width of the second pillar portion 260L is reduced as the second pillar portion is directed toward the first stacked structure Figs. 25A-Fig. 27.
Allowable Subject Matter
Claims 7 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 7, Zhang et al. in Fig. 27 disclose the semiconductor memory device of claim 1, wherein the data storage layer 50 includes:
a first dielectric layer [0172] including a first tunneling insulating layer 56, a first charge storage layer 54 and a first blocking insulating layer 52 that are sequentially stacked on an outer side of the first pillar portion 160L; and
a second dielectric layer [0172] including a second tunneling insulating layer 56, a second charge storage layer 54 and a second blocking insulating layer 52 that are sequentially stacked on an outer side of the second pillar portion 260L.
The prior art neither anticipates nor renders obvious wherein the second blocking insulating layer separates the first charge storage layer from the second charge storage layer .
Regarding claim 13, the prior art neither anticipates nor renders obvious in the context of the claims, the semiconductor device of claim 11, further comprising: a pad insulating layer interposed between the first stacked structure and the second stacked structure, wherein the first semiconductor layer includes a pad portion extending along a plane crossing the vertical direction in the pad insulating layer, a width of the pad portion is greater than a width of the second semiconductor layer at the plane, and the second semiconductor layer is connected to the pad portion.
Although various prior art references disclose several individual limitations in the claims, these references, and their combinations, neither anticipate nor render obvious the above identified limitation(s), as structured and interrelated in the context of the claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SONYA D MCCALL-SHEPARD whose telephone number is (571)272-9801. The examiner can normally be reached M-F: 8:30 AM-5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Sonya McCall-Shepard/ Primary Examiner, Art Unit 2898
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