Prosecution Insights
Last updated: July 17, 2026
Application No. 18/746,755

SLOPE-COMPENSATION CLAMP CIRCUIT FOR SWITCHING CONVERTER SYSTEM

Non-Final OA §102§103
Filed
Jun 18, 2024
Examiner
TRAN, NGUYEN
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
4m
Est. Remaining
91%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
909 granted / 1088 resolved
+15.5% vs TC avg
Moderate +8% lift
Without
With
+7.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
35 currently pending
Career history
1126
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
84.6%
+44.6% vs TC avg
§102
11.1%
-28.9% vs TC avg
§112
1.9%
-38.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1088 resolved cases

Office Action

§102 §103
DETAILED ACTION 1. This action is in response to the election filed on 5/4/26. Notice of Pre-AIA or AIA Status 2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions 3. Applicant's election with traverse of Species I (claims 1-5) in the reply filed on 5/4/26 is acknowledged. The traversal is on the ground(s) that “Claims 1-15, drawn to a circuit comprising. classified in H02M1/0029;" and "Claims 16-20, drawn to a circuit comprising classified in H02M1/0009." (Restriction at 2.) However, both the species are directed to slope compensation clamp circuits, which is described by H02M1/0029, "Circuits or arrangements for limiting the slope of switching signals, e.g. slew rate." (CPC.)”. This is found persuasive. Therefore, the restriction requirement mailed on 03/02/26 has been withdrawn. Drawings 4. The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, “a current mirror” (in claim 10) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 102 5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 6. Claims 1, 6, 8, and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Floriani et al. (US 20220416657). Regarding claim 1: Floriani et al. disclose a circuit (i.e. figures 2-6) comprising: a switching converter (i.e. 60) comprising at least one switch (i.e. switch of 60) activated in response to a switching signal (i.e. from 94) to provide an inductor current (i.e. IL) through an inductor (i.e. L) to generate an output voltage (i.e. Vout) across a load (i.e. load at Vout); and a switching control system (i.e. controller of figure 3) comprising: a switch controller (i.e. controller of figure 4) configured to generate the switching signal (i.e. from 94) in response to an activation signal (i.e. PWM); and a peak current mode controller (i.e. controller of figure 6) configured to generate the activation signal (i.e. PWM) in response to the inductor current (i.e. IL) being approximately equal (i.e. function of 107) to a slope-compensation current (i.e. current provide to node 216), the slope- compensation current (i.e. current provide to node 216 from 210) comprising a sum (i.e. 210) of a slope current (i.e. Islope) and a compensation current (i.e. from 180) generated via a compensation voltage (i.e. VC), the peak current mode controller (i.e. controller of figure 6) comprising a slope-compensation clamp circuit (i.e. figure 7: circuit 118, 123) configured to clamp the compensation voltage (i.e. VC) to a minimum amplitude that is based on the slope current (i.e. Islope) (i.e. the slop current Islope is provide to the comparator 107 via the summation 210 in order to regulate voltage Vout. Figures 2-3 show voltage Vout is provide to the diagnosis 510 to generate signal DIAG to the processor 500. The processor 500 generate the CONT signal to the register 99 to provide signal PAR to control the clamp circuit of figure 7. Therefore, clamp the compensation voltage VC is based on the slope current Islope) (i.e. ¶ 82-106). Regarding claim 6: (i.e. figures 2-6) wherein the peak current mode controller (i.e. controller of figure 6) further comprises a feedback error amplifier (i.e. 110) configured to generate the compensation voltage (i.e. VC) on a compensation terminal based on an amplitude of a feedback voltage (i.e. FB) associated with the output voltage (i.e. Vout) of the switching converter relative to a predefined reference voltage (i.e. Vref), wherein the slope-compensation clamp circuit (i.e. figure 7: circuit 118, 123) is coupled (i.e. electrically coupled) to the compensation terminal to set the minimum amplitude of the compensation voltage (i.e. VC) (i.e. ¶ 82-106). Regarding claim 8: (i.e. figures 2-6) wherein the slope-compensation clamp circuit (i.e. figure 7: circuit 118, 123) is configured to clamp the compensation voltage (i.e. VC) to the minimum amplitude during a pulse frequency modulation (PFM) mode of the switching converter (i.e. ¶ 82-106) (i.e. ¶ 156). Regarding claim 11: Floriani et al. disclose a circuit (i.e. figures 2-6) comprising: a comparator (i.e. 92) configured to generate an activation signal (i.e. PWM) in response to an inductor current (i.e. IL) of a switching converter (i.e. 60) being equal to a slope-compensation current (i.e. current provide to node 216 from 210), the slope-compensation current (i.e. current provide to node 216 from 210) comprising a sum (i.e. 210) of a slope current (i.e. Islope) and a compensation current (i.e. from 180) generated via a compensation voltage (i.e. VC); a feedback error amplifier (i.e. 110) configured to generate the compensation voltage (i.e. VC) based on an amplitude of a feedback voltage (i.e. FB) associated with an output voltage (i.e. Vout) of the switching converter (i.e. 60) relative to a predefined reference voltage (i.e. Vref); a slope generator (i.e. 200) configured to generate the slope current (i.e. Islope); and a slope-compensation clamp circuit (i.e. figure 7: circuit 118, 123) configured to clamp the compensation voltage (i.e. VC) to a minimum amplitude based on the slope current (i.e. Islope) (i.e. the slop current Islope is provide to the comparator 107 via the summation 210 in order to regulate voltage Vout. Figures 2-3 show voltage Vout is provide to the diagnosis 510 to generate signal DIAG to the processor 500. The processor 500 generate the CONT signal to the register 99 to provide signal PAR to control the clamp circuit of figure 7. Therefore, clamp the compensation voltage VC is based on the slope current Islope) (i.e. ¶ 82-106). Claim Rejections - 35 USC § 103 7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 8. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Floriani et al. (US 20220416657) in view of Chen et al. (US 2020389091). Regarding claim 9: (i.e. figures 2-6) wherein the peak current mode controller further (i.e. controller of figure 6) comprises: a slope generator (i.e. 200) configured to generate the slope current (i.e. Islope); a summation (i.e. 210) component configured to generate the slope-compensation current (i.e. from 210); and a comparator (i.e. 92) configured to compare the inductor current (i.e. IL) with the slope-compensation current (i.e. current provide to node 216 from 210) to generate the activation signal (i.e. PWM), but does not specifically disclose based on subtracting the slope current from the compensation current associated with the compensation voltage. Chen et al. disclose a voltage converter (i.e. figure 6) comprising based on subtracting the slope current (i.e. Islp) from the compensation current (i.e. Icon) associated with the compensation voltage (i.e. from 630, 112) (i.e. ¶ 42). Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Floriani et al.’s invention with the converter as disclose by Chen et al. to improvements in current-mode control of voltage converter circuits. 9. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Floriani et al. (US 20220416657) in view of Chen et al. (US 2020389091) and further in view of Romeo (US 20210099082). Regarding claim 10: Floriani et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose the slope generator comprises a current mirror configured to provide the slope current to the slope-compensation clamp circuit. Romeo discloses a voltage converter (i.e. figures 2 and 6) comprising the slope generator comprises a current mirror (i.e. 234, ¶ 37) configured to provide the slope current (i.e. Iramp) to the slope-compensation clamp circuit (i.e. 180, 646). Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Floriani et al.’s invention with the converter as disclose by Romeo to achieve accurate current limitation in clocked applications without subharmonic oscillation. Allowable Subject Matter 10. Claims 16-20 are allowed. The following is an examiner’s statement of reasons for allowance: In regards to claim 16, the prior art fails to disclose a slope-compensation error amplifier having a first input, a second input, and an output, the first input of the slope-compensation error amplifier being coupled to the switch output, the second input of the slope-compensation error amplifier being coupled to a compensation terminal that is adapted to receive a compensation voltage for slope-compensation control of the switching converter system; and a regulation transistor device having a first input, a second input, and an output, the first input of the regulation transistor device being coupled to the output of the slope-compensation error amplifier, the second input of the regulation transistor device being adapted to receive an input voltage, and the output of the regulation transistor device being coupled to the compensation terminal. 11. Claims 2-5, 7, and 12-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion 12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NGUYEN TRAN whose telephone number is (571)270-1269. The examiner can normally be reached Flex: M-F 8-7. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at 571-272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Nguyen Tran/ Primary Examiner, Art Unit 2838
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Prosecution Timeline

Jun 18, 2024
Application Filed
May 20, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
91%
With Interview (+7.6%)
2y 5m (~4m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1088 resolved cases by this examiner. Grant probability derived from career allowance rate.

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