DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 6, 11-12 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2020/0162091) and further in view of Frohlich (US 2023/0046938) and Thomsen et al. (USP 9,866,238).
Regarding claim 1, Huang discloses calibration DAC architecture in figure 1 that teaches: a digital-to-analog converter (DAC) (110); an incremental analog-to-digital converter (IADC) (130) having a first input (V1) coupled to a first output of the DAC (V1); and a controller(140) coupled to the DAC (110 via output of 140, Din1/Din2) and the IADC (130), wherein the controller (140) is configured to: determine a direct current (DC) offset (D_OS) associated with the DAC (110) using the IADC (130); and control a mission-mode digital input signal (Din1/Din2) of the DAC based on the DC offset (D_OS) (See figure 1 and its descriptions for further details).
Huang fails to teach or suggest using IADC (incrementally ADC) instead of using ADC.
However, Frohlich discloses an DAC architecture that teach and/or suggest using incrementally ADC in Digital to Analog Conversion circuit (see para. 0009, line 1), where large dynamic range analog signals need to be converted into the digital domain (see para. 0003).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to integrated incrementally ADC into Huang’s disclosure for circuit requires large dynamic range analog signal to be converted into digital domain.
Regarding claim 2, Huang further teaches: switch circuit (120, polarity swapping is functioning just like a switch circuitry) coupled to the first output (V1/V2) of the DAC (110) (see figure 1 and its descriptions).
Regarding claim 6, Thomsen teaches in figure 1 an IADC (100) configure to include sigma delta modulator (102) (see col. 4, lines 20-40) for performing analog to digital conversion (see figure 1 and its description).
Regarding claim 11, Claim 11 is similar to claim 1 in method format. Therefore, claim 11 is rejected as well as rejected in claim 1, such as: Huang discloses calibration DAC architecture in figure 1 that teaches: a digital-to-analog converter (DAC) (110); an incremental analog-to-digital converter (IADC) (130) having a first input (V1) coupled to a first output of the DAC (V1); and a controller(140) coupled to the DAC (110 via output of 140, Din1/Din2) and the IADC (130), wherein the controller (140) is configured to: determine a direct current (DC) offset (D_OS) associated with the DAC (110) using the IADC (130); and control a mission-mode digital input signal (Din1/Din2) of the DAC based on the DC offset (D_OS) (See figure 1 and its descriptions for further details).
Huang fails to teach or suggest using IADC (incrementally ADC) instead of using ADC.
However, Frohlich discloses an DAC architecture that teach and/or suggest using incrementally ADC in Digital to Analog Conversion circuit (see para. 0009, line 1), where large dynamic range analog signals need to be converted into the digital domain (see para. 0003).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to integrated incrementally ADC into Huang’s disclosure for circuit requires large dynamic range analog signal to be converted into digital domain.
Regarding claim 12, Claim 12 is similar to claim 2 in method format. Therefore, claim 12 is rejected as well as rejected in claim 2, such as: Huang further teaches: switch circuit (120, polarity swapping is functioning just like a switch circuitry) coupled to the first output (V1/V2) of the DAC (110) (see figure 1 and its descriptions).
Regarding claim 20, Huang discloses calibration DAC architecture in figure 1 that teaches: a digital-to-analog converter (DAC) (110) including a first output (V1) and a second output (V2); and an incremental analog-to-digital converter (IADC) (130) including a switch circuit (120, polarity swapping circuit is functioning like switching circuit), a first input (V1) selectively coupled to the first output of the DAC (110) or the second output (V2) of the DAC (110) via the switch circuit (120), and a second input (V2) selectively coupled to the first output (V1) of the DAC (110) or the second output (V2) of the DAC (110) via the switch circuit (120) (see figure 1 and its description for further details).
Huang fails to teach or suggest using IADC (incrementally ADC) instead of using ADC.
However, Frohlich discloses an DAC architecture that teach and/or suggest using incrementally ADC in Digital to Analog Conversion circuit (see para. 0009, line 1), where large dynamic range analog signals need to be converted into the digital domain (see para. 0003).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to integrated incrementally ADC into Huang’s disclosure for circuit requires large dynamic range analog signal to be converted into digital domain.
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein the switch circuit is configured to: in a non-flip mode, couple the first output of the DAC to the first input of the IADC and a second output of the DAC to a second input of the IADC; and in a flip mode, couple the first output of the DAC to the second input of the IADC and the second output of the DAC to the first input of the IADC.
Claim 4 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein: the IADC is configured to: generate a non-flip-mode digital output signal based on a first output current of the DAC while the switch circuit is configured in the non-flip mode; and generate a flip-mode digital output signal based on a second output current of the DAC while the switch circuit is configured in the flip mode; and the controller is configured to determine the DC offset based on the non-flip-mode digital output signal and the flip-mode digital output signal.
Claim 5 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein the controller is configured to set a calibration-mode digital input signal of the DAC to a middle code, and wherein the IADC is configured to generate the non-flip-mode digital output signal and the flip-mode digital output signal while the calibration-mode digital input signal of the DAC is set to the middle code.
Claim 7 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein: the IADC is configured to be coupled to another DAC after the DC offset associated with the DAC is determined; and the controller is configured to determine another DC offset associated with the other DAC using the IADC after the IADC is coupled to the other DAC.
Claim 8 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: a current source circuit configured to: sink a first current from a first node coupled to the first input of the IADC; and sink a second current from a second node coupled to a second input of the IADC.
Claim 9 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein an amount of the first current is the same as an amount of the second current.
Claim 10 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein: the controller is configured to set a calibration-mode digital input signal of the DAC to a middle code; the IADC is configured to generate a first digital output signal based on a first output current of the DAC while the calibration-mode digital input signal is set to the middle code; the controller is configured to set the calibration-mode digital input signal of the DAC to the middle code minus one; the IADC is configured to generate a second digital output signal based on a second output current of the DAC while the calibration-mode digital input signal is set to the middle code minus one; and the controller is configured to determine the DC offset based on the first digital output signal and the second digital output signal.
Claim 13 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: generating, via the IADC, a non-flip-mode digital output signal based on the first output current of the DAC while the switch circuit is configured in a non-flip mode; and generating, via the IADC, a flip-mode digital output signal based on a second output current of the DAC while the switch circuit is configured in a flip mode, wherein the DC offset is determined based on the non-flip-mode digital output signal and the flip-mode digital output signal.
Claim 14 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: in the non-flip mode, coupling a first output of the DAC to a first input of the IADC and a second output of the DAC to a second input of the IADC using the switch circuit; and in the flip mode, coupling the first output of the DAC to the second input of the IADC and the second output of the DAC to the first input of the IADC using the switch circuit.
Claim 15 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: setting the calibration-mode digital input signal of the DAC to a middle code, wherein the non-flip-mode digital output signal and the flip-mode digital output signal are generated while the calibration-mode digital input signal of the DAC is set to the middle code.
Claim 16 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: coupling the IADC to another DAC after the DC offset associated with the DAC is determined; and determining another DC offset associated with the other DAC using the IADC after the IADC is coupled to the other DAC.
Claim 17 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: sinking a first current from a first node coupled to a first input of the IADC; and sinking a second current from a second node coupled to a second input of the IADC, wherein the first digital output signal is generated while the first current and the second current are being sunk from the first input and the second input of the IADC, respectively.
Claim 18 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein an amount of the first current is the same as an amount of the second current.
Claim 19 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: setting the calibration-mode digital input signal of the DAC to a middle code, wherein the first digital output signal is generated based on the first output current of the DAC while the calibration-mode digital input signal is set to the middle code; setting the calibration-mode digital input signal of the DAC to the middle code minus one; and generating a second digital output signal based on a second output current of the DAC while the calibration-mode digital input signal is set to the middle code minus one, wherein the DC offset is determined based on the first digital output signal and the second digital output signal.
Cited References
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Cited references are related to instant application subject matters.
Conclusion
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/LAM T MAI/Primary Examiner, Art Unit 2845