DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s Remarks/Arguments filed on May 22nd, 2026, have been carefully considered.
Claims 1, 4, 8, 11, 15, and 17 have been amended.
No claims have been added or canceled.
Claims 1-20 are currently pending in the instant application.
Claim Interpretation
The examiner has determined the claims merely require determining a physical block of memory using the first portion of the LBA and combines the second part of the LBA as an offset into the physical block and thus reads on the plurality of PBAs, since data can be smaller than the physical block, multiple addresses can be offset within the same block. If the applicant wants the claims to be interpreted differently the examiner suggests the applicant provide exact locations for support in the specification as to how the specification teaches a different interpretation.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 5-10, 12-16, 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. [US2006/0161725] in view of Feldman et al. [US2009/0002863] further in view of Kuo et al. [US2021/0397375]. Lee teaches a multiple function flash memory system. Feldman teaches system and method of monitoring data operations at a data storage device. Kuo teaches memory control method, memory storage device and memory control circuit unit.
Regarding claims 1, 8, and 15, Lee teaches a method [Lee abstract “a system and method for implementing a flash memory system…”] comprising:
maintaining a logical-to-physical (L2P) table that maps a plurality of logical block addresses (LBAs) to a plurality of physical blocks [Lee paragraph 0043, all lines “…The main memory 412 is random access memory (RAM) and stores the address translation table 420, which keeps track of valid copies of data, by mapping LUNs together with logical block addresses (LBAs), which are mapped to physical address blocks (PBAs)…”],
Lee fails to explicitly teach wherein an entry of the L2P table maps two or more of the plurality of LBAs to one physical block.
However, Feldman does teach wherein an entry of the L2P table maps two or more of the plurality of LBAs to one physical block [Feldman paragraph 0032, last lines “…the table 302 may associate multiple LBAs to a single PBA, or a single LBA to multiple PBAs, or both...”].
Lee and Feldman are analogous arts in that they both deal with address translation in a memory system.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lee’s L2P conversion method with Feldman’s teaching that it was well known in the art that multiple logical address can be resolved to a single physical block for the benefit of expanding the memory address range over the actual size limit of the physical addressable range and thus improve memory system performance.
receiving a memory operation including an LBA [Lee paragraph 0027, first lines “…During normal-mode operation…” and paragraph 0049, first lines “…In operation, the address translation table 420 maps the LUNs 500-506 and the LBAs from the host to the PBAs…”];
Lee and Feldman fail to explicitly teach responsive to determining that the memory operation is not a maintenance operation.
However, Kuo does teach responsive to determining that the memory operation is not a maintenance operation [Kuo figure 16, feature S1604 “Receiving a mapping table for updating management units accessed by a host…” and paragraph 0092, firs lines “…a trim command is received in step S1602, or a mapping table for updating management units accessed by a host system is received in step S1604…”(The examiner has determined that it was known in the art to receive or not receive a maintenance operation, Kuo clearly shows a teaching of not receiving a maintenance operation.)].
Lee, Feldman, and Kuo are analogous arts in that they all deal with improving memory system performance.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lee and Feldman’s L2P mapping with Kuo’s teachings of determining a memory maintenance operation for the benefit of reducing the number of times the same L2P mapping is read during data merge operations thus improving the execution efficiency of the memory storage device [Kuo paragraph 0010, last half “…the number of times that the same logic to physical mapping table is read multiple times during the data merging operation can be reduced to improve the execution efficiency of the data merging operation, thereby increasing the system performance of the memory storage device…”].
Lee teaches splitting the LBA into a first portion and a second portion [Lee figure 6A, feature 606 “LBAblock” and 608 “LBALSB”];
wherein the first portion references a first entry of the L2P table [Lee figure 7, feature 712 “Use LBAtbl as index to get PBAtbl from “SRAM translation table”] and wherein the second portion is an offset to reference a physical block address (PBA) of a plurality of PBAs inside a physical block of the first entry [Lee paragraph 0052, last lines “…The six MSBs of the LBA.sub.LSB are concatenated with the PBA.sub.tbl to construct the PBA address for the flash memory. The two LSBs of the LBA.sub.LSB are used to access 512 bytes out of the 2K-page flash. In this case, 6-bit PBA.sub.LSB equals 6-bit MSB from 8-bit LBA.sub.LSB…” and paragraph 0059, middle lines “…If less than 512 bytes, the page offset value will be equal to the 2 LSBs bits of the LBA.sub.LSB, in a step 720, and the 6-bit PBA.sub.LSB is equal to 6 most significant bit (MSB) bits of the LBA.sub.LSB, in a step 722…”]; and
performing the memory operation at the PBA inside the physical block [Lee paragraph 0060, first lines “…it is determined if the flash memory access is a read operation or a write operation, in a step 730. If the operation is a read operation, data is read from the PBA page, in a step 732…”]; and
Kuo teaches responsive to determining that the memory operation is a maintenance operation [Kuo paragraph 0089, middle lines “…when determining that the trim command is received…” and Figure 16, S1602 “Receiving a trim command” (The examiner has determined that a trim command reads on a maintenance operation. And that Kuo shows that it was known in the art to determine what is received between a maintenance operation or not a maintenance operation)],
updating the L2P table [Kuo paragraph 0089, last lines “…update a mapping of the indicated logical addresses to a null value in the logical to physical mapping table, so as to indicate that the physical units originally mapped to the indicated logical addresses no longer include the valid data…”].
Regarding claims 2, 9, and 16, Lee teaches the first portion of the LBA includes one or more most significant bits of the LBA [Lee paragraph 0059, middle lines “…and the 6-bit PBA.sub.LSB is equal to 6 most significant bit (MSB) bits of the LBA.sub.LSB…”].
Regarding claims 3 and 10, as per claim 1, Lee teaches the second portion of the LBA includes one or more least significant bits [Lee paragraph 0051, last lines “…The offset 616 is provided by the lower six bits (LSBs) of the LBA…”].
Regarding claims 5, 12, and 18, as per claim 1, Lee teaches moving data written to the plurality of PBAs inside the physical block to a second plurality of PBAs inside a second physical block using a single command [Lee paragraph 0064, middle lines “…A second LUN base address register 804 stores values for the LUN 1 (associated with a security partition) has a LUN counter value of 1, a FAT 16 file structure, a 01 type file system type, a security attribute, results in 01/01/1 code. A third LUN base address register 806 stores values for another LUN 1 can also be associated with a public partition…”].
Regarding claims 6, 13, and 19, as per claim 1, Lee teaches updating the L2P table by remapping a set of one or more most significant bits of the LBA to the second physical block [Lee paragraph 0060, middle lines “…If occupied, a new empty block is found and updated with the new PBA value to address translation table, in a step 736. As such, a new PBA page is calculated based on the new PBA.sub.tbl…”].
Regarding claims 7, 14, and 20, as per claim 1, Lee teaches loading the L2P table to a cache in volatile memory, wherein the loaded L2P table is a complete copy of the L2P table as stored in non-volatile memory [Lee paragraph 0043, first lines “…The main memory 412 is random access memory (RAM) and stores the address translation table 420…” and paragraph 0041, middle lines “…up to four copies (for purposes such as copying, backup, etc.) of the control information in the reserved area are preserved to facilitate erase-before-write operations of the flash memory…”].
Claims 4, 11, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. [US2006/0161725] in view of Feldman et al. [US2009/0002863] in view of Kuo et al. [US2021/0397375] further in view of McGlaughlin et al. [US2019/0303283]. Lee teaches a multiple function flash memory system. Feldman teaches system and method of monitoring data operations at a data storage device. Kuo teaches memory control method, memory storage device and memory control circuit unit. McGlaughlin teaches memory management.
Regarding claims 4, 11, and 17, as per claim 1, Lee fails to explicitly teaches performing the memory operation at the PBA inside the physical block further comprises: performing a write in-place operation to write data at the PBA; and determining not to update the L2P table responsive to the write in-place operation.
However, McGlaughlin teaches the memory operation at the PBA inside the physical block further comprises: performing a write in-place operation to write data at the PBA [McGlaughlin paragraph 0018, middle lines “…the present disclosure can include write in place memory, in which multiple writes to cells mapped by a particular logical address can performed without having to change the physical address to which the particular logical address maps…”]. and determining not to update the L2P table responsive to the write in-place operation [McGlaughlin paragraph 0018, last half lines “…without having to change the physical address to which the particular logical address maps…” and paragraph 0033, last lines “…the write process 331 and/or read process 332 can involve accessing a PMUA table 340 and taking particular actions based on whether the value of an activity counter field of the corresponding entry has reached one or more threshold levels…”].
Lee, Feldman, Kuo, and McGlaughlin are analogous arts in that they all deal improving memory management.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lee, Feldman, and Kuo with McGlaughlin’s use of write in-place writing techniques for the benefit of increasing the useful lifetime by effectively and efficiently handling wear leveling [McGlaughlin paragraph 0018, last lines “…managing memory in accordance with embodiments described herein can increase the useful lifetime of a system by effectively and efficiently handling wear leveling…”].
Response to Arguments
Applicant’s arguments with respect to claims 1, 8, and 15 have been considered but are moot in view of new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC CARDWELL whose telephone number is (571)270-1379. The examiner can normally be reached on Monday - Friday 10-6pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached on (571) 272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC CARDWELL/Primary Examiner, Art Unit 2139
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