Prosecution Insights
Last updated: October 27, 2026
Application No. 18/747,108

METHODS AND APPARATUS TO IMPLEMENT DUAL-DRIVE REDUNDANT OUTPUT STRUCTURES

Final Rejection §103
Filed
Jun 18, 2024
Examiner
PAN, YUHUI R
Art Unit
2116
Tech Center
2100 — Computer Architecture & Software
Assignee
Emerson Electric Co.
OA Round
2 (Final)
83%
Grant Probability
Favorable
3-4
OA Rounds
2m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
517 granted / 622 resolved
+28.1% vs TC avg
Strong +22% interview lift
Without
With
+22.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
27 currently pending
Career history
648
Total Applications
across all art units

Statute-Specific Performance

§101
6.3%
-33.7% vs TC avg
§103
54.2%
+14.2% vs TC avg
§102
22.7%
-17.3% vs TC avg
§112
12.5%
-27.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 622 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Allowable Subject Matter Claim 22 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Response to Amendment Applicant’s arguments with respect to claim(s) 1, 8, 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1 – 7, 16 – 21 are rejected under 35 U.S.C. 103 as being unpatentable over Judkinset al. US 2024/0161713 (hereinafter Judkins) in view of Hasan US 2013/0002233 (hereinafter Hasan). Regarding claim 1, Judkins teaches: an apparatus to provide a dual-drive redundant output in a control system, the apparatus comprising: interface circuitry; machine-readable instructions; and at least one processor circuit to be programmed by the machine-readable instructions to: at a first state: enable a first source electrical current path corresponding to first source electrical current regulator circuitry in circuit with a first terminal to be coupled to a field device (Fig. 6A - - normal operation mode, first I/O module 100% source); and enable a first sink electrical current path corresponding to first sink electrical current regulator circuitry in circuit with a second terminal to be coupled to the field device (Fig. 6A - - normal operation mode, first I/O module 50% sink); at a second state, enable a second sink electrical current path corresponding to second sink electrical current regulator circuitry in circuit with the second terminal (Fig. 6A - - normal operation mode, second I/O module 50% sink); the first sink electrical current path and the second sink electrical current path to be concurrently enabled in the second state (Fig. 6A - - normal operation mode, first I/O module 50% sink; second I/O module 50% sink; thus both sink are concurrently enabled); and at a third state, disable the first sink electrical current path (Fig. 6A - - fault detected mode, first I/O module 0% sink). But Judkins does not explicitly teach: at a third state, disable the first sink electrical current path while the first source electrical current path remains enabled. However, Hasan teaches: at a third state, disable the first sink electrical current path while the first source electrical current path remains enabled (Fig. 4, Abstract - - “selectively enable the current source and disable the current sink during a first phase of a load”). Judkins and Hasan are analogous art because they are from the same field of endeavor. They all relate to control system. Therefore before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the above method, as taught by Judkins, and incorporating enable the current source and disable the current sink, as taught by Hasan. One of ordinary skill in the art would have been motivated to do this modification in order to detect a load, as suggested by Hasan (Abstract). Claim 16 is substantially similar to claim 1 and is rejected for the same reasons and rationale as above. Regarding claim 2, the combination of Judkins and Hasan teaches all the limitations of the base claims as outlined above. Judkins further teaches: one or more of the at least one processor circuit is to enable the second sink electrical current path after detecting a presence of at least one of second source electrical current regulator circuitry or the second sink electrical current regulator circuitry ([0056] - - the I/O controller set up output power on each channel, thus it enables sink path of second I/O module). Claim 17 is substantially similar to claim 2 and is rejected for the same reasons and rationale as above. Regarding claim 3, the combination of Judkins and Hasan teaches all the limitations of the base claims as outlined above. Judkins further teaches: the third state corresponds to an asymmetric drive state in which a first input-output card that includes the first source electrical current regulator circuitry is to source electrical current to the field device and a second input-output card that includes the second sink electrical current regulator circuitry is to sink the electrical current from the field device (Fig. 6, - - normal operation mode, first I/O module 100% source, second I/O module 50% sink). Claim 18 is substantially similar to claim 3 and is rejected for the same reasons and rationale as above. Regarding claim 4, the combination of Judkins and Hasan teaches all the limitations of the base claims as outlined above. Judkins further teaches: the first source electrical current regulator circuitry and the first sink electrical current regulator circuitry are on a first input-output card, and the second sink electrical current regulator circuitry in a second input-output card (Fig.3 - - first I/O module is a first I/O card; second I/O module is a second I/O card). Regarding claim 5, the combination of Judkins and Hasan teaches all the limitations of the base claims as outlined above. Judkins further teaches: one or more of the at least one processor circuit is to determine an error has occurred at the field device based on electrical current flow corresponding to at least one of the first terminal or the second terminal ([0057], [0062] - - detecting a fault based on the current at each channel). Claim 19 is substantially similar to claim 5 and is rejected for the same reasons and rationale as above. Regarding claim 6, the combination of Judkins and Hasan teaches all the limitations of the base claims as outlined above. Judkins further teaches: first communication circuitry to provide a signal to the first source electrical current path, the signal to be communicated to the field device ([0042] - - the industrial controller 300 communicates with the industrial control equipment 310 through I/o modules; the industrial control equipment 310 is field device). Claim 20 is substantially similar to claim 6 and is rejected for the same reasons and rationale as above. Regarding claim 7, the combination of Judkins and Hasan teaches all the limitations of the base claims as outlined above. Judkins further teaches: the signal is to include information specifying a type of the field device ([0055] - - user may configure each channel as an Analog Output type). Regarding claim 21, the combination of Judkins and Hasan teaches all the limitations of the base claims as outlined above. Judkins further teaches: one or more of the at least one processor circuit is to, in the second state, determine an error has occurred when an electrical current through at least one of the first sink electrical current path or the second sink electrical current path is not substantially half of an electrical current to be sourced by the first source electrical current regulator circuitry (Fig. 6A - - normal operation mode, first I/O module 50% sink; second I/O module 50% sink; [0015] - - a fault occurs when the current is not 1.5+/- tolerance). Claims 8, 9, 12 – 14 are rejected under 35 U.S.C. 103 as being unpatentable over Judkinset al. US 2024/0161713 (hereinafter Judkins) in view of “WIKIPEDIA, "H-bridge," retrieved from <https://en.wikipedia.org/wiki/H-bridge> on May 2, 2024, 5 pages” (hereinafter WIKIPEDIA) and JP 2021076803 (hereinafter Tppoan). Regarding claim 8, Judkins teaches: an apparatus to provide a dual-drive redundant output in a control system, the apparatus comprising: source electrical current regulator circuitry having an output (Fig. 6A - - first I/O module source current); sink electrical current regulator circuitry having an input coupled to a second device interface terminal, and having an output, the second device interface terminal to be coupled to the field device in the control system (Fig. 6A - - first I/O module sink current; Fig. 3 - - industrial control equipment is a field device); and second switch circuitry having a first terminal coupled to the output of the sink electrical current regulator circuitry, and having a second terminal coupled to ground. But Judkins does not explicitly teach: first switch circuitry having a first terminal coupled to the output of the source electrical current regulator circuitry, and having a second terminal coupled to a first device interface terminal, the first device interface terminal to be coupled to a field device in the control system; second switch circuitry having a first terminal coupled to the output of the sink electrical current regulator circuitry, and having a second terminal coupled to ground. However, WIKIPEDIA teaches: first switch circuitry having a first terminal coupled to the output of the source electrical current regulator circuitry, and having a second terminal coupled to a first device interface terminal, the first device interface terminal to be coupled to a field device in the control system; second switch circuitry having a first terminal coupled to the output of the sink electrical current regulator circuitry, and having a second terminal coupled to ground (Page 1 - - S1 is a first switch , S2 is a second switch). Judkins and WIKIPEDIA are analogous art because they are from the same field of endeavor. They all relate to control system. Therefore before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the above method, as taught by Judkins, and incorporating H-bridge, as taught by WIKIPEDIA. One of ordinary skill in the art would have been motivated to do this modification in order to improve feasibility and effectiveness of a controller, as suggested by WIKIPEDIA (Abstract). But the combination of Judkins and WIKIPEDIA does not explicitly teach: a microcontroller to determine a fault based on a comparison of a first electrical current and a second electrical current, the first electrical current to be output by the source electrical current regulator circuitry, the second electrical current to flow through the sink electrical current regulator circuitry. However, Tppoan teaches: a microcontroller to determine a fault based on a comparison of a first electrical current and a second electrical current, the first electrical current to be output by the source electrical current regulator circuitry, the second electrical current to flow through the sink electrical current regulator circuitry (Page 2 - - “A difference detection circuit that detects the difference between the source current and the sink current, An abnormality detecting means having a leakage determination circuit for detecting an leakage by comparing the detected difference value with a threshold value for the leakage determination.”). Judkins, WIKIPEDIA and Tppoan are analogous art because they are from the same field of endeavor. They all relate to control system. Therefore before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the above method, as taught by the combination of Judkins and WIKIPEDIA, and incorporating detecting difference between the source current and the sink current, as taught by Tppoan. One of ordinary skill in the art would have been motivated to do this modification in order to detect leakage, as suggested by Tppoan (Page 2). Regarding claim 9, the combination of Judkins, WIKIPEDIA and Tppoan teaches all the limitations of the base claims as outlined above. Tppoan further teaches: source electrical current measurement circuitry coupled to the source electrical current regulator circuitry, the source electrical current measurement circuitry to measure the first electrical current; and sink electrical current measurement circuitry coupled to the sink electrical current regulator circuitry, the sink electrical current measurement circuitry to measure the second electrical current (Page 2- - A source current detection circuit that detects the source current; a sink current detection circuit that detects the sink current). Judkins, WIKIPEDIA and Tppoan are combinable for the same rationale as set forth. Regarding claim 12, the combination of Judkins, WIKIPEDIA and Tppoan teaches all the limitations of the base claims as outlined above. Judkins further teaches: the microcontroller is to determine an error has occurred at the field device based on an electrical current measurement corresponding to at least one of the first device interface terminal or the second device interface terminal ([0058] - - detection of power balance faults based on detected current values). Regarding claim 13, the combination of Judkins, WIKIPEDIA and Tppoan teaches all the limitations of the base claims as outlined above. Judkins further teaches: the source electrical current regulator circuitry and the sink electrical current regulator circuitry are on a first input-output card (Fig. 3 - - first I/O module is a first input-output card), the apparatus including a second input-output card (Fig. 3 - - second I/O module is a second input-output card), the second input-output card including: second source electrical current regulator circuitry having an output (Fig. 6A - - normal operation mode, second I/O module 0% source); second sink electrical current regulator circuitry having an input coupled to the second device interface terminal, and having an output (Fig. 6A - - normal operation mode, second I/O module 50% sink); and WIKIPEDIA teaches: third switch circuitry having a first terminal coupled to the output of the second source electrical current regulator circuitry, and having a second terminal coupled to the first device interface terminal; fourth switch circuitry having a first terminal coupled to the output of the second sink electrical current regulator circuitry, and having a second terminal coupled to ground (Page 1 - - S3 is a third switch , S4 is a fourth switch). Judkins, WIKIPEDIA and Tppoan are combinable for the same rationale as set forth. Regarding claim 14, the combination of Judkins, WIKIPEDIA and Tppoan teaches all the limitations of the base claims as outlined above. Judkins further teaches: the first input-output card and the second input-output card are to operate in an asymmetric drive state in which the source electrical current regulator circuitry of the first input-output card is to source electrical current to the field device and the second sink electrical current regulator circuitry of the second input-output card is to sink the electrical current from the field device (Fig. 6, - - normal operation mode, first I/O module 100% source, second I/O module 50% sink). Claims 15 is rejected under 35 U.S.C. 103 as being unpatentable over Judkinset al. US 2024/0161713 (hereinafter Judkins) in view of “WIKIPEDIA, "H-bridge," retrieved from <https://en.wikipedia.org/wiki/H-bridge> on May 2, 2024, 5 pages” (hereinafter WIKIPEDIA) and JP 2021076803 (hereinafter Tppoan) and further in view of KN et al. US 2018/0343763 (hereinafter KN). Regarding claim 15, the combination of Judkins, WIKIPEDIA and Tppoan teaches all the limitations of the base claims as outlined above. But the combination of Judkins, WIKIPEDIA and Tppoan does not explicitly teach: a first current back-feed prevention component having an input and an output, the second terminal of the first switch circuitry coupled to the first device interface terminal via the first current back-feed prevention component based on the input of the first current back-feed prevention component coupled to the second terminal of the first switch circuitry and the output of the first current back-feed prevention component coupled to the first device interface terminal. However, KN teaches: a first current back-feed prevention component having an input and an output, the second terminal of the first switch circuitry coupled to the first device interface terminal via the first current back-feed prevention component based on the input of the first current back-feed prevention component coupled to the second terminal of the first switch circuitry and the output of the first current back-feed prevention component coupled to the first device interface terminal (Fig. 3, [0041] - - diodes 308, 314 are back-feed prevention component). Judkins, WIKIPEDIA, Tppoan and KN are analogous art because they are from the same field of endeavor. They all relate to control system. Therefore before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the above method, as taught by the combination of Judkins, WIKIPEDIA and Tppoan, and incorporating back-feed prevention component, as taught by KN. One of ordinary skill in the art would have been motivated to do this modification in order to provide protection, as suggested by KN ([0041]). Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to YUHUI R PAN whose telephone number is (571)272-9872. The examiner can normally be reached Monday-Friday 8AM-5PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kenneth Lo can be reached at (571) 272-9774. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /YUHUI R PAN/Primary Examiner, Art Unit 2116
Read full office action

Prosecution Timeline

Jun 18, 2024
Application Filed
Jul 01, 2026
Non-Final Rejection mailed — §103
Sep 28, 2026
Response Filed
Oct 07, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
83%
Grant Probability
99%
With Interview (+22.4%)
2y 7m (~2m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 622 resolved cases by this examiner. Grant probability derived from career allowance rate.

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