DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to RCE filed on 06/16/2026. Claims 1-20 have been examined and are pending in this application.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/16/2026 has been entered.
Response to Arguments
Applicant’s arguments, filed 05/14/2026, with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
A new reference NPL Du et al. “A Novel Program Suspend Scheme for Improving the Reliability of 3D NAND Flash Memory”, Journal of the Electron Device Society, Volume 10, 2022, is cited in this Office Action necessitated by the amendment.
In view of the new reference, independent claims 1, 8, and 15 are not in a condition for allowance. Claims depending therefrom, either directly or indirectly, are also not in a condition for allowance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5, 8, 12, 15, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Hyun et al. US 2013/0205085 (“Hyun”) in view of Chan US 2007/0171725 (“Chan”) and in further view of NPL Du et al. “A Novel Program Suspend Scheme for Improving the Reliability of 3D NAND Flash Memory”, Journal of the Electron Device Society, Volume 10, 2022 (Du’NPL).
As per independent claim 1, Hyun teaches A memory device (“memory device 116” para 0041 and FIGS. 1-2) comprising:
a memory array (“memory elements 126” para 0041 and FIG. 2);
control logic (“controller 114” para 0043 and FIGS. 1-2), operatively coupled with the memory array (“control signals from the controller 114 are transmitted to the memory device 116 via one or more control signal lines 152.” Para 0043 and FIGS. 1-2), to perform operations comprising:
initiating application of a program pulse on the memory array as part of a program operation (“the program operations are performed using incremental step pulse programming (ISPP), in which a memory element 126 is programmed to a specific state (bit combination) using incremental voltage steps or pulses.” Para 0036 and FIGS. 3A-3B);
determining whether a first request to suspend the program operation was received during the application of the program pulse (“The program suspend module 120 may suspend a program operation at one or more groups of memory elements 126 of the memory device 116 in response to receiving a read access request or other memory access request from an application 128.” Para 0038. “the program suspend module 120 is configured to store information that defines the state or progress of the program operation, including a pulse count at which the current program operation is suspended.” Para 0036);
responsive to determining that the first request to suspend the program operation was received during the application of the program pulse, setting a program suspend indicator to a suspend state (“the program suspend module 120 is configured to store information that defines the state or progress of the program operation, including a pulse count at which the current program operation is suspended.” Para 0036. “The memory control manager 140 may then set a bit of the program suspend register 160 to indicate that the memory control manager 140 is suspending the current program operation.” Para 0049 and FIG. 2);
responsive to completing the program verify operation, determining that the program suspend indicator is set to the suspend state and suspending the program operation (“the program suspend module 120 is configured to store information that defines the state or progress of the program operation, including a pulse count at which the current program operation is suspended.” Para 0036. “The memory control manager 140 may then set a bit of the program suspend register 160 to indicate that the memory control manager 140 is suspending the current program operation.” Para 0049 and FIG. 2).
Hyun discloses all of the claim limitations from above. It is implicit or inherent in Hyun that a verification step is performed following the application of an ISPP. This is because Hyun teaches “memory element 126 is programmed to a specific state (bit combination)” para 0036. Furthermore, Hyun teaches “desired bit configuration” or “desired state” of the memory element 126 that are only achievable with a verify step. Further, Hyun does not explicitly teach “wherein the program pulse continues to be applied after setting the program suspend indicator to the suspend state” and “wherein the program operation is not suspended until after the program verify operation is complete”.
Nevertheless, in order to show that a verify step is typically performed following a program pulse, an analogous art in the same field of endeavor Chan is relied upon. Chan teaches responsive to completing application of the program pulse, initiating a program verify operation on the memory array (Chan in the background section teaches “A program operation typically includes alternate cycles of applying a programming pulse followed by sensing to program verify if a memory cell has been programmed to an intended state.” Para 0038).
Given the teaching of Chan, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Hyun with “responsive to completing application of the program pulse, initiating a program verify operation on the memory array”. The motivation would be that the disclosure of Chan improves program performance including improving program verify operations, para 0039 of Chan.
Hyun in view of Chan discloses all of the claim limitations from above, but does not explicitly teach “wherein the program pulse continues to be applied after setting the program suspend indicator to the suspend state” and “wherein the program operation is not suspended until after the program verify operation is complete”.
However, in an analogous art in the same field of endeavor, Du’NPL teaches wherein the program pulse continues to be applied after setting the program suspend indicator to the suspend state (“a novel program suspend scheme is proposed by adding a ‘stabilizing’ pulse to mimic the verify pulse after the program stage, if the program suspend command is issued during the program stage, as elaborated in Fig. 5(a).” Page 101, second column, third paragraph);
wherein the program operation is not suspended until after the program verify operation is complete (“a novel program suspend scheme is proposed by adding a ‘stabilizing’ pulse to mimic the verify pulse after the program stage, if the program suspend command is issued during the program stage, as elaborated in Fig. 5(a).” Page 101, second column, third paragraph).
Given the teaching of Du’NPL, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Hyun and Chan with “wherein the program pulse continues to be applied after setting the program suspend indicator to the suspend state” and “wherein the program operation is not suspended until after the program verify operation is complete”. The motivation would be that experimental results show that with the “stabilizing” pulse, a critical ratio is small enough to be handled by ECC or other soft-correction mechanism, page 102, second column, first paragraph of Du’NPL.
As per dependent claim 5, Hyun in combination with Chan and Du’NPL discloses the device of claim 1. Hyun teaches wherein the control logic is to perform operations further comprising: initiating a read operation on the memory array while the program operation is suspended; and responsive to completing the read operation, initiating a verify resume operation and resuming the program operation (“After the read operation is completed … the program operation may be resumed.” Para 0053).
As per claims 8 and 12, these claims are respectively rejected based on arguments provided above for similar rejected claims 1 and 5.
As per claims 15 and 19, these claims are respectively rejected based on arguments provided above for similar rejected claims 1 and 5.
Claims 2, 6-7, 9, 13-14, 16-17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hyun in view of Chan and in further view of Du’NPL and in further view of Du et al. US 2023/0367488 (“Du”).
As per dependent claim 2, Hyun in combination with Chan and Du’NPL discloses the device of claim 1. Hyun, Chan, and Du’NPL may not explicitly disclose, but in an analogous art in the same field of endeavor, Du teaches wherein the control logic is to perform operations further comprising: determining whether a second request to suspend the program operation was received during the program verify operation (“control logic 512 … may receive an interrupt command, e.g., issued by a memory controller, during word line driver 508 applies a verify voltage on select word line 318, e.g., within a verify phase, as shown in FIG. 13A.” Para 0091);
responsive to determining that the second request to suspend the program operation was received during the program verify operation, setting the program suspend indicator to the suspend state (“control logic 512 may be configured to store the information of the suspended program operation … into registers 514.” Para 0097).
Given the teaching of Du, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Hyun, Chan, and Du’NPL with “wherein the control logic is to perform operations further comprising: determining whether a second request to suspend the program operation was received during the program verify operation” and “responsive to determining that the second request to suspend the program operation was received during the program verify operation, setting the program suspend indicator to the suspend state”. The motivation would be that the invention improves performance of a memory device, para 0099 of Du.
As per dependent claim 6, Hyun in combination with Chan and Du’NPL discloses the device of claim 5. Hyun, Chan, and Du’NPL may not explicitly disclose, but in an analogous art in the same field of endeavor, Du teaches wherein the control logic is to perform operations further comprising: responsive to resuming the program operation, determining whether a third request to suspend the program operation was received during the verify resume operation; and responsive to determining that the third request to suspend the program operation was received during the verify resume operation, setting the program suspend indicator to the suspend state and initiating application of a subsequent program pulse on the memory array as part of the program operation (“In response to a resume command … peripheral circuits 302 can be configured to resume the suspended program operation. … control logic 512 is further configured to retrieve the information of the suspended program operation stored in registers 514 … As shown in FIGS. 10A, 11A, and 13A, once the program operation is resumed, in the same program/verify cycle … a verify voltage … corresponding to the same cycle, can be applied to check whether the threshold voltage of each programmed memory cell 306 reaches the verify voltage. … the clean process may be performed to suspend the ongoing verify phase during which the interrupt command is received. … once the interrupt command is received, the ongoing verify phase may be stopped immediately, and the clean process may be initiated.” Para 0098. “If one or more memory cells … fail to pass the verification … a subsequent program/verify cycle … may be applied on the verification-failed memory cells with an increased program voltage.” Para 0099).
Given the teaching of Du, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Hyun, Chan, and Du’NPL with “wherein the control logic is to perform operations further comprising: responsive to resuming the program operation, determining whether a third request to suspend the program operation was received during the verify resume operation; and responsive to determining that the third request to suspend the program operation was received during the verify resume operation, setting the program suspend indicator to the suspend state and initiating application of a subsequent program pulse on the memory array as part of the program operation”. The motivation would be that the invention improves performance of a memory device, para 0099 of Du.
As per dependent claim 7, Hyun in combination with Chan, Du’NPL, and Du discloses the device of claim 6. Hyun teaches wherein the control logic is to perform operations further comprising: responsive to determining that the third request to suspend the program operation was not received during the verify resume operation, setting the program suspend indicator to a default state (“the memory control manager 140 may store a bit value of one (1) in the program suspend register 160 to indicate that the current program operation is suspended.” Para 0049. Hence, the default value would be a zero (0)).
As per dependent claims 9 and 13-14, these claims are respectively rejected based on arguments provided above for similar rejected dependent claims 2 and 6-7.
As per dependent claims 16 and 20, these claims are respectively rejected based on arguments provided above for similar rejected dependent claims 2 and 6.
As per dependent claim 17, Hyun in combination with Chan, Du’NPL, and Du discloses the device of claim 16. Hyun teaches wherein the suspend indicator is set to a first state to represent that the request to suspend the program operation was received and to a second state to represent that the request to suspend the program operation was not received (“the memory control manager 140 may store a bit value of one (1) in the program suspend register 160 to indicate that the current program operation is suspended.” Para 0049. Hence, the default value would be a zero (0)).
Claims 3-4, 10-11, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Hyun in view of Chan and in further view of Du’NPL and in further view of Donati et al. US 2020/0273523 (“Donati”).
As per dependent claim 3, Hyun in combination with Chan and Du’NPL discloses the device of claim 1. Hyun, Chan, and Du’NPL may not explicitly disclose, but in an analogous art in the same field of endeavor, Donati teaches wherein the program verify operation does not utilize a selective slow program convergence (SSPC) pulse (“the controller determined that the cell is in program state in scenario ‘c’. Therefore, the SSPC voltage will not be applied to the channel.” Para 0050).
Given the teaching of Donati, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Hyun, Chan, and Du’NPL with “wherein the program verify operation does not utilize a selective slow program convergence (SSPC) pulse”. The motivation would be that the technique described improves threshold voltage distribution, para 0051 of Donati.
As per dependent claim 4, Hyun in combination with Chan and Du’NPL discloses the device of claim 1. Hyun teaches setting the program suspend indicator to a default state (“the memory control manager 140 may store a bit value of one (1) in the program suspend register 160 to indicate that the current program operation is suspended.” Para 0049. Hence, the default value would be a zero (0)).
Hyun, Chan, and Du’NPL may not explicitly disclose, but in an analogous art in the same field of endeavor, Donati teaches wherein the control logic is to perform operations further comprising: responsive to determining that the first request to suspend the program operation was not received during the application of the program pulse (“After the fourth program pulse, the memory array receives a suspend command.” Para 0048 and FIGS. 4A-4C),
responsive to completing application of the program pulse, initiating a program verify operation on the memory array using a selective slow program convergence (SSPC) pulse (“Because the cell is in the SSPC state, the voltage applied to the channel via the bitline in this example is V_step/2.” Para 0049 and FIGS. 4A-4C).
Given the teaching of Donati, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Hyun, Chan, and Du’NPL with “further comprising: responsive to determining that the first request to suspend the program operation was not received during the application of the program pulse” and “responsive to completing application of the program pulse, initiating a program verify operation on the memory array using a selective slow program convergence (SSPC) pulse”. The motivation would be that the technique described improves threshold voltage distribution, para 0051 of Donati.
As per dependent claims 10-11, these claims are respectively rejected based on arguments provided above for similar rejected dependent claims 3-4.
As per dependent claim 18, this claim is rejected based on arguments provided above for similar rejected dependent claim 3.
Conclusion
Another close prior art reference Pelster et al. US 2019/0243577 (“Pelster”) was considered by the Examiner. Pelster negates the patentability of the instant claimed invention. For example, Pelster teaches “The embodiments shown in FIG. 7 introduce a configurable construct to program N tiers of progress pulses for specifying an exact minimum of program pulses that must be completed after the program operation is resumed before a subsequent suspend command can be allowed.” Paragraph [0052] of Pelster.
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/ZUBAIR AHMED/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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