DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6, 8-10, 11, 16 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0317027 to Ishii; in view of US 2020/0357330 to Endo; in view of US 2019/0370109 to Ishikawa.
As per claim 1, Ishii teaches a vehicle display system, comprising:
a display device (Fig. 1), comprising a display panel (Fig. 1, 11) and a plurality of first driving circuits (Fig. 1, 14-1:14-3), wherein the plurality of first driving circuits are configured to drive the display panel; and
a control circuit (Fig. 1, timing controller 12), electrically connected to the plurality of first driving circuits, and configured to provide register data (Fig. 2, paragraph 36, “The setting register 23 has setting data written thereto in accordance with the writing operation of the timing controller 12”),
wherein at least one of the plurality of first driving circuits receives and temporarily stores the register data (Fig. 2, stored in register 23) and checks the register data (Fig. 2, checked by controller 25/28), and the at least one of the plurality of first driving circuits reports a check result to the control circuit when the register data fails a check (paragraph 63, “The timing controller 12 accesses the register controller 31 using setting communication (communication signal CS) and reads the comparison result CR …. if the comparison result CR indicates that the checksum values do not match (logical level 0 in this embodiment), then the timing controller 12 determines that failure has occurred in the logic circuit provided in the source controller 25 of the source driver 14-1”).
Ishii does not teach wherein the control circuit generates or receives a control command, calculates a cyclic redundancy check (CRC) code and appends the CRC code to the control command to form register data.
Endo suggests wherein the control circuit generates or receives a control command (paragraph 42, “the graphics processor 400 is capable of transmitting a packet command”; paragraph 71, “when an error has been detected, an interrupt is issued to the graphics processor 400”), calculates a cyclic redundancy check (CRC) code and appends the CRC code to the control command to form register data (Figs. 5B-5C, “In order to allow the receiver side to verify whether or not the packet command has been received correctly, CRC bits are appended. FIG. 5C shows pixel data (which will be referred to as the “BDP pixel data”) including the cyclic redundancy code (CRC) data as appended data.”).
It would have been obvious to one of ordinary skill in the art, to modify the device of Ishii, so that the control circuit generates or receives a control command, calculates a cyclic redundancy check (CRC) code and appends the CRC code to the control command to form register data, such as taught by Endo, for the purpose of validating transmitted data.
Ishii and Endo do not teach wherein the at least one of the plurality of first driving circuits comprises a storage circuit and a check circuit in direct connection to the storage circuit, the register data is stored in the storage circuit and the check circuit checks the register data.
Ishikawa wherein the at least one of the plurality of first driving circuits (paragraph 34, “in the case where the circuit apparatus 100 is a display driver”) comprises a storage circuit (Fig. 1, 10) and a check circuit in direct connection to the storage circuit, the register data is stored in the storage circuit and the check circuit checks the register data (paragraph 77, “the control circuit 110 reads out the setting data from the register 130, and generates a CRC value. Next, as shown in step S7, the control circuit 110 writes the setting data and the CRC value to the nonvolatile memory 10”; paragraph 79, “a CRC value that serves as the error detection data is automatically generated in the circuit apparatus 100 and written to the nonvolatile memory 10”).
It would have been obvious to one of ordinary skill in the art, to modify the device of Ishii and Endo, so that the at least one of the plurality of first driving circuits comprises a storage circuit and a check circuit in direct connection to the storage circuit, the register data is stored in the storage circuit and the check circuit checks the register data, such as taught by Ishikawa, for the purpose of ensuring proper display operation.
As per claim 6, Ishii, Endo and Ishikawa teach the vehicle display system according to claim 1, wherein the display device further comprises a gamma correction circuit (Ishii, 34-2, paragraph 53, “calculation based on the setting data for the gamma setting mode 1 and the gamma setting mode 2 to derive a setting value”), wherein the control circuit is electrically connected to the gamma correction circuit and configured to provide the register data (Fig. 2, paragraph 36, “The setting register 23 has setting data written thereto in accordance with the writing operation of the timing controller 12”).
As per claim 8, Ishii, Endo and Ishikawa teach the vehicle display system according to claim 1, wherein the control circuit comprises a timing controller (Fig. 1, 12), a micro controller unit or a vehicle control unit.
As per claim 9, Ishii, Endo and Ishikawa teach the vehicle display system according to claim 1, wherein a check method used by one of the plurality of first driving circuits comprises cyclic redundancy check or checksum (paragraph 85).
As per claim 10, Ishii, Endo and Ishikawa teach the vehicle display system according to claim 1, wherein the register data is not stored after the vehicle display system is shut down or restarted (paragraph 49, “The setting register group 32 is constituted of a plurality of D flip-flops, for example”).
As per claim 11, it comprises similar limitations to those in claim 1 and it is therefore rejected for similar reasons.
As per claim 16, it comprises similar limitations to those in claim 6 and it is therefore rejected for similar reasons.
As per claim 18, it comprises similar limitations to those in claim 8 and it is therefore rejected for similar reasons.
As per claim 19, it comprises similar limitations to those in claim 9 and it is therefore rejected for similar reasons.
As per claim 20, it comprises similar limitations to those in claim 10 and it is therefore rejected for similar reasons.
Claim 2 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0317027 to Ishii; in view of US 2020/0357330 to Endo; in view of US 2019/0370109 to Ishikawa; in view of US 2021/0020136 to Zhao.
As per claim 2, Ishii, Endo and Ishikawa teach the vehicle display system according to claim 1.
Ishii, Endo and Ishikawa do not explicitly disclose wherein when the register data passes the check, the at least one of the plurality of first driving circuits executes a corresponding function.
Zhao teaches wherein when the register data passes the check, the at least one of the plurality of first driving circuits executes a corresponding function (paragraph 43, “the analyzing and processing module 11 … records the display data signal and sends it to the display panel 30 for display via the driver 21”).
It would have been obvious to one of ordinary skill in the art, to modify the device of Ishii, Endo and Ishikawa, so that wherein when the register data passes the check, the at least one of the plurality of first driving circuits executes a corresponding function, such as taught by Zhao, for the purpose of improving display quality.
As per claim 12, it comprises similar limitations to those in claim 2 and it is therefore rejected for similar reasons.
Claim 3 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0317027 to Ishii; in view of US 2020/0357330 to Endo; in view of US 2019/0370109 to Ishikawa; in view of US 2018/0240397 to Hara.
As per claim 3, Ishii, Endo and Ishikawa teach the vehicle display system according to claim 1.
Ishii, Endo and Ishikawa do not explicitly disclose wherein the control circuit again provides the register data to the at least one of the plurality of first driving circuits that reports the check result after the control circuit receives the check result.
Zhao teaches wherein the control circuit again provides the register data to the at least one of the plurality of first driving circuits that reports the check result after the control circuit receives the check result (paragraph 59, “the external device can perform processing (such as re-transmission of image data”).
It would have been obvious to one of ordinary skill in the art, to modify the device of Ishii, Endo and Ishikawa, so that the control circuit again provides the register data to the at least one of the plurality of first driving circuits that reports the check result after the control circuit receives the check result, such as taught by Hara, for the purpose of improving display quality.
As per claim 13, it comprises similar limitations to those in claim 3 and it is therefore rejected for similar reasons.
Claim 4 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0317027 to Ishii; in view of US 2020/0357330 to Endo; in view of US 2019/0370109 to Ishikawa; in view of US 2024/0038110 to Kobayashi.
As per claim 4, Ishii, Endo and Ishikawa teach the vehicle display system according to claim 1, wherein the display device further comprises a backlight module (paragraph 22, “a backlight installed within the display device”) wherein the control circuit is configured to provide the register data (Fig. 2, paragraph 36, “The setting register 23 has setting data written thereto in accordance with the writing operation of the timing controller 12”).
Ishii, Endo and Ishikawa do not explicitly teach a plurality of second driving circuits, and the plurality of second driving circuits are configured to drive the backlight module, wherein the control circuit is electrically connected to the plurality of second driving circuits.
Kobayashi teaches a plurality of second driving circuits (Fig. 3, 60/130), and the plurality of second driving circuits are configured to drive the backlight module, wherein the control circuit is electrically connected to the plurality of second driving circuits (Fig. 3, processing device 200 is analogous to the control circuit).
It would have been obvious to one of ordinary skill in the art, to modify the device of Ishii, Endo and Ishikawa, by including a plurality of second driving circuits, and the plurality of second driving circuits are configured to drive the backlight module, wherein the control circuit is electrically connected to the plurality of second driving circuits, such as taught by Kobayashi, for the purpose of controlling a desired brightness.
As per claim 14, it comprises similar limitations to those in claim 4 and it is therefore rejected for similar reasons.
Claim 5 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0317027 to Ishii; in view of US 2020/0357330 to Endo; in view of US 2019/0370109 to Ishikawa; in view of US 2018/0061294 to Kim et al.
As per claim 5, Ishii, Endo and Ishikawa teach the vehicle display system according to claim 4.
Ishii, Endo and Ishikawa do not teach wherein data is transmitted between the plurality of second driving circuits and between the control circuit and the plurality of second driving circuits through a serial peripheral interface.
Kim et al. teach wherein data is transmitted between the plurality of second driving circuits and between the control circuit and the plurality of second driving circuits through a serial peripheral interface (paragraph 57, “The backlight controller may transfer backlight control data, including a duty ratio control value of a pulse width modulation (PWM) signal, to the backlight driver in a serial peripheral interface (SPI) data format according to a global/local diming signal input from a host system or the timing controller”).
It would have been obvious to one of ordinary skill in the art, to modify the device of Ishii, Endo and Ishikawa, so that data is transmitted between the plurality of second driving circuits and between the control circuit and the plurality of second driving circuits through a serial peripheral interface, such as taught by Kim et al., for the purpose of simplifying a wiring configuration.
As per claim 15, it comprises similar limitations to those in claim 5 and it is therefore rejected for similar reasons.
Claim 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0317027 to Ishii; in view of US 2020/0357330 to Endo; in view of US 2019/0370109 to Ishikawa; in view of US 2022/0148469 to Sun et al.
As per claim 7, Ishii, Endo and Ishikawa teach the vehicle display system according to claim 1.
Ishii, Endo and Ishikawa do not teach wherein data is transmitted between the plurality of first driving circuits and between the control circuit and the plurality of first driving circuits through a controller area network bus.
Sun et al. teach wherein data is transmitted between the plurality of first driving circuits and between the control circuit and the plurality of first driving circuits through a controller area network bus (paragraph 12, “utilize transmission interface technologies, such as inter-integrated circuit (I.sup.2C) bus interface, universal asynchronous receiver/transmitter (UART) interface, serial peripheral interface (SPI), universal serial bus (USB) interface, controller area network bus (CAN bus) interface”).
It would have been obvious to one of ordinary skill in the art, to modify the device of Ishii, Endo and Ishikawa, so that data is transmitted between the plurality of first driving circuits and between the control circuit and the plurality of first driving circuits through a controller area network bus, such as taught by Sun et al. for the purpose of enduring reliable data transmission.
As per claim 17, it comprises similar limitations to those in claim 7 and it is therefore rejected for similar reasons.
Conclusion
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/JOSE R SOTO LOPEZ/Primary Examiner, Art Unit 2622