Prosecution Insights
Last updated: April 19, 2026
Application No. 18/747,314

SYSTEMS AND METHODS FOR COMPARTMENTALIZATION

Non-Final OA §102
Filed
Jun 18, 2024
Examiner
RAHIM, MONJUR
Art Unit
2436
Tech Center
2400 — Computer Networks
Assignee
Dover Microsystems Inc.
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
3y 1m
To Grant
99%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allow Rate
742 granted / 879 resolved
+26.4% vs TC avg
Strong +16% interview lift
Without
With
+16.1%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
37 currently pending
Career history
916
Total Applications
across all art units

Statute-Specific Performance

§101
11.7%
-28.3% vs TC avg
§103
41.7%
+1.7% vs TC avg
§102
26.6%
-13.4% vs TC avg
§112
5.5%
-34.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 879 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION 1. This action is responsive to: an original application filed on 18 June 2024. 2. Claims 1-20 are currently pending and claims 1 and 20 are independent claims. Information Disclosure Statement 3. No IDS filed. Priority 4. Priority claimed from provisional application no.63/509,000, filed on 19 December 2024. Drawings 5. The drawings filed on 18 June 2024 are accepted by the examiner. Claim Rejections - 35 USC § 102 6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-20 are rejected 35 U.S.C §102 (a)(2) as being anticipated by Milburn et al. (US Publication No. 20210406028), hereinafter Milburn. Regarding claim 1: A method comprising acts of: in response to receiving a compartment update request, determining, by compartment check hardware, a target compartment of a compartment transition triggering the compartment update request (Milburn, ¶66-67, ¶144). and loading, by the compartment check hardware, a compartment configuration corresponding to the target compartment, wherein the compartment configuration indicates at least one address range associated with the target compartment (Milburn, ¶10, ¶122-123). Regarding claim 2: wherein: the target compartment of the compartment transition is determined at least in part by: determining, based on the compartment update request, a local identifier of the target compartment relative to a source compartment of the compartment transition; and using a compartment configuration corresponding to the source compartment to map the local identifier of the target compartment to a global identifier of the target compartment, wherein: the compartment configuration corresponding to the target compartment is loaded based on the global identifier of the target compartment (Milburn, ¶45, ¶86, Abstract). Regarding claim 3: wherein: the global identifier of the target compartment comprises a memory address at which the compartment configuration corresponding to the target compartment is stored (Milburn, ¶12). Regarding claim 4: wherein: the at least one address range associated with the target compartment comprises at least one address range that an instruction executing in the target compartment is allowed to access (Milburn, ¶15-18). Regarding claim 5: wherein: the compartment transition comprises a branch instruction; the target compartment of the compartment transition is determined at least in part by: determining, based on the compartment update request, a target address of the branch instruction; and matching the target address of the branch instruction to the target compartment (Milburn, ¶84-85, ¶22). Regarding claim 6: wherein: the compartment update request is received from tag processing hardware configured to check instructions executed by a host system; and the method further comprises acts of, by the tag processing hardware: detecting the compartment transition, at least in part by determining that an instruction executed by the host system represents a transfer of control from a source compartment to the target compartment; and issuing the compartment update request in response to detecting the compartment transition (Milburn, ¶76, ¶123). Regarding claim 7: wherein: the tag processing hardware determines that the instruction represents a transfer of control at least in part by determining that the instruction matches at least one rule of a compartmentalization policy (Milburn, ¶3). Regarding claim 8: wherein: the compartmentalization policy comprises a compartment entry rule and/or a compartment exit rule (Milburn, ¶107). Regarding claim 9: wherein: the method further comprises an act of constructing, by the tag processing hardware, an input pattern based on metadata selected from a group consisting of: an instruction type of the instruction; and metadata associated with the instruction; the input pattern is used to determine whether the instruction matches at least one rule of the compartmentalization policy (Milburn, ¶114, 112). Regarding claim 10: wherein: the method further comprises an act of determining whether the compartment transition is allowed; and the act of loading the compartment configuration corresponding to the target compartment is performed in response to determining that the compartment transition is allowed (Milburn, Abstract). Regarding claim 11: wherein: the act of determining whether the compartment transition is allowed comprises determining whether a compartment transition graph includes a transition from a source compartment of the compartment transition to the target compartment of the compartment transition (Milburn, ¶13-15). Regarding claim 12: wherein: the compartment configuration corresponding to the target compartment is loaded prior to receiving the compartment update request; and the method further comprises acts of: predicting, by the compartment check hardware, one or more compartment configurations that are likely to be encountered; loading, by the compartment check hardware, the one or more predicted compartment configurations; and determining, by the compartment check hardware, whether any of the one or more predicted compartment configurations is associated with the target compartment of the compartment transition triggering the compartment update request (Milburn, ¶141-144). Regarding claim 13: further comprising acts of: in response to receiving a compartment check request, determining, by the compartment check hardware, a memory address associated with an instruction triggering the compartment check request; determining, by the compartment check hardware, based on a current compartment configuration, one or more address ranges; and checking the memory address associated with the instruction triggering the compartment check request against the one or more address ranges determined based on the current compartment configuration (Milburn, ¶47, 12-13). Regarding claim 14: wherein: the memory address associated with the instruction comprises a memory address from which the instruction is fetched; and the memory address from which the instruction is fetched is checked against a code address range in the current compartment configuration (Milburn, ¶47, ¶74). Regarding claim 15: wherein: the memory address associated with the instruction comprises a memory address that the instruction is attempting to access; and the memory address that the instruction is attempting to access is checked against a data address range in the current compartment configuration (Milburn, ¶147, ¶150). Regarding claim 16: wherein: the compartment update request comprises a first compartment update request; and the method further comprises acts of: determining, based on a second compartment update request, information relating to an address range that is dynamically allocated for a compartment to which the second compartment update request pertains; and using the information relating to the address range to update a compartment configuration for the compartment to which the second compartment update request pertains (Milburn, ¶55, 56). Regarding claim 17: wherein: the information relating to the address range comprises a start address, an end address, and/or a size of the address range (Milburn, ¶17). Regarding claim 18: wherein: the second compartment update request is triggered as a result of a host system executing a runtime library function allocating the address range for the compartment to which the second compartment update request pertains; the runtime library function presents the information relating to the address range on a data bus of the host system; and the act of determining the information relating to the address range comprises, in response to the second compartment update request, capturing the information relating to the address range from the data bus of the host system (Milburn, ¶54-56). Regarding claim 19: wherein: the compartment update request is sent by a host processor as a result of executing one or more instructions in a source compartment, the one or more instructions configured to cause the host processor to provide, to the compartment check hardware, a global identifier for a source compartment of the compartment transition, a global identifier for the target compartment of the compartment transition, and/or a local identifier for the target compartment relative to the source compartment (Milburn, ¶45, ¶86, Abstract). Regarding claim 20: the processing hardware comprises compartment check hardware implemented by one or more processors programmed by executable instructions, one or more programmable logic devices programmed by bitstreams, and/or one or more logic circuits fabricated into semiconductors (Milburn, ¶153, 79-80). and the compartment check hardware is configured to: in response to receiving a compartment update request, determine a target compartment of a compartment transition triggering the compartment update request (Milburn, ¶66-67, ¶144). load a compartment configuration corresponding to the target compartment, wherein the compartment configuration indicates at least one address range associated with the target compartment (Milburn, ¶10, ¶122-123). Conclusion 7. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Monjour Rahim whose telephone number is (571)270-3890. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Shewaye Gelagay can be reached on 571-272-4219. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (in USA or CANANDA) or 571-272-1000. /Monjur Rahim/ Patent Examiner United States Patent and Trademark Office Art Unit: 2436; Phone: 571.270.3890 E-mail: monjur.rahim@uspto.gov Fax: 571.270.4890
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Prosecution Timeline

Jun 18, 2024
Application Filed
Oct 08, 2025
Non-Final Rejection — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
99%
With Interview (+16.1%)
3y 1m
Median Time to Grant
Low
PTA Risk
Based on 879 resolved cases by this examiner. Grant probability derived from career allow rate.

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