DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This communication is considered fully responsive to the amendment filed on 08/19/2026.
Claims 1, 19 and 20 have been amended.
Rejection to claims under 35 USC § 112 is withdrawn since the claims have been amended accordingly.
New title is accepted.
Response to Arguments
Applicant’s arguments with respect to claims filed on 08/19/2026 have been considered but are moot because the arguments are related solely to newly added limitations addressed in the instant Office Action with one of the previously identified prior art, thus rendering the applicant’s arguments moot.
The applicant also presented other arguments drawn to the various dependent claims. However, said other arguments are all dependency based, depending from the arguments drawn to the independent claims’ limitations discussed above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 7, 9, 11, 16 and 19 rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2016/0239444, “Chen”) in view of Tsai et al. (US 2024/0013824, “Tsai”).
Examiner’s note: in what follows, references are drawn to Chen unless otherwise mentioned.
Chen comprises the following features:
With respect to independent claims:
Regarding claim 1, a semiconductor device comprising:
a first semiconductor die ([0023, Fig. 1 and Fig. 3] “A single package 300 has multiple dies, including at least a first die (denoted by “Die 0”) 302 and a second die (denoted by “Die 1”) 304”) including a first transmission circuit, a first reception circuit and a first mask circuit (See Fig. 3, and [0026] “The first die 302 has a clock source 312, an input circuit 314, an output circuit 316, and a sub-system 318.” That is, 318, 314 and 316 are equivalent to the recited first transmission circuit, first reception circuit and first mask circuit, respectively.), the first mask circuit configured to receive a first data ([Fig. 3 and 0026] “The output circuit 316 is used to transfer transmit data (which is generated by the sub-system 318) to the second die 304”), which is output by the first transmission circuit in accordance with a first clock signal (See Fig. 3 for 316 is functioning with CLK0.), to output the first data to an outside (See Fig. 3 for data transfer from 316 to 324.) during a first operation period ([0031 and Fig. 4] “the interface valid signal Valid with a 1T active period allows one data transfer between the sub-system 402 and the asynchronous FIFO buffer 404, where T is a period of the source clock used by the sub-system 402.”), to stop the output of the first data during a second operation period ([0032 and Fig. 4] “When the sub-system 402 enters the wait state, the interface valid signal Valid is deasserted (inactive) and the data transfer between the sub-system 402 and the asynchronous FIFO buffer 404 is stopped”. Note that Chen’s disclosure is its flow-control arrangement in which a TX-side controller causes a wait state and inactivates a valid signal so that data transfer is stopped.), and to control an output timing of the first data output to the outside at a transmission frequency that differs from a frequency of the first clock signal (This will be discussed in view of Tsai.); and
a second semiconductor die ([0023, Fig. 1 and Fig. 3] “A single package 300 has multiple dies, including at least a first die (denoted by “Die 0”) 302 and a second die (denoted by “Die 1”) 304”) including a second reception circuit (See Fig. 3 for 324 “Async FIFO” in the second die, 304.), the second reception circuit configured to read the first data, which is transmitted from the first semiconductor die and buffered, in accordance with a second clock signal that is different from the first clock signal ([0028] “With regard to the input circuit 324, it buffers the transmit data (which is transferred from the output circuit 316) in the asynchronous FIFO buffer 325 according to the first clock CLK0 generated at the first die 302, and outputs the buffered transmit data in the asynchronous FIFO buffer 325 to the sub-system 328 according to the second clock CLK1 generated at the second die 304.”).
It is noted that while disclosing two dies transferring data, Chen does not specifically teach about a block enabling and disabling transmissions during time periods. It, however, had been known in the art before the effective date of the instant application as shown by Tsai as follows;
to output the first data to an outside during a first operation period ([Tsai, 0070] “The first four clock cycles of the write clock gating enabling signal WGE, each labeled as 1, correspond to the enabling section.”);
to stop the output of the first data during a second operation period ([Tsai, 0072] “The rest two clock cycles of each of the read clock gating enabling signals RGE.sub.1˜RGE.sub.K, each labeled as 0, are used to disable the transmission”); and
to control an output timing of the first data output to the outside at a transmission frequency that differs from a frequency of the first clock signal ([Tsai, 0072] “The first four clock cycles of each of the read clock gating enabling signals RGE.sub.1˜RGE.sub.K, each labeled as 1, correspond to the enabling section. The rest two clock cycles of each of the read clock gating enabling signals RGE.sub.1˜RGE.sub.K, each labeled as 0, are used to disable the transmission of one of the read clock signals RCK.sub.1˜RCK.sub.K.” Note that the claimed first clock signal and output clock are equivalent to the cited read clock signal RCK and the gating clock, respectively. See [Tsai, 0066] “an enable section of each of the read clock gating enabling signals RGE.sub.1˜RGE.sub.K, which is a high state section, controls each of the read clock gating circuits 130 to transmit four clock cycles of the read clock signals RCK.sub.1˜RCK.sub.K to each of the data transmission circuits 110 labeled as DT.sub.1˜DT.sub.K.”).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of instant application to modify Chen by using the features of Tsai in order to control transmission timing between different time domains and reduce transfer failure such that “a data transmission apparatus having clock gating mechanism that includes a plurality of data transmission circuits, a write clock gating circuit, a plurality of read clock gating circuits and a gating signal transmission circuit.” [Tsai, 0007].
Regarding claim 19, a semiconductor chip comprising:
a transmission circuit (See Fig. 3 for 318.) configured to output data in accordance with a clock signal (See Fig. 3 for CLK0 in 302.); and
a mask circuit (See Fig. 3 for 316.) configured to receive the clock signal (See Fig. 3 for CLK0.) and the data output from the transmission circuit (See Fig. 3 for data from 318 to 316.), to output the data to an outside during a first operation period, to stop outputting the data to the outside during a second operation period ([0032 and Fig. 4] “When the sub-system 402 enters the wait state, the interface valid signal Valid is deasserted (inactive) and the data transfer between the sub-system 402 and the asynchronous FIFO buffer 404 is stopped”. Note that Chen’s disclosure is its flow-control arrangement in which a TX-side controller causes a wait state and inactivates a valid signal so that data transfer is stopped.), and to control an output timing of the data output to the outside at a transmission frequency different from a frequency of the clock signal (This will be discussed in view of Tsai.).
It is noted that while disclosing two dies transferring data, Chen does not specifically teach about a block enabling and disabling transmissions during time periods. It, however, had been known in the art before the effective date of the instant application as shown by Tsai as follows;
to output the first data to an outside during a first operation period ([Tsai, 0070] “The first four clock cycles of the write clock gating enabling signal WGE, each labeled as 1, correspond to the enabling section.”);
to stop the output of the first data during a second operation period ([Tsai, 0072] “The rest two clock cycles of each of the read clock gating enabling signals RGE.sub.1˜RGE.sub.K, each labeled as 0, are used to disable the transmission”); and
to control an output timing of the first data output to the outside at a transmission frequency that differs from a frequency of the first clock signal ([Tsai, 0072] “The first four clock cycles of each of the read clock gating enabling signals RGE.sub.1˜RGE.sub.K, each labeled as 1, correspond to the enabling section. The rest two clock cycles of each of the read clock gating enabling signals RGE.sub.1˜RGE.sub.K, each labeled as 0, are used to disable the transmission of one of the read clock signals RCK.sub.1˜RCK.sub.K.” Note that the claimed first clock signal and output clock are equivalent to the cited read clock signal RCK and the gating clock, respectively. See [Tsai, 0066] “an enable section of each of the read clock gating enabling signals RGE.sub.1˜RGE.sub.K, which is a high state section, controls each of the read clock gating circuits 130 to transmit four clock cycles of the read clock signals RCK.sub.1˜RCK.sub.K to each of the data transmission circuits 110 labeled as DT.sub.1˜DT.sub.K.”).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of instant application to modify Chen by using the features of Tsai in order to control transmission timing between different time domains and reduce transfer failure such that “a data transmission apparatus having clock gating mechanism that includes a plurality of data transmission circuits, a write clock gating circuit, a plurality of read clock gating circuits and a gating signal transmission circuit.” [Tsai, 0007].
With respect to dependent claim:
Regarding claim 7, the semiconductor device according to claim 1, wherein the second operation period is a period that is continuous with the first operation period (See [Tsai, Fig. 5] and aforesaid [Tsai, 0072]).
Regarding claim 9, the semiconductor device according to claim 1, wherein a frequency of the first clock signal is greater than a frequency of the second clock signal ([0039] “a clock sys_ck generated by a clock source at the TX side is faster than a clock sys_ck′ generated by a clock source at the RX side”).
Regarding claim 11, the semiconductor device according to claim 1, wherein the first mask circuit outputs a transmission stop signal to the first transmission circuit before the second operation period starts ([0034] “when the asynchronous FIFO buffer 504 is almost full, the controller 503 generates one stall event to the sub-system 502 for instructing the sub-system 502 to deassert the interface valid signal Valid for a 1T period, where T is a period of the source clock used by the sub-system 502.”).
Regarding claim 16. The semiconductor device according to claim 1, wherein the second semiconductor die further includes a second transmission circuit (See Fig. 3 for 328.) and a second mask circuit (See Fig. 3 for 326.), and the second mask circuit receives second data that is output by the second transmission circuit in accordance with the second clock signal (See Fig. 3 for CLK1 and data transfer from 328 to 326.), and bypasses and outputs the second data to an outside (See Fig. 3 for data outgoing from 326 to die 0.).
Claim(s) 2 rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2016/0239444, “Chen”) in view of Tsai et al. (US 2024/0013824, “Tsai”) and further in view of Kuroki (US 2010/0115324).
Examiner’s note: in what follows, references are drawn to Chen unless otherwise mentioned.
Regarding claim 2, it is noted that while disclosing two dies transferring data, Chen does not specifically teach about lengths of operation periods based on difference between two frequencies. It, however, had been known in the art before the effective date of the instant application as shown by Kuroki as follows;
the semiconductor device according to claim 1, wherein at least one of a length of the first operation period and a length of the second operation period is set on the basis of a difference between a frequency of the first clock signal and a frequency of the second clock signal ([Kuroki, 0063] “Referring to FIG. 12, based on the effective period of the data strobe signal DQS, phase difference data P[n:0] is specified which represents a phase difference between the system clock signal SCLK and output timing of data of the serial/parallel converting circuit 24 in a clock signal domain of the data strobe signal DQS. This value is converted into a phase shift amount with respect to the system clock signal SCLK of the system clock synchronizing circuit 19 and shifts the read clock signal rclk at the position which satisfies Setup and Hold”).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of instant application to modify Chen by using the features of Kuroki in order to control measurement errors of delay time such that “memory interface circuit includes a clock signal supply buffer configured to send a system clock signal which is supplied through a reference node” [Kuroki, 0013].
Claim(s) 3 rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2016/0239444, “Chen”) in view of Tsai et al. (US 2024/0013824, “Tsai”) and further in view of Yap (US 2014/0250260).
Examiner’s note: in what follows, references are drawn to Chen unless otherwise mentioned.
Regarding claim 3, it is noted that while disclosing two dies transferring data, Chen does not specifically teach about lengths of operation periods based on a size of a buffer memory. It, however, had been known in the art before the effective date of the instant application as shown by Yap as follows;
the semiconductor device according to claim 1, wherein at least one of a length of the first operation period and a length of the second operation period is set on the basis of a size of a buffer memory that is included in the second semiconductor die and that buffers the first data ([0029] “the FIFO depth of the asynchronous FIFO buffer 315/325 depends on the maximum accumulated time interval error (e.g., |T0−T1| shown in FIG. 2).”, and [Yap, claim 18] “detecting an emptiness condition of the asynchronous FIFO buffer; and suspending the outputting of data from the asynchronous FIFO buffer in response to detecting the emptiness condition.”).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of instant application to modify Chen by using the features of Yap in order to reduce read latency such that “provide for an asynchronous first in first out (FIFO) buffer that provides data in response to requests to read a memory array.” [Yap, 0031].
Claim(s) 4 rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2016/0239444, “Chen”) in view of Tsai et al. (US 2024/0013824, “Tsai”) and further in view of Smith et al. (US 2010/0124256, “Smith”).
Examiner’s note: in what follows, references are drawn to Chen unless otherwise mentioned.
Regarding claim 4, it is noted that while disclosing two dies transferring data, Chen does not specifically teach about lengths of operation periods based on one of PVT variations. It, however, had been known in the art before the effective date of the instant application as shown by Smith as follows;
the semiconductor device according to claim 1, wherein at least one of a length of the first operation period and a length of the second operation period is set on the basis of condition information including at least one of a process, a voltage and a temperature of the first semiconductor die ([Smith, claim 16] “to control a length of the prescribed period of time as a function of at least one of a process, a supply voltage, and a temperature of the PLL.”).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of instant application to modify Chen by using the features of Smith in order to provide immune methods to PVT variations such that “methods and techniques for advantageously detecting and advantageously eliminating the occurrence of runaway in a PLL, particularly over variations in PVT conditions to which the PLL may be subjected.” [Smith, 0007].
Claim(s) 5-6 rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2016/0239444, “Chen”) in view of Tsai et al. (US 2024/0013824, “Tsai”) and further in view of Kwon (US 2012/0026806).
Examiner’s note: in what follows, references are drawn to Chen unless otherwise mentioned.
Regarding claim 5, it is noted that while disclosing two dies exchanging data, Chen does not specifically teach about lengths of operation periods based length of data. It, however, had been known in the art before the effective date of the instant application as shown by Kwon as follows;
the semiconductor device according to claim 1, wherein at least one of a length of the first operation period and a length of the second operation period is set on the basis of a length of the first data ([Kwon, 0039] “The transmission control signal generation block 30 is configured to generate a transmission control signal T_CON in response to a set level of the data strobe signal DQS, wherein the enable time point of the transmission control signal T_CON may be adjusted.”).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of instant application to modify Chen by using the features of Kwon in order to reduce errors in writing operations such that “a data input circuit capable of substantially preventing an error in a write operation by accurately detecting the final falling edge of a data strobe signal” [Kwon, 0011].
Regarding claim 6, the semiconductor device according to claim 1, wherein at least one of a length of the first operation period and a length of the second operation period is variable ([Kwon, 0039] “The transmission control signal generation block 30 is configured to generate a transmission control signal T_CON in response to a set level of the data strobe signal DQS, wherein the enable time point of the transmission control signal T_CON may be adjusted.”).
The rational and motivation for adding this teaching of Kwon are the same as for claim 5.
Claim(s) 8 rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2016/0239444, “Chen”) in view of Tsai et al. (US 2024/0013824, “Tsai”) and further in view of Park et al. (US 2022/0343955, “Park”).
Examiner’s note: in what follows, references are drawn to Chen unless otherwise mentioned.
Regarding claim 8, it is noted that while disclosing two dies exchanging data, Chen does not specifically teach about alternating periods. It, however, had been known in the art before the effective date of the instant application as shown by Park as follows;
the semiconductor device according to claim 1, wherein the first operation period and the second operation period alternate ([Park, 0029] “by setting an offset period of a non-target rank depending on a data reception delay period of a target rank performing a write operation, it may be possible to optimize a period in which a termination operation is performed in a write operation alternately performed between ranks.”).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of instant application to modify Chen by using the features of Park in order to reduce impedance mismatch at high speed such that “an enable signal generation circuit configured to activate, when a write operation is performed, a termination enable signal earlier than a time point when a write latency elapses, by a duration amount of an entry offset period” [Park, 0004].
Claim(s) 10 rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2016/0239444, “Chen”) in view of Tsai et al. (US 2024/0013824, “Tsai”) and further in view of Cheng et al. (US 2024/0086087, “Cheng”).
Examiner’s note: in what follows, references are drawn to Chen unless otherwise mentioned.
Regarding claim 10, it is noted that while disclosing two dies exchanging data, Chen does not specifically teach about a transmission ready signal. It, however, had been known in the art before the effective date of the instant application as shown by Cheng as follows;
the semiconductor device according to claim 1, wherein the first mask circuit outputs a transmission ready signal to the first transmission circuit before the first operation period starts ([Cheng, 0043] “The predetermined time duration can be also configured so that transmission of the read enable signal is initiated before the data is ready for transmission.”).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of instant application to modify Chen by using the features of Cheng in order to support effective data transfer such that “a read enable signal from the controller to the semiconductor device when a predetermined time duration elapses after the controller sends instructions to the semiconductor device” [Cheng, 0002].
Claim(s) 12 rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2016/0239444, “Chen”) in view of Tsai et al. (US 2024/0013824, “Tsai”) and further in view of Kinoshita et al. (US 2009/0290445, “Kinoshita”).
Examiner’s note: in what follows, references are drawn to Chen unless otherwise mentioned.
Regarding claim 12, it is noted that while disclosing two dies exchanging data, Chen does not specifically teach about two counters for two separate periods. It, however, had been known in the art before the effective date of the instant application as shown by Kinoshita as follows;
the semiconductor device according to claim 1, wherein the first mask circuit comprises: a first counter configured to operate during the first operation period on the basis of a valid signal that is received together with the first data; and a second counter configured to operate during the second operation period ([Kinoshita, claim 1] “a first counter circuit including a plurality of latch circuits for sequentially shifting the normal-phase command signal based on the normal-phase clock; a second counter circuit including a plurality of latch circuits for sequentially shifting the reverse-phase command signal based on the reverse-phase clock; a selector circuit for selectively controlling a signal path so that when an even latency is set, the normal-phase command signal is transmitted through the first counter circuit while the reverse-phase command signal is transmitted through the second counter circuit,”).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of instant application to modify Chen by using the features of Kinoshita in order to effectively suppress constant current flowing such that “a configuration in which consumption current can be sufficiently suppressed when using a high-speed external clock” [Kinoshita, 0008].
Claim(s) 13 rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2016/0239444, “Chen”) in view of Tsai et al. (US 2024/0013824, “Tsai”) and Kinoshita et al. (US 2009/0290445, “Kinoshita”), and further in view of Takaki (US 2017/0262393).
Examiner’s note: in what follows, references are drawn to Chen unless otherwise mentioned.
Regarding claim 13, it is noted that while disclosing two dies exchanging data, Chen does not specifically teach about a second counter in a second operation. It, however, had been known in the art before the effective date of the instant application as shown by Takaki as follows;
the semiconductor device according to claim 12, wherein the second counter operates without the valid signal during at least a part of the second operation period ([Takaki, 0088] “a configuration in which consumption current can be sufficiently suppressed when using a high-speed external clock”).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of instant application to modify Chen by using the features of Takaki in order to effectively manage internal time during multiple modes such that “The RTOS causes the processor to update internal time during a first mode and to stop updating in a second mode.” [Takaki, Abstract].
Claim(s) 20 rejected under 35 U.S.C. 103 as being unpatentable over Yap (US 2014/0250260) in view of Chen et al. (US 2016/0239444, “Chen”), and further in view of Tsai et al. (US 2024/0013824, “Tsai”).
Examiner’s note: in what follows, references are drawn to Chen unless otherwise mentioned.
Regarding claim 20, a data storage system (See Fig. 2.) comprising:
at least one memory device (See Fig.2 for 202 “Memory Chip”); and
a controller (See Fig. 2 for 205 “Controller”) configured to control an operation of the at least one memory device.
It is noted that while disclosing a memory device, Yap does not specifically teach about two dies. It, however, had been known in the art before the effective date of the instant application as shown by Chen as follows;
a first chiplet ([Chen, 0023, Fig. 1 and Fig. 3] “A single package 300 has multiple dies, including at least a first die (denoted by “Die 0”) 302 and a second die (denoted by “Die 1”) 304”) including a mask circuit (See [Chen, Fig. 3] for 316.) that receives data ([Chen, Fig. 3 and 0026] “The output circuit 316 is used to transfer transmit data (which is generated by the sub-system 318) to the second die 304”) in accordance with a first clock signal (See [Chen, Fig. 3] for 316 is functioning with CLK0.), outputs the data to an outside (See [Chen, Fig. 3] for data transfer from 316 to 324.) during a first operation period ([Chen, 0031 and Fig. 4] “the interface valid signal Valid with a 1T active period allows one data transfer between the sub-system 402 and the asynchronous FIFO buffer 404, where T is a period of the source clock used by the sub-system 402.”), and stops output of the data during a second operation period ([Chen, 0032 and Fig. 4] “When the sub-system 402 enters the wait state, the interface valid signal Valid is deasserted (inactive) and the data transfer between the sub-system 402 and the asynchronous FIFO buffer 404 is stopped”. Note that Chen’s disclosure is its flow-control arrangement in which a TX-side controller causes a wait state and inactivates a valid signal so that data transfer is stopped. This will be further clarified in view of Tsai.); and
a second chiplet ([Chen, 0023, Fig. 1 and Fig. 3] “A single package 300 has multiple dies, including at least a first die (denoted by “Die 0”) 302 and a second die (denoted by “Die 1”) 304”) including a buffer memory that receives and stores the data (See [Chen, Fig. 3] for 325, and [Chen, 0027] “the input circuit 324 of the second die 304 also has an asynchronous FIFO buffer 325”), and a reception circuit that reads the data stored in the buffer memory in accordance with a second clock signal that is different from the first clock signal ([Chen, 0028] “outputs the buffered transmit data in the asynchronous FIFO buffer 325 to the sub-system 328 according to the second clock CLK1 generated at the second die 304.”).
It is noted that while disclosing a memory device, Yap does not specifically teach about a block enabling and disabling transmissions during time periods. It, however, had been known in the art before the effective date of the instant application as shown by Tsai as follows;
outputs the data to an outside during a first operation period ([Tsai, 0070] “The first four clock cycles of the write clock gating enabling signal WGE, each labeled as 1, correspond to the enabling section.”); and
stops output of the data during a second operation period ([Tsai, 0072] “The rest two clock cycles of each of the read clock gating enabling signals RGE.sub.1˜RGE.sub.K, each labeled as 0, are used to disable the transmission”), wherein the mask circuit controls an output timing of the data output to the outside at a transmission frequency that differs from a frequency of the first clock signal ([Tsai, 0072] “The first four clock cycles of each of the read clock gating enabling signals RGE.sub.1˜RGE.sub.K, each labeled as 1, correspond to the enabling section. The rest two clock cycles of each of the read clock gating enabling signals RGE.sub.1˜RGE.sub.K, each labeled as 0, are used to disable the transmission of one of the read clock signals RCK.sub.1˜RCK.sub.K.” Note that the claimed first clock signal and output clock are equivalent to the cited read clock signal RCK and the gating clock, respectively. See [Tsai, 0066] “an enable section of each of the read clock gating enabling signals RGE.sub.1˜RGE.sub.K, which is a high state section, controls each of the read clock gating circuits 130 to transmit four clock cycles of the read clock signals RCK.sub.1˜RCK.sub.K to each of the data transmission circuits 110 labeled as DT.sub.1˜DT.sub.K.”).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of instant application to modify Yap by using the features of Tsai in order to control transmission timing between different time domains and reduce transfer failure such that “a data transmission apparatus having clock gating mechanism that includes a plurality of data transmission circuits, a write clock gating circuit, a plurality of read clock gating circuits and a gating signal transmission circuit.” [Tsai, 0007].
Allowable Subject Matter
Regarding claim 14-15 and 17-18, said claims were objected with allowable subject matter in the previous office action dated 05/19/2026 with reasons for allowance given then, and said claims remain objected now.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Harry H. Kim whose telephone number and email address are as follows; 571-272-5009, harry.kim2@uspto.gov.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Derrick Ferris can be reached at 571-272-3123.
Information regarding the status of an application may be obtained from www.uspto.gov. For questions or assistance, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (in USA or Canada) or 571-272-1000.
/HARRY H KIM/ Primary Examiner, Art Unit 2411
Prosecution Insights