DETAILED ACTION
1. This office action is in the reply to an application (application No. 18/747,396) filed on June 18, 2024. Claims 1-20 are submitted for examination. Claims 1, 15 and 18 are independent.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
3. This application filed on 06/18/2024 claims foreign priority to 10-2024-0011291, filed on 01/25/2024.
Information Disclosure Statement
4. The information disclosure statements (IDS) submitted on June 18, 2024 have been considered. The submission is in-compliance with the provisions of 37 CFR 1.97. Form PTO-1449 is signed and attached hereto.
Drawings
5. The drawings filed on June 18, 2024 are accepted.
Specification
6. The specification filed on June 18, 2024 is also accepted.
Internet Communications
7. Applicant is encouraged to submit a written authorization for Internet communications (PTO/SB/439, http:/www.uspto.gov/sites/default/files/documents/sb0439.pdf) in the instant patent application to authorize the examiner to communicate with the applicant via email. The authorization will allow the examiner to better practice compact prosecution. See MPEP § 502.03.
Claim Rejections - 35 USC § 101
8. 35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
9. Claims 15-17 are rejected under 35 U.S.C. 101 because the claimed invention is directed
to non-statutory subject matter.
Regarding independent Claim 15, the claim is directed to an apparatus or device claim. In particular the preamble recites “a control device”. However, the body of the claim does not include at least one explicit hardware element (e.g. physical memory, a hardware processor, physical node, etc.). Examiner note that pending claims are interpreted as broadly as their terms reasonably allow. The broadest reasonable interpretation of a claim limitation such as, a random number generator, a key generator and an encryption engine could cover software per se only, in view of the ordinary and customary meaning of the term generator. An apparatus/system/device claim consisting of only pure software elements, without a tie to a specific, tangible machine, is generally considered non-statutory and is (ineligible) for patent protection. Therefore, the claim is not directed to any of the statutory categories and is not patent-eligible subject matter and is non-statutory under 35 U.S.C. § 101. The office suggests adding explicit physical or hardware elements such as (memory, hardware processors or microprocessor) would overcome this rejection.
Dependent claims 16-17 depend on rejected Claim 15, and carry the deficiencies of the parent claim 1. They are likewise rejected for the same reasons.
Claim Rejections - 35 USC § 102
10. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
11. Claims 1, 18-20 are rejected under 35 U.S.C. 102 (a)(1) and/or 102 (a)(2) as being anticipated by Thomas E. Tkacik (herein after referred as Tkacik) (US Publication No. 2022/0350503A1; Pub. Date: Nov. 3, 2022)
The following is referring to independent claims 1 and 18:
As per independent claim 1, Tkacik discloses a data storage system [Figure 1 ref. 120 and 130, a memory controller 120 with an IEE 125, and a memory 130 and para. 0019, a memory interface connected to a memory. Para. 0038, The memory controller 200 may receive address and other command information on an address channel 240. The data to be written to the DRAM is received on the write data channel 242. The data to be read from the DRAM is output on the read data channel 244.]
comprising:
a memory device [Figure 1, Ref. 130, memory and DDRM, para. 0019, a memory interface connected to a memory and Para. 0038, …DRAM]
and a control device configured to control an operation of the memory device [ Figure 1, Ref. 120, the memory controller 120. And Figure 2, Memory Controller 200, Para. 0038, “the memory controller 200 may receive address and other command information on an address channel 240. The data to be written to the DRAM is received on the write data channel 242. The data to be read from the DRAM is output on the read data channel 244”. Para. 0019, “a memory controller, including: a memory interface connected to a memory; an address and control logic connected to the memory interface and a command interface, wherein the address and control logic is configured to receive a memory access request and a write memory request. Examiner Note: The memory controller controls operation such as Read and Write on the memory device DRAM]
generate at least one timed key on the basis of a period of a scrub operation of the memory device [Para. 0044, “memory scrubber 230 may be used in order to drive the update the keys for each region of the memory”, …“When a key update is to occur, a new key is generated for each memory region” and Para. 0043, The memory scrubber 230 cycles through the memory refreshing the whole memory periodically. The rate at which the memory is refreshed is based upon the size of the memory and the availability of time to perform the refresh operation. The time to completely scrub the memory may be on the order of hours, but other rates are possible as well. Examiner Note: a new timed Key which is periodically updated and is generated when a key update occurs. A key update is driven by the memory scrubber and the scrubber operates periodically (over a period of time) and this meets the limitation “generate at least one timed key on the basis of a period of a scrub operation of the memory device”], and perform, by using the at least one timed key, encryption on data to be written to the memory device or decryption on data written to the memory device [Para. 0018, encrypt the decrypted stored data using a new first key; store the data encrypted with the new first key; decrypt the stored data using the first key. Note As shown on para. 0043-0044; The new first key is a timed key that is generated periodically when key update is executed and the key update is driven by the memory scrubber]
As per independent claim 18, Tkacik discloses a memory device [Figure 1, Ref. 130, memory and DDRM, para. 0019, a memory interface connected to a memory and Para. 0038, …DRAM] comprising: a memory cell array including a plurality of memory cells [ DDRM or dynamic RAM . Note: DDRM or dynamic RAM comprises of a vast plurality of memory cells, each a tiny capacitor and transistor (1T1C), arranged in massive two-dimensional arrays (rows and columns) on a chip to store binary data]; and a memory controller configured to control an operation of the memory cell array [ Figure 1, Ref. 120, the memory controller 120. And Figure 2, Memory Controller 200, Para. 0038, “the memory controller 200 may receive address and other command information on an address channel 240. The data to be written to the DRAM is received on the write data channel 242. The data to be read from the DRAM is output on the read data channel 244”. Para. 0019, “a memory controller, including: a memory interface connected to a memory; an address and control logic connected to the memory interface and a command interface, wherein the address and control logic is configured to receive a memory access request and a write memory request. Examiner Note: The memory controller controls operation such as Read and Write on the memory device DRAM], generate at least one timed key on the basis of a period of a scrub operation for the memory cell array [Para. 0044, “memory scrubber 230 may be used in order to drive the update the keys for each region of the memory”, …“When a key update is to occur, a new key is generated for each memory region” and Para. 0043, The memory scrubber 230 cycles through the memory refreshing the whole memory periodically. The rate at which the memory is refreshed is based upon the size of the memory and the availability of time to perform the refresh operation. The time to completely scrub the memory may be on the order of hours, but other rates are possible as well. Examiner Note: a new timed Key which is periodically updated is generated when a key update occurs and a key update is driven by the memory scrubber and the scrubber operates periodically (over a period of time) and this meets the limitation “generate at least one timed key on the basis of a period of a scrub operation of the memory device/memory cell array”], and perform, using the at least one timed key, encryption or decryption on data to be written to the memory cell array[Para. 0018, encrypt the decrypted stored data using a new first key; store the data encrypted with the new first key; decrypt the stored data using the first key. Note As shown on para. 0043-0044; The new first key is a timed key that is generated periodically when key update is executed and the key update is driven by the memory scrubber]
The following is referring to dependent claims 19-20:
As per dependent claim 19, Tkacik discloses a memory device as applied to claim 18 above. Furthermore, Tkacik discloses the memory device wherein during a period of time corresponding to the period of the scrub operation [Para. 0044, “memory scrubber 230 may be used in order to drive the update the keys for each region of the memory”, …“When a key update is to occur, a new key is generated for each memory region” and Para. 0043, The memory scrubber 230 cycles through the memory refreshing the whole memory periodically. The rate at which the memory is refreshed is based upon the size of the memory and the availability of time to perform the refresh operation. The time to completely scrub the memory may be on the order of hours, but other rates are possible as well. Examiner Note: a new timed Key which is periodically updated is generated when a key update occurs and a key update is driven by the memory scrubber and the scrubber operates periodically (over a period of time) and this meets the limitation “generate at least one timed key on the basis of a period of a scrub operation of the memory device], the memory controller performs the encryption or the decryption using a first timed key on data of a memory cell on which the scrub operation has not been performed [Para. 0044, The scanning function of the memory scrubber 230 may be used in order to drive the update the keys for each region of the memory. FIG. 3 illustrates memory regions and their associated keys. The memory 300 includes region 1 310, region 2 320, and region 3 330. The memory may include any number of regions based upon the specific application. Each region may have an old key and a new key. A water level or key update location 340 indicates a boundary between data that is encrypted with the new key and the old key. The memory scrubber 230 moves the location of the key update location 340 as data in the memory is encrypted with the new key. If a key refresh has been indicated, then the data in the location is decrypted using the old key and then re-encrypted using the new key. Then the key update location 340 is moved. This process repeats itself as the memory scrubber 230 scans through the memory checking for and correcting errors. Para. 0045. the key selector 215 determines whether the old key or the new key should be used for decryption/encryption of the data. First the key selector 215 determines the region associated with the address of the data….the key selector 215 decides whether the address to be accessed is “above” or “below” the key update location 340. Note: the memory regions not yet reached by the scrubber (i.e. addresses below the key update location) continue to use the old key/the first timed key. Those region corresponds to memory cells on which the scrub operation has not yet been performed.] and performs the encryption or the decryption using a second timed key on data of a memory cell on which the scrub operation has been performed [Para. 0044, “When a key update is to occur, a new key is generated for each memory region”, para. 0018, decrypt the stored data using the first key; encrypt the decrypted stored data using a new first key; store the data encrypted with the new first key;… key update location indicates a boundary between data stored in the memory encrypted using the first/old key and the new first key/second timed key]
As per dependent claim 20, Tkacik discloses a memory device as applied to claim 18 above. Furthermore, Tkacik discloses the memory device wherein when the period of time corresponding to the scrub operation ends and a period of time corresponding to a new period starts [Para. 0043, The memory scrubber 230 cycles through the memory refreshing the whole memory periodically. The rate at which the memory is refreshed is based upon the size of the memory and the availability of time to perform the refresh operation. The time to completely scrub the memory may be on the order of hours, but other rates are possible as well. Note, this teaches that the scrubbing is periodic meaning that: a first scrub cycle (period) completes and a subsequent scrub cycle (second period) begins. Thus successive scrub periods corresponds to the claimed “time period” and a “new time period”], during the period of time corresponding to the new period [Para. 0043, The memory scrubber 230 cycles through the memory refreshing the whole memory periodically. Note: repeated scrub cycles, operations occurring during subsequent scrub cycle occur corresponds to the new period] the memory controller performs the encryption or the decryption using the second timed key on data of a memory cell [[Para. 0044, “When a key update is to occur, a new key is generated for each memory region”, para. 0018, decrypt the stored data using the first key; encrypt the decrypted stored data using a new first key; store the data encrypted with the new first key;… key update location indicates a boundary between data stored in the memory encrypted using the first/old key and the new first key/second timed key] on which the scrub operation has not been performed [[Para. 0044, The scanning function of the memory scrubber 230 may be used in order to drive the update the keys for each region of the memory. FIG. 3 illustrates memory regions and their associated keys. The memory 300 includes region 1 310, region 2 320, and region 3 330. The memory may include any number of regions based upon the specific application. Each region may have an old key and a new key. A water level or key update location 340 indicates a boundary between data that is encrypted with the new key and the old key. The memory scrubber 230 moves the location of the key update location 340 as data in the memory is encrypted with the new key. If a key refresh has been indicated, then the data in the location is decrypted using the old key and then re-encrypted using the new key. Then the key update location 340 is moved. This process repeats itself as the memory scrubber 230 scans through the memory checking for and correcting errors. Para. 0045. the key selector 215 determines whether the old key or the new key should be used for decryption/encryption of the data. First the key selector 215 determines the region associated with the address of the data….the key selector 215 decides whether the address to be accessed is “above” or “below” the key update location 340. Note: the memory regions not yet reached by the scrubber (i.e. addresses below the key update location) continue to use the old key/the first timed key. Those region corresponds to memory cells on which the scrub operation has not yet been performed.]and performs the encryption or the decryption using a third timed key on data of a memory cell on which the scrub operation has been performed [Para. 0044, “When a key update is to occur, a new key is generated for each memory region”, para. 0018, decrypt the stored data using the first key; encrypt the decrypted stored data using a new first key; store the data encrypted with the new first key;… key update location indicates a boundary between data stored in the memory encrypted using the first/old key and the new first key/third timed key. Note: This teaches memory cells on which the scrub operation ha been performed (i.e. those beyond the key update location) are encrypted using the current new key. When a subsequent key update occurs, the new kye is replaced by anther newly generated key-i.e. third timed key which is then used for scrubbed memory cells]
Claim Rejections - 35 USC § 103
12. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
13. Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Thomas E. Tkacik (herein after referred as Tkacik) (US Publication No. 2022/0350503A1; Pub. Date: Nov. 3, 2022)
in view of Ignazio Antonino Urzi (herein after referred as Urzi) (US Publication No. 20150358300 A1; Pub. Date: Dec. 10, 2015)
As per dependent claim 11, Tkacik discloses a memory device as applied to claim 1 above. Tkackik further discloses a control device wherein the control device performs the encryption and the decryption [Para. 0018, decrypt the stored data using the first key; encrypt the decrypted stored data using a new first key; store the data encrypted with the new first key;… key update location indicates a boundary between data stored in the memory encrypted using the first/old key and the new first key/second timed key. Para. 0019, write IEE is configured to encrypt data to be stored in the memory and read IEE is configured to decrypt encrypted data read from the memory] using a final key [Para. 0044, Each region may have an old key and a new key. Para. 0042, The key logic 214 provides the correct keys to the write IEE 210 and read IEE 212. Note: the encryption/decryption engines operate using a selected operative key supplied by key logic. The operative key corresponds to the claim limitation “final key”]
Tkacik teaches key replacement (old keys by the new keys) but doesn’t explicitly disclose the limitation: “final key that is generated using a fixed key corresponding to a fixed value and at least one timed key”
However, Uriz discloses: “final key that is generated using a fixed key corresponding to a fixed value and at least one timed key” [Para. 0082, Once the complete memory is written by the new key, the old key is reloaded with new values from a random number generator and a key swap is done, i.e., the old key becomes the new key and the new key as the old key. and para. 0088, “Once the kicker pointer reaches location N, the old key is no longer useful and is replaced by a new random key generated, for example, from a random number generator and a key swap is done.” and Para. 0079, “The kicker mechanism (read followed by write) is responsible for periodic key changes in order to increase the security level in case a memory location remains unwritten for too long” Examiner Note: the above key generation model involving a persistent) old/fixed timed key and a periodically refreshed timed key, both of which are used in the encryption/decryption process. This meets the limitation, “generation an operational (final/new) key using both the a fixed/old key and a timed key]
Tkacik and Urzi are analogous arts and are in the same field of endeavor as they both pertain and directed to a memory controller
It would have been obvious to one having ordinary skill in the art, before the effective filing of the claimed invention, to modify the system of Tkacik, to implement generation of operational or fixed key such as , “final key that is generated using a fixed key corresponding to a fixed value and at least one timed key” as taught by Urzi because this would enhance the security of the system by being compliant with the latest generation of security and encrypt sensitive data stored in external memories. [Urzi, Para. 0008, in order to be compliant with the latest generation of security requirements, it may be desirable to encrypt sensitive data stored in external memories, such as secured code and compressed video, for example]
14. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Thomas E. Tkacik (herein after referred as Tkacik) (US Publication No. 2022/0350503A1; Pub. Date: Nov. 3, 2022)
in view of Carlos J. Gonzalez (herein after referred as Gonzalez) (US Publication No. 20110055468 A1, Pub. Date: March 3, 2011)
As per dependent claim 12, Tkacik discloses a memory device as applied to claim 1 above. Furthermore, Tkackik discloses a control device, wherein the control device generates the timed key [Para. 0044, When a key update is to occur, a new key is generated for each memory region., “The scanning function of the memory scrubber 230 may be used in order to drive the update the keys for each region of the memory”. Para. 0043, The memory scrubber 230 may simply cycle through the memory in a sequential order. When a memory location is to be refreshed, the memory scrubber 230 sends a refresh request to the address/command logic 232….”the memory scrubber 230 cycles through the memory refreshing the whole memory periodically. The rate at which the memory is refreshed is based upon the size of the memory and the availability of time to perform the refresh operation. The time to completely scrub the memory may be on the order of hours, but other rates are possible as well” Note: This teaches that the control device generates new encryption key/timed key and that key generation is driven by the memory scrubber]Para. 0043, The memory scrubber 230 may simply cycle through the memory in a sequential order. When a memory location is to be refreshed, the memory scrubber 230 sends a refresh request to the address/command logic 232….”the memory scrubber 230 cycles through the memory refreshing the whole memory periodically. The rate at which the memory is refreshed is based upon the size of the memory and the availability of time to perform the refresh operation. The time to completely scrub the memory may be on the order of hours, but other rates are possible as well. Note: This teaches that the scrub operation has a defined period i.e. a complete scrub cycle with a measurable duration].
Tkacik teaches periodic scrubbing and key updates and time key generation but doesn’t explicitly disclose subdividing the scrub period into fractional sub period (1/ M) or Tkacik doesn’t explicitly discloses the following underlined claim limitation: “generate the timed key in each period of time corresponding to 1/M (where M is an integer satisfying M>=1) of the period of the scrub operation of the memory device”
However, Gonzalez explicitly discloses the underlined claim limitation: “generate the timed key in each period of time corresponding to 1/M (where M is an integer satisfying M>=1) of the period of the scrub operation of the memory device” [Para. 0078, the scrubs may be performed at some regular time interval, T, where T is a parameter provided to set the rate of scrub and para. 0077 also teaches fractional scrub rates: such as 1/1’ ½’ 4/4; 4/8; …1/256. This meets configuring scrub operations to occur at fractional portion (1/M) of the base scrub period where M is an integer >=1]
Tkacik and Gonzalez re analogous arts and are in the same field of endeavor as they both pertain and directed to memory scrubbing.
It would have been obvious to one having ordinary skill in the art, before the effective filing of the claimed invention, to modify the system of Tkacik, to implement a fractional scrub rate such as, “in each period of time corresponding to 1/M (where M is an integer satisfying M>=1) of the period of the scrub operation of the memory device” as taught by Gonzalez because this would enhance the security of the system by knowing when/how to make the decision to perform a scrub or not for scanning through the memory and correcting data errors [See Gonzalez, at least para. 0077, The decision to perform a scrub or not would be based on whether the RN exceeded the threshold value numerically. For example, for a threshold value of 5, the RN would be higher 5/256 of the time]
15. Claims 13 is rejected under 35 U.S.C. 103 as being unpatentable over (herein after referred as Tkacik) (US Publication No. 2022/0350503A1; Pub. Date: Nov. 3, 2022) in view of Avila et al (Avila) (US Publication No. 2013/0128666 A1, Pub. Date: May 23, 2013)
As per dependent claim 13, Tkacik discloses a memory device as applied to claim 1 above. Tkackik further discloses a control device configured to control an operation of the memory device [ Figure 1, Ref. 120, the memory controller 120. And Figure 2, Memory Controller 200, Para. 0038, “the memory controller 200 may receive address and other command information on an address channel 240. The data to be written to the DRAM is received on the write data channel 242. The data to be read from the DRAM is output on the read data channel 244”. Para. 0019, “a memory controller, including: a memory interface connected to a memory; an address and control logic connected to the memory interface and a command interface, wherein the address and control logic is configured to receive a memory access request and a write memory request. Examiner Note: The memory controller controls operation such as Read and Write on the memory device DRAM]
Tkacik doesn’t explicitly disclose the limitation: “wherein the control device comprises a random number generator that provides a random number for the period of the scrub operation of the memory device”
However, Avila explicitly discloses the underlined claim limitation: “a random number generator configured to provide a random number for a period of a scrub operation of a memory device” [Para. 0068, use random numbers (RN) or pseudo-random numbers (PRN) to determine the frequency of scrub operations if they are available to the system, or generated by the system. A number of methods are described below for using an RN or PRN sequence to decide whether or not to perform a scrub operation. All of the below methods assume the RN is being checked at some regular interval, and the decision to perform the scrub or not is based on some test of the RN value and 0045, In general, the scrub operation can be initiated in response to any number of factors, such as a number of host operations, a number of physical read, write and/or erase operations, a time period, usage characteristics of the host, or some random or pseudo-random sequence, the generating and checking of which may be tied to any of the above Para.0051, Scrubbing may be controlled by the memory system controller .]
Tkacik and Avila are analogous arts and are in the same field of endeavor as they both pertain and directed to a memory controller.
It would have been obvious to one having ordinary skill in the art, before the effective filing of the claimed invention, to modify the system of Tkacik, to implement scrub operation timing controlled by the random number generator such as, “a random number generator configured to provide a random number for a period of a scrub operation of a memory device” as taught by Avila because this would enhance the security of the system by scanning through the memory and correcting data errors without impacting the performance of the host. [See Avila, at least para. 0072, performing the scrub would not impact performance to the host. The scrub operations may be deferred until sometime later in the host command processing, sometime after the command processing, or until a later host command. In such a case, the scrub operation parameters that have been decided upon are stored and processed at a later time when it is most convenient to the host. Note address above the key update location that corresponds to the address regions already processed by the scrubber are decrypted with the old key/the first timed key and re-encrypted using the new key/second timed key]
16. Claims 14 is rejected under 35 U.S.C. 103 as being unpatentable over Thomas E. Tkacik (herein after referred as Tkacik) (US Publication No. 2022/0350503A1; Pub. Date: Nov. 3, 2022)
in view of Avila et al (Avila) (US Publication No. 2013/0128666 A1, Pub. Date: May 23, 2013) and further in view of Ignazio Antonino Urzi (herein after referred as Urzi) (US Publication No. 20150358300 A1; Pub. Date: Dec. 10, 2015)
As per dependent claim 14 the combination of Tkacik and Avila discloses a memory device as applied to claim 13 above. Tkackik further discloses a control device configured to control an operation of the memory device [ Figure 1, Ref. 120, the memory controller 120. And Figure 2, Memory Controller 200, Para. 0038, “the memory controller 200 may receive address and other command information on an address channel 240. The data to be written to the DRAM is received on the write data channel 242. The data to be read from the DRAM is output on the read data channel 244”. Para. 0019, “a memory controller, including: a memory interface connected to a memory; an address and control logic connected to the memory interface and a command interface, wherein the address and control logic is configured to receive a memory access request and a write memory request. Examiner Note: The memory controller controls operation such as Read and Write on the memory device DRAM]
The combination of Tkacik and Avila doesn’t explicitly disclose the limitation: “wherein the control device comprises a key generator that generates the at least one timed key on the basis of the random number and an encryption engine that encrypts data to be written to the memory device using the at least one timed key”
However, Urzi discloses: the control device [Figure 1, a memory controllers 13 1, and 13 2 and Local Controllers 151 1, and 152 2. Para. 0053, Each channel CHi comprises a memory controller 13 1 connected to a memory interface 14 1 coupled to the corresponding external memory 2 1] comprises:
a key generator configured to generate at least one timed key [Para. 0026, 0079 and 0086 indicates how new timed encryption key is periodically generated replacing the old encryption key based on time-out periods, Para. 0026, generating the new encryption key from at least the selected new primary key, Para. 0079, The kicker mechanism (read followed by write) is responsible for periodic key changes in order to increase the security level in case a memory location remains unwritten for too long. At any instant of time, two random keys (old and new) are being used by the encryptor/decryptor. Internally, a memory pointer is maintained which acts as a reference for key usage. In case the pointer location is not written by system traffic (i.e., the master elements) for a time period called the “time out period,” the kicker mechanism performs a read to this location with the old key, writes the data back with the new key thus guaranteeing the key change, and increments the pointer. Once the complete memory is written by the new key, the old key is reloaded with new values from a random number generator and a key swap is done, i.e., the old key becomes the new key. Para. 0086, If the pointer PNT does not move during the time out period, the kicker process will perform read from location 3, the data being decrypted with the old key, and write data back in the same location 3 encrypted with the new key, and then increment pointer to location 4] on the basis of the random number Para. 0082, “Once the complete memory is written by the new key, the old key is reloaded with new values from a random number generator and a key swap is done, i.e., the old key becomes the new key and the new key as the old key;” and para. 0088, “Once the kicker pointer reaches location N, the old key is no longer useful and is replaced by a new random key generated, for example, from a random number generator and a key swap is done.”] and
an encryption engine configured to encrypt data to be written to the memory device using the at least one timed key [Para. 0079, The kicker mechanism (read followed by write) is responsible for periodic key changes in order to increase the security level in case a memory location remains unwritten for too long and Para. 0026, teaches decryption with the old (timed key) and encryption using a new (timed) key, “encrypting data to be stored within a memory bank and decrypting data to be read from a memory bank and upon reception at a channel of a specific transaction (kicker transaction/timed out) having been initiated by the channel, the method includes reading the data located at the current address and encrypted with a previous encryption key, decrypting the encrypted data with previous encryption key, selecting a new primary key, generating the new encryption key from at least the selected new primary key, re-encrypting the decrypted data with the new encryption key and rewriting the re-encrypted data at the current address]
Tkacik, Avila and Urzi are analogous arts and are in the same field of endeavor as they all pertain and directed to a memory controller.
It would have been obvious to one having ordinary skill in the art, before the effective filing of the claimed invention, to modify the system of Tkacik and Avila, to implement encryption or decryption using a timed key generated on the basis of a random number, such as “wherein the control device comprises a key generator that generates the at least one timed key on the basis of the random number and an encryption engine that encrypts data to be written to the memory device using the at least one timed key” as taught by Urzi because this would enhance the security of the system by being compliant with the latest generation of security and encrypt sensitive data stored in external memories. [Urzi, Para. 0008, in order to be compliant with the latest generation of security requirements, it may be desirable to encrypt sensitive data stored in external memories, such as secured code and compressed video, for example]
17. Claim 15-16 is rejected under 35 U.S.C. 103 as being unpatentable over Ignazio Antonino Urzi (herein after referred as Urzi) (US Publication No. 20150358300 A1; Pub. Date: Dec. 10, 2015) in view of Avila et al (Avila) (US Publication No. 2013/0128666 A1, Pub. Date: May 23, 2013)
The following is referring to independent claim 15:
As per independent claim 15, Urzi discloses a control device [Figure 1, a memory -controllers 13 1, and 13 2 and Local Controllers 151 1, and 152 2. Para. 0053, Each channel CHi comprises a memory controller 13 1 connected to a memory interface 14 1 coupled to the corresponding external memory 2 1] and comprising:
a random number generator configured to provide a random number [Para. 0082, Once the complete memory is written by the new key, the old key is reloaded with new values from a random number generator and a key swap is done, i.e., the old key becomes the new key and the new key as the old key]
a key generator configured to generate at least one timed key [Para. 0026, 0079 and 0086 indicates how new timed encryption key is periodically generated replacing the old encryption key based on time-out periods, Para. 0026, generating the new encryption key from at least the selected new primary key, Para. 0079, The kicker mechanism (read followed by write) is responsible for periodic key changes in order to increase the security level in case a memory location remains unwritten for too long. At any instant of time, two random keys (old and new) are being used by the encryptor/decryptor. Internally, a memory pointer is maintained which acts as a reference for key usage. In case the pointer location is not written by system traffic (i.e., the master elements) for a time period called the “time out period,” the kicker mechanism performs a read to this location with the old key, writes the data back with the new key thus guaranteeing the key change, and increments the pointer. Once the complete memory is written by the new key, the old key is reloaded with new values from a random number generator and a key swap is done, i.e., the old key becomes the new key. Para. 0086, If the pointer PNT does not move during the time out period, the kicker process will perform read from location 3, the data being decrypted with the old key, and write data back in the same location 3 encrypted with the new key, and then increment pointer to location 4] on the basis of the random number [Para. 0082, “Once the complete memory is written by the new key, the old key is reloaded with new values from a random number generator and a key swap is done, i.e., the old key becomes the new key and the new key as the old key;” and para. 0088, “Once the kicker pointer reaches location N, the old key is no longer useful and is replaced by a new random key generated, for example, from a random number generator and a key swap is done.”] and
an encryption engine configured to encrypt data to be written to the memory device using the at least one timed key [Para. 0079, The kicker mechanism (read followed by write) is responsible for periodic key changes in order to increase the security level in case a memory location remains unwritten for too long and Para. 0026, teaches decryption with the old (timed key) and encryption using a new (timed) key, “encrypting data to be stored within a memory bank and decrypting data to be read from a memory bank and upon reception at a channel of a specific transaction (kicker transaction/timed out) having been initiated by the channel, the method includes reading the data located at the current address and encrypted with a previous encryption key, decrypting the encrypted data with previous encryption key, selecting a new primary key, generating the new encryption key from at least the selected new primary key, re-encrypting the decrypted data with the new encryption key and rewriting the re-encrypted data at the current address. Note As shown on para. 0043-0044; The new first key is a timed key that is generated periodically when key update is executed and the key update is driven by the memory scrubber.]
Urzi doesn’t explicitly disclose the following underlined claim limitation: “a random number generator configured to provide a random number for a period of a scrub operation of a memory device”
However, Avila explicitly discloses the underlined claim limitation: “a random number generator configured to provide a random number for a period of a scrub operation of a memory device” [Para. 0068, use random numbers (RN) or pseudo-random numbers (PRN) to determine the frequency of scrub operations if they are available to the system, or generated by the system. A number of methods are described below for using an RN or PRN sequence to decide whether or not to perform a scrub operation. All of the below methods assume the RN is being checked at some regular interval, and the decision to perform the scrub or not is based on some test of the RN value and 0045, In general, the scrub operation can be initiated in response to any number of factors, such as a number of host operations, a number of physical read, write and/or erase operations, a time period, usage characteristics of the host, or some random or pseudo-random sequence, the generating and checking of which may be tied to any of the above Para.0051, Scrubbing may be controlled by the memory system controller .]
Urzi and Avila are analogous arts and are in the same field of endeavor as they both pertain and directed to a memory controller.
It would have been obvious to one having ordinary skill in the art, before the effective filing of the claimed invention, to modify the system of Urzi, to implement scrub timing operation controlled by the random number generator such as, “a random number generator configured to provide a random number for a period of a scrub operation of a memory device” as taught by Avila because this would enhance the security of the system by scanning through the memory and correcting data errors without impacting the performance of the host. [See Avila, at least para 072, performing the scrub would not impact performance to the host. The scrub operations may be deferred until sometime later in the host command processing, sometime after the command processing, or until a later host command. In such a case, the scrub operation parameters that have been decided upon are stored and processed at a later time when it is most convenient to the host.]
As per dependent claim 16, The combination of Urzi and Avila discloses a control device as applied to claim 15 above. Furthermore, Urzi discloses the control device “wherein the key generator generates and provides a final key using a fixed key corresponding to at least one fixed value and at least one timed key” [Para. 0082, Once the complete memory is written by the new key, the old key is reloaded with new values from a random number generator and a key swap is done, i.e., the old key becomes the new key and the new key as the old key. [Para. 0082, “Once the complete memory is written by the new key, the old key is reloaded with new values from a random number generator and a key swap is done, i.e., the old key becomes the new key and the new key as the old key;” and para. 0088, “Once the kicker pointer reaches location N, the old key is no longer useful and is replaced by a new random key generated, for example, from a random number generator and a key swap is done.” and Para. 0079, “The kicker mechanism (read followed by write) is responsible for periodic key changes in order to increase the security level in case a memory location remains unwritten for too long” Examiner Note: the above key generation model involving a persistent) old/fixed timed key and a periodically refreshed timed key, both of which are used in the encryption/decryption process. This meets the limitation, “generation an operational (final/new) key using both the a fixed/old key and a timed key]
18. Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Ignazio Antonino Urzi (herein after referred as Urzi) (US Publication No. 20150358300 A1; Pub. Date: Dec. 10, 2015) in view of Avila et al (Avila) (US Publication No. 2013/0128666 A1, Pub. Date: May 23, 2013) and further in view of Thomas E. Tkacik (herein after referred as Tkacik) (US Publication No. 2022/0350503A1; Pub. Date: Nov. 3, 2022)
As per dependent claim 17, The combination of Urzi and Avila discloses a control device as applied to claim 15 above. Furthermore, Urzi discloses the control device “wherein the key generator generates the final key on the basis of a first timed key when an address according to a command [Para. 0082, Once the complete memory is written by the new key, the old key is reloaded with new values from a random number generator and a key swap is done, i.e., the old key becomes the new key and the new key as the old key. [Para. 0082, “Once the complete memory is written by the new key, the old key is reloaded with new values from a random number generator and a key swap is done, i.e., the old key becomes the new key and the new key as the old key;” and para. 0088, “Once the kicker pointer reaches location N, the old key is no longer useful and is replaced by a new random key generated, for example, from a random number generator and a key swap is done.” and Para. 0079, “The kicker mechanism (read followed by write) is responsible for periodic key changes in order to increase the security level in case a memory location remains unwritten for too long” Examiner Note: the above key generation model involving a persistent) old/fixed timed key and a periodically refreshed timed key, both of which are used in the encryption/decryption process. This meets the limitation, “generation an operational (final/new) key using both the a fixed/old key and a timed key],
The combination of Urzi and Avila doesn’t explicitly disclose the following underlined claim limitation: wherein the key generator generates the final key on the basis of a first timed key when an address according to a command, received from an outside is a first address and generates the final key on the basis of a second timed key when the address is a second address and the first address and the second address are distinguished by a scrub pointer indicating an address at which the scrub operation has progressed.
However, Tkacik discloses the above underlined claim limitation. In Particular Tkacik discloses: the key generator generates the final key on the basis of a first timed key [Para. 0044, Each region may have an old key and a new key and Para. 0045, the key selector 215 decides whether the address to be accessed is “above” or “below” the key update location 340. Note: This teaches that different addresses are associated with different keys. Addresses on one side of the scrub boundary use the old key which corresponds to the claim limitation, “first timed key”] when an address according to a command, received from an outside is a first address [Para. 0019, address and control logic connected to the memory interface and a command interface, wherein the address and control logic is configured to receive a memory access request and a write memory request; and para. 0038, The memory controller 200 may receive address and other command information on an address channel 240. Note: a control device/memory controller that receives commands and addresses from outside components (e.g. processors) and processes those addresses for memory accesses] and generates the final key on the basis of a second timed key when the address is a second address [Para. 0044, “When a key update is to occur, a new key is generated for each memory region”, and para. 0044, key update location 340 indicates a boundary between data that is encrypted with the new key and the old key. Note: This teaches that the memory addresses on other side of the scrub boundary use the new key which corresponds to the claimed “second timed key”] the first address and the second address are distinguished by a scrub pointer indicating an address at which the scrub operation has progressed [Para. 0044, he memory scrubber 230 moves the location of the key update location 340 and para. 0018, key update location, wherein the key update location indicates a boundary and para. 0043, he memory scrubber 230 cycles through the memory refreshing the whole memory periodically. Note: The key update location is a scrub progress pointer that indicates how far the scrub operation has progressed and distinguish addresses that have been scrubbed from those that have not.]
Urzi, Avila and Tkacik are analogous arts and are in the same field of endeavor as they all pertain and directed to a memory controller.
It would have been obvious to one having ordinary skill in the art, before the effective filing of the claimed invention, to modify the system of Urzi and Avila to implement a scrub pointer such as, “wherein the key generator generates the final key on the basis of a first timed key when an address according to a command, received from an outside is a first address and generates the final key on the basis of a second timed key when the address is a second address and the first address and the second address are distinguished by a scrub pointer indicating an address at which the scrub operation has progressed” as taught by Tkacik because this would enhance the security by scanning through the memory at and correcting data errors using an error correction code. [See Tkacik, at least para. 0017-0018, memory scrubber configured to …scan through the memory at a second rate to correct data errors using an error correction code]
Allowable Subject Matter
19. Dependent claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Dependent claims 3-10 depend on the above dependent claims 2 and would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
20. The following is an examiner’s statements of reasons for allowance:
Regarding dependent claim 2, Tkacik or a combination of Tkacik, Urzi, Avila and Gonzalez, including the rest of the cited prior arts and the prior art cited in the IDS, either taken alone or in combination neither anticipates nor renders obvious the claimed subject matter of the instant application that is taken as a whole including the following specific claim limitation recited in dependent claim 2 : “wherein the control device generates a first timed key in a first period of the scrub operation, generates a second timed key in a second period of the scrub operation, and performs the encryption and the decryption using the first timed key and the second timed key during a period of time corresponding to the second period”
For this reason, the specific claim limitations recited in dependent claim 2 taken as whole are found to be allowable.
21. The dependent claims 3-10 which are dependent on the above dependent claim 2 being further
limiting to the dependent claims, definite and enabled by the specification would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
22. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
A. US Publication No. 2009/0125788 A1 Wheeler discloses hardware-based memory scrubbing where the controller 12 includes an engine 20 configured to implement proactive scrubbing of the memory system 14. The controller 12 can also include a pseudorandom number generator 27. The engine 20 can control the pseudorandom number generator 27 according to the operating mode of the engine
B. US Patent No. 5978952 A Hayek discloses error correction circuitry attempts to detect and correct on the fly erroneous words within random access memory (RAM) within a computer system. RAM errors are scrubbed or corrected back in the memory without delaying the memory access cycle. Duration of each memory scrubbing subprocess is kept short enough that the response time of the computer system is not impaired with the housekeeping task of scrubbing RAM memory errors.
C. US Publication No. 2010/0042841 A1 King discloses updating and distributing of encryption keys. The system creates a shared secret and from the shared secret, two keys are created: a utilized key and a stored key. The utilized key is used to encrypt messages between nodes. When it is time to replace the utilized key to maintain security, the stored key is utilized to encrypt messages for generating/distributing a new shared secret. The new shared secret is then used to generate a new utilized key and a new stored key. This process may be repeated any number of times to maintain security
D. US Patent No. 9053808 B2 Sprouse discloses flash memory with targeted read scrub algorithm. A method and system have been described for counteracting and correcting for read disturb effects in blocks of flash memory. The method may include the step of a controller of the memory system performing a read scrub scan on only a portion of one targeted word line in a block at desired intervals
E. See the other cited prior arts.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMSON B LEMMA whose telephone number is 571-272-3806. The examiner can normally be reached on M-F 8am-10pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Shaw Yin Chen can be reached on to 571-272-8878. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SAMSON B LEMMA/Primary Examiner, Art Unit 2498