DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to because Fig. 1A, 150A should read 105A, the first sidewall.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 1, 8, 9 and 11 are objected to because of the following informalities:
1. A semiconductor device comprising: a plurality of active regions in a substrate; a gate trench formed in at least one of the plurality of the active regions, the gate trench including a first sidewall, a second sidewall opposite to the first sidewall, and a bottom sidewall; a growth promotion region formed on the first sidewall of the gate trench; a first gate dielectric layer formed on the first sidewall of the gate trench to contact the growth promotion region; a second gate dielectric layer formed on the second sidewall of the gate trench to be thinner than the first gate dielectric layer; and a gate electrode partially filling the gate trench over the first and second gate dielectric layers.
8. The semiconductor device of claim 1, wherein one gate electrode is disposed in each active region of the plurality of the active regions.
9. The semiconductor device of claim 1, wherein the plurality of the active regions includes a first node and a second node obtained by being divided by the gate trench.
11. A semiconductor device comprising: a substrate; an isolation layer defining an active region including a first node and a second node in the substrate; a gate trench formed between the first node and the second node and including a first sidewall and a second sidewall; a growth promotion region formed on the first sidewall of the gate trench; a first gate dielectric layer formed on the first sidewall of the gate trench to contact the growth promotion region; a second gate dielectric layer formed on the second sidewall of the gate trench to be thinner than the first gate dielectric layer; a gate electrode partially filling the gate trench over the first and second gate dielectric layers; and a potential barrier region formed in the second node below the second sidewall of the gate trench.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 19 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 19, the metes and bounds of the claimed invention are vague and ill-defined as a result of uncertainty in the different boundaries and new limitations “wherein one gate electrode is disposed in each active region of the active regions”. The claim is indefinite because of the following: There is insufficient antecedent basis for the limitation “each active region of the active regions”. It is unclear how there is an active region in a plurality of active regions.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-9, 11, 14-17 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. US 2023/0343801.
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Lee et al. US 2023/0343801
Regarding claim 1, Lee et al. Fig. 4 and [0027]-[0237] disclose a semiconductor device comprising:
a plurality of active regions AR1, AR2 [0051] in a substrate 100 [0049];
a gate trench 100t [0070] formed in at least one of the plurality of the active regions, the gate trench 100t including a first sidewall, a second sidewall opposite to the first sidewall, and a bottom sidewall (annotated above);
a growth promotion region 100f [0093]-[0095] formed on the first sidewall of the trench 100t Fig. 7;
a first gate dielectric layer 134 [0084] formed on the first sidewall of the trench to contact the growth promotion region 100f;
a second gate dielectric layer 134, Fig. 21 formed on the second sidewall of the trench to be thinner than the first gate dielectric layer; and
a gate electrode 142 [0074] partially filling the trench over the first and second gate dielectric layers.
Regarding claim 2, Lee et al. Fig. 4 and [0027]-[0237] disclose the semiconductor device of claim 1, wherein the growth promotion region 100f includes a growth promotion species [0094]-[0095] for increasing a growth rate of the first gate dielectric layer 134.
Regarding claim 3, Lee et al. Fig. 4 and [0027]-[0237] disclose the semiconductor device of claim 1, wherein the growth promotion region includes oxygen, fluorine [0094]-[0095], or a combination thereof.
Regarding claim 4, Lee et al. Fig. 4 and [0027]-[0237] disclose the semiconductor device of claim 1, wherein the first gate dielectric layer 130 includes silicon oxide SiO, and the growth promotion region includes an oxygen-containing silicon layer [0223].
Regarding claim 5, Lee et al. Fig. 4 and [0027]-[0237] disclose the semiconductor device of claim 1, wherein the first gate dielectric layer 130 includes silicon oxide Fig. 7, and the growth promotion region 100f includes a fluorine-containing silicon layer Fig. 7 [0093]-[0095].
Regarding claim 6, Lee et al. Fig. 4 and [0027]-[0237] disclose the semiconductor device of claim 1, wherein the first gate dielectric layer 130 includes silicon oxide SiO, and the growth promotion region includes a silicon layer containing oxygen and fluorine [0223].
Regarding claim 7, Lee et al. Fig. 4 and [0027]-[0237] disclose the semiconductor device of claim 1, wherein the first gate dielectric layer includes silicon oxide SiO, and the growth promotion region includes silicon oxide or fluorine-containing silicon oxide [0223].
Regarding claim 8, Lee et al. Fig. 4 and [0027]-[0237] disclose the semiconductor device of claim 1, wherein one gate electrode 140A is disposed in each active region of the active regions [0067].
Regarding claim 9, Lee et al. Fig. 4 and [0027]-[0237] disclose the semiconductor device of claim 1, the active region includes a first node 102 and a second node 103 obtained by being divided by the trench 100t.
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Lee et al. US 2023/0343801
Regarding claim 11, Lee et al. Fig. 4 and [0027]-[0237] disclose a semiconductor device comprising:
a substrate 100 [0043];
an isolation layer 110 [0043] defining an active region including a first node and a second node in the substrate;
a gate trench 100t formed between the first node and the second node and including a first sidewall and a second sidewall (annotated above);
a growth promotion region 100f [0093]-[0095] formed on the first sidewall of the trench Fig. 7;
a first gate dielectric layer 134 formed on the first sidewall of the trench to contact the growth promotion region 100f;
a second gate dielectric layer 132 formed on the second sidewall of the trench to be thinner than the first gate dielectric layer 134;
a gate electrode 142 partially filling the trench over the first and second gate dielectric layers; and
a potential barrier region (annotated above) formed in the second node below the second sidewall of the gate trench.
Regarding claim 14, Lee et al. Fig. 4 and [0027]-[0237] disclose the semiconductor device of claim 11, wherein the growth promotion region 100f includes a growth promotion species [0094]-[0095] to increase a growth rate of the first gate dielectric layer 134.
Regarding claim 15, Lee et al. Fig. 4 and [0027]-[0237] disclose the semiconductor device of claim 11, wherein the growth promotion region includes oxygen, fluorine [0094]-[0095], or a combination thereof.
Regarding claim 16, Lee et al. Fig. 4 and [0027]-[0237] disclose the semiconductor device of claim 11, wherein the first gate dielectric layer 134 includes silicon oxide Fig. 7, and the growth promotion region 100f includes an oxygen-containing silicon layer, a fluorine-containing silicon layer Fig. 7 [0093]-[0095], or a silicon layer containing oxygen and fluorine.
Regarding claim 17, Lee et al. Fig. 4 and [0027]-[0237] disclose the semiconductor device of claim 11, wherein the first gate dielectric layer includes silicon oxide SiO, and the growth promotion region includes silicon oxide or fluorine-containing silicon oxide [0223].
Regarding claim 19, Lee et al. Fig. 4 and [0027]-[0237] disclose the semiconductor device of claim 11, wherein one gate electrode G1, 140A is disposed in each active region AR of the active regions.
Allowable Subject Matter
Claims 10, 12, 13 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 10, the prior art neither anticipates nor renders obvious, in the context of the claims, a first doped region formed in the first node; a second doped region formed in the second node to be deeper than the first doped region; a data storage element coupled to the first doped region; and a bit line coupled to the second doped region.
Regarding claim 12, the prior art neither anticipates nor renders obvious, in the context of the claims, a first doped region formed in the first node; and a second doped region formed in the second node to be deeper than the first doped region, wherein the potential barrier region is disposed below the second doped region. Claim 13 is dependent on claim 12.
Regarding claim 18, the prior art neither anticipates nor renders obvious, in the context of the claims, a data storage element coupled to the first doped region; and a bit line coupled to the second doped region.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SONYA D MCCALL-SHEPARD whose telephone number is (571)272-9801. The examiner can normally be reached M-F: 8:30 AM-5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Sonya McCall-Shepard/Primary Examiner, Art Unit 2898
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