DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 19-20 are drafted in mean plus function format.
Claim 19 cites ”mean for generating a set of references that mimic operation of devices sought to be controlled in a vector modulator and means for using the set of references to generate control signal to control the vector modulator” invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. Therefore, the claim 19 is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Claim 20 cites ”mean for generating the control signals that control the vector modulator using a bias digital to analog converter (DAC)” invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. Therefore, the claim 20 is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 9-10, 13-14, and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kalani et al. (US 2025/0219647).
Regarding claim 1, Kalani discloses an architecture in figures (4-8) that teaches phase shifter (figure 7) comprises gain control generator (figure 4) having constant transconductance Gm (401) (Gm is also inherent as current source (430), definition in google IA) and bias DAC (402) (resistor ladder or string or network is well kwon as DAC) and vector modulator (figure 6, 2nd part of the figure 6 (610, 690,695) receive bias output (640, 650) of gain control circuit (figure 4) (see descriptions of the figures).
Regarding claim 2, Kalani teaches (in figure 4) Gm bias comprise transistors (403 404).
Regarding claim 3, Kalani teaches (in figure 4) Gm bias circuit provides a set of references (R2Rp and R2Rn) to bias DAC(402).
Regarding claim 8, Kalani teaches in figure 6, wherein the gain control signal generator circuit is configured to provide bias voltages (640, 650) to control the vector modulator for frequencies including sub-THz frequencies.
Regarding claim 9, Kalani teaches first transistor (403) and second transistor (404) of the Gm circuit configured to generate gate-source proportional to size ratio between the first and second transistors (see 401).
Regarding claim 10, Kalani teaches first transistor (403) and second transistor (404) are N-type in a common source arrangement (see 401).
Regarding claim 13, claim 13 is similar to claim 1 in method format. Therefore, claim 13 is rejected as well as rejected in claim 1 such as, Kalani discloses an architecture in figures (4-8) that teaches phase shifter (figure 7) comprises gain control generator (figure 4) having constant transconductance Gm (401) (Gm is also inherent as current source (430), definition in google IA) and bias DAC (402) (resistor ladder or string or network is well kwon as DAC) and vector modulator (figure 6, 2nd part of the figure 6 (610, 690,695) receive bias output (640, 650) of gain control circuit (figure 4) (see descriptions of the figures).
Regarding claim 14 Kalani teaches (in figure 4) Gm bias circuit provides a set of references (R2Rp and R2Rn) to bias DAC(402).
Regarding claim 18, Kalani teaches in figure 6, wherein the gain control signal generator circuit is configured to provide bias voltages (640, 650) to control the vector modulator for frequencies including sub-THz frequencies.
Regarding claim 19, Kalani discloses an architecture in figures (4-8) that teaches generating references by phase shifter (figure 7) comprises gain control generator (figure 4) having constant transconductance Gm (401) to be controlled in a vector modulator (Gm is also inherent as current source (430), definition in google IA) and using references signals in bias DAC (402) (resistor ladder or string or network is well kwon as DAC) to control the vector modulator (figure 6, 2nd part of the figure 6 (610, 690,695) receive bias output (640, 650) of gain control circuit (figure 4) (see descriptions of the figures).
Regarding claim 20, Kalani teaches (in figure 4) generating the control signal by using Gm bias circuit provides a set of references (R2Rp and R2Rn) to bias DAC(402).
Allowable Subject Matter
Claim 4 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest prior art of record (Kalani et al.) considered individually or in combination, fails to fairly teach or suggest objected feature, which is “wherein the set of references comprises a reference voltage, Vt+Vod, and a reference current I that produces a proportional voltage, Vod/sqrt(n) across a resistor in the Gm bias circuit”.
Claim 5 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest prior art of record (Kalani et al.) considered individually or in combination, fails to fairly teach or suggest objected feature, which is “wherein the set of references comprises voltage value between Vt and Vt+2Vod and is used to generate the bias output to the vector modulator“.
Claim 6 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest prior art of record (Kalani et al.) considered individually or in combination, fails to fairly teach or suggest objected feature, which is “wherein the bias DAC comprises a resistor bank having symmetrical nonequal resistant comprising resistance value R0 to R2N-1-2 where the resistance are symmetrical with respect to a center node of the resistor bank and where “N” represent a number of bits in a control word for the phase shifter “.
Claim 7 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest prior art of record (Kalani et al.) considered individually or in combination, fails to fairly teach or suggest objected feature, which is “wherein the bias DAC comprises a non-linear bias DAC configured to provide the bias outputs to an in phase variable gain amplifier (I VGA) and a quadrature VGA (Q VGA) in the vector modulator “.
Claim 11 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest prior art of record (Kalani et al.) considered individually or in combination, fails to fairly teach or suggest objected feature, which is “wherein gates of the first transistor and second transistor a connected to respective inputs of the first OTA, wherein drains of the first and second transistors are coupled via respective resistors to respective P-type devices arranged in a common source configuration forming a matched current mirror , wherein an output of the first OTA is connected to an output of a second OTA, and wherein inputs of the second OTA are connected across the resistance coupled to the first transistor “.
Claim 12 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest prior art of record (Kalani et al.) considered individually or in combination, fails to fairly teach or suggest objected feature, which is “a first amplifier having an inverting input connected to a supply voltage, a non-inverting input connected to the drain of the first transistor and an output connected to the gate of the first transistor, a second amplifier have inverting input connected to the supply voltage, a non-inverting input connected to the drain of the second transistor, and an output connected to the gate of the second transistor “.
Claim 15 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest prior art of record (Kalani et al.) considered individually or in combination, fails to fairly teach or suggest objected feature, which is “wherein the set of references comprises a reference voltage, Vt+Vod, and a reference current I that produces a proportional voltage, Vod/sqrt(n) across a resistor in the Gm bias circuit”.
Claim 16 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest prior art of record (Kalani et al.) considered individually or in combination, fails to fairly teach or suggest objected feature, which is “wherein the bias DAC comprises a resistor bank having symmetrical nonequal resistant comprising resistance value R0 to R2N-1-2 where the resistance are symmetrical with respect to a center node of the resistor bank and where “N” represent a number of bits in a control word for the phase shifter “.
Claim 17 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest prior art of record (Kalani et al.) considered individually or in combination, fails to fairly teach or suggest objected feature, which is “wherein the bias DAC comprises a non-linear bias DAC configured to provide the bias outputs to an in phase variable gain amplifier (I VGA) and a quadrature VGA (Q VGA) in the vector modulator “.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAM T MAI whose telephone number is (571)272-1807. The examiner can normally be reached Monday-Friday 6am-2pm eastern time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dameon Levi can be reached at 571 272-2105. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LAM T MAI/Primary Examiner, Art Unit 2845