DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The multiple information disclosure statements (IDS) have been considered by the examiner.
Drawings
The drawings were received on6/19/2024 have been accepted by the examiner.
Claim Rejections - 35 USC § 112
Claims 7-8, 10-12, 17, 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claims 7-8, 11, 17, 19, the limitations drawn to an access pass render the claims indefinite. It is not clear what is being referred to as an access pass and it is not understood what really happening during this particular process. The specification does not appropriately define this term. Clarification is required.
Regarding Claims 10 and 12, limitations drawn to a “9x2p2 memory” and a “5x2p4 memory” render the claims indefinite since it is not clear what type of memories are being referred to nor is it clear what these descriptions of memory mean. Clarification is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7, 9, 13-18, 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by SONG et al. [US 2024/0377952].
Claim 1, SONG et al. discloses an apparatus [Fig. 4] comprising: a first data terminal [BK0 data input] configured to receive a first portion of a plurality of data bits as part of a write operation [par. 0046-0052]; a second data terminal [BK1 data input] configured to receive a second portion of the plurality of data bits as part of the write operation [par. 0046-0052]; and an input/output circuit [410] configured to select the first data terminal or the second data terminal to receive a plurality of metadata bits associated with the plurality of data bits as part of the write operation [metadata mode, par. 0049].
Claim 2, SONG et al. discloses the apparatus of claim 1, wherein the input/output circuit is configured to select the first data terminal or the second data terminal based on a state of a terminal select bit in a column address [par. 0050].
Claim 3, SONG et al. discloses the apparatus of claim 1, wherein the first data terminal and the second data terminal are each configured to receive a burst length of 32 bits of data and the selected one of the first or the second data terminal is configured to receive 2 bits of metadata [par. 0048-0058].
Claim 4, SONG et al. discloses the apparatus [Fig. 4] of claim 1, further comprising: a third data terminal [BK2 data input] configured to receive a third portion of the plurality of data bits as part of the write operation [par. 0046-0052]; and a fourth data terminal [BK3 data input] configured to receive a fourth portion of the plurality of data bits as part of the write operation [par. 0046-0052], wherein the input/output circuit is configured to select the third data terminal or the fourth data terminal to receive a second portion of the plurality of metadata bits as part of the write operation.
Claim 5, SONG et al. discloses the apparatus of claim 1, further comprising an error correction code (ECC) circuit configured to generate parity bits based on the plurality of data bits and the plurality of metadata bits [par. 0006; 0078-0081].
Claim 6, SONG et al. discloses the apparatus of claim 1, further comprising a memory array including a plurality of column planes, wherein the plurality of data bits and the plurality of metadata bits are written to the memory array as part of the write operation [Abstract, par. 0054-0057].
Claim 7, SONG et al. discloses the apparatus of claim 6, further comprising a column decoder configured to write the data bits to a selected portion of the plurality of column planes and the plurality of metadata to one of a non-selected portion of the plurality of column planes as part of a single access pass [par. 0045-0052].
Claim 9 is rejected using the same rationale as Claim 1 wherein the system is represented by Fig 4, the memory device is memory 350 and the controller is 410.
Claim 13 is rejected using the same rationale as Claim 5.
Claim 14, SONG et al. discloses the system of claim 9, wherein the controller is configured to provide a column address with a terminal select bit which indicates which of the first or the second data terminals the controller is providing the plurality of metadata bits to [par. 0045-0052].
Claim 15 is rejected using the same rationale as Claim 1.
Claim 16 is rejected using the same rationale as Claim 4.
Claim 17 is rejected using the same rationale as Claim 7.
Claim 18, SONG et al. discloses the method of claim 17, further comprising: selecting a first portion of a plurality of column planes or a second portion of the plurality of column planes of the memory array based on a column plane select bit of the column address; writing the plurality of data bits to the selected one of the first portion or the second portion of the plurality of column planes; and writing the plurality of metadata bits to a non-selected one of the first portion or the second portion of the plurality of column planes [par. 0045-0052].
Claim 20, SONG et al. discloses the method of claim 15, further comprising receiving the plurality of metadata bits as part of a burst length with the first or the second portion of the plurality of data bits [par. 0045-0052].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ayyapureddi [US 2025/0110830]; Apparatus and Method for Alternate Memory Die Metadata Storage. See Abstract.
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/MIDYS ROJAS/Primary Examiner, Art Unit 2133