Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
This office acknowledges receipt of the following item(s) from the Applicant:
Information Disclosure Statement (IDS) was considered.
Claims 1-20 are present for examination.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1-7 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the column plane" in line 4. There is insufficient antecedent basis for this limitation in the claim.
Claim(s) 2-7 are dependent on claim 1 and are therefore rejected for thereason(s) of indefiniteness as indicated above.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 3-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 20160365131 A1).
Regarding claim 1: Kim discloses a memory device with odd and even column access (FIG. 2) comprising: a first column plane (memory cells arranged in columns, par. 6, FIG. 2) comprising a first plurality of bit lines (bit lines BL, FIG. 2); a second column plane (memory cells arranged in columns, par. 6, FIG. 2) comprising a second plurality of bit lines (bit lines BL, FIG. 2); and a column decoder (column signal transmission unit 220, par. 39, FIG. 2) configured to provide a first write enable signal (write command signal WT, par. 39 and 44-45) to the column plane as part of a write operation (write operation from write command signal, chosen by column select signal, par. 6 and 39-41) and configured to provide a second write enable signal (write command signal WT, par. 39 and 44-45) to the second column plane (via column select signal, par. 41) as part of the write operation, wherein the first write enable signal (write command signal WT) enables writing to the first plurality of bit lines (writing to memory cells in bit lines corresponding column select signal, par. 41) and wherein the second write enable signal (write command signal WT) enables writing to a selected subset of even ones (write command signal WT for write command to even column, par. 45) of the second plurality of bit lines or a selected subset of odd ones (write command signal WT for write command to odd column, par. 45) of the second plurality of bit lines.
Regarding claim 3: Kim discloses a memory device with odd and even column access (FIG. 2), wherein the second write enable signal (write command signal WT) is configured to enable writing to a pair of the even ones (for write command to subset of even columns, par. 45) of the second plurality of bit lines or a pair of the odd ones (for write command to subset of odd columns, par. 45) of the second plurality of bit lines.
Regarding claim 4: Kim discloses a memory device with odd and even column access (FIG. 2), wherein the second write enable signal (write command signal WT) is configured to enable writing to a single one of the even ones(for write command to even column, par. 45) of the second plurality of bit lines or a single one of the odd ones (for write command to odd column, par. 45) of the second plurality of bit lines.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20160365131 A1) in view of Kim et al. (US 20240220149 A1; hereinafter “Kim2”).
Regarding claim 2: Kim discloses a memory device with odd and even column access (FIG. 2), wherein the column decoder is configured to write the plurality of data bits to the first plurality of bit lines (write operation from write command signal, chosen by column select signal, par. 6 and 39-41) and configured to write the at least one metadata bit (write operation can include metadata bit) to the selected subset of the even ones (write command signal WT for write command to even column, par. 45) of the second plurality of bit lines or the selected subset of the odd ones (write command signal WT for write command to odd column, par. 45) of the second plurality of bit lines.
Kim does not disclose a data terminal configured to receive a plurality of data bits and at least one metadata bit as part of the write operation.
Kim2 discloses a semiconductor device with column access circuit, comprising a data terminal configured to receive a plurality of data bits and at least one metadata bit as part of the write operation (ECC engine 340/350, column access circuit receives a plurality of data units, including normal and meta data, par. 9).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Kim with the configuration of Kim2 to allow the system to receive the plurality of data bits and include a metadata bit for operation like the claimed invention.
Claim(s) 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20160365131 A1) in view of Sutera et al. (US 20230315571 A1).
Regarding claim 5: Kim discloses a memory device with odd and even column access (FIG. 2), a third column plane (memory cells arranged in columns, par. 6, FIG. 2) comprising a third plurality of bit lines (bit lines BL, FIG. 2); and wherein the column decoder is further configured to write the plurality of data bits (writing data to memory cells via bit line BL, par. 41) to the first column plane.
Kim does not disclose an error correction code (ECC) circuit configured to generate a plurality of parity bits based on a plurality of data bits and at least one metadata bit received as part of the write operation, and he at least one metadata bit to the second column plane and the plurality of parity bits to the third column plane as part of a single access pass as part of the write operation.
Sutera does disclose an integrated error correction code and parity protection utilization comprising an error correction code (ECC) circuit (par. 22 and 26, FIG. 1) configured to generate a plurality of parity bits (par. 22-23) based on a plurality of data bits and at least one metadata bit (par. 22-23) received as part of the write operation (in write access operation, par. 22-23), and the at least one metadata bit (par. 22-23) to the second column plane and the plurality of parity bits (par. 22-23) to the third column plane as part of a single access pass as part of the write operation (in write access operation, par. 22-23).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Kim with the configuration of Sutera to allow the system to have an error correction code circuit to monitor and check parity bits to ensure proper operation.
Claim(s) 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20160365131 A1) in view of Sutera et al. (US 20230315571 A1) in view of Kim2 et al. (US 20240220149 A1).
Regarding claim 6: Kim and Sutera do not disclose the ECC circuit comprises a metadata filter circuit configured to receive a plurality of bits from the second column plane as part of a read operation and configured to select the at least one metadata bit from the plurality of bits.
Kim2 does disclose a semiconductor device with column access circuit wherein the ECC circuit (ECC engine 340/350, FIG. 3) comprises a metadata filter circuit configured to receive a plurality of bits (column access circuit receives a plurality of data units, including normal and meta data, par. 9) from the second column plane (subset of plurality of bit lines of memory cell array 310, FIG. 3) as part of a read operation and configured to select the at least one metadata bit (during read operation, selects and stores a unit of meta data, par. 112) from the plurality of bits.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Kim and Sutera with the configuration of Kim2 to allow the system to filter the incoming plurality of data bits to select a metadata bit needed for operation.
Claim(s) 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20160365131 A1) in view of Nakai (US 20200183781 A1).
Regarding claim 7: Kim discloses a memory device with odd and even column access (FIG. 2), providing the first write enable signal (write command signal WT, par. 45) to the GCR column plane or the second write enable signal signal (write command signal WT, par. 45) to the GCR column plane (via column select signal, par. 41).
Kim does not disclose a global column redundancy (GCR) column plane.
Nakai does disclose a redundancy scheme with dedicated error correction code circuit further comprising: a global column redundancy (GCR) column plane (global column redundancy architecture, par. 40).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Kim with the global redundancy planes of Nakai to allow the system to operate as the claimed invention and send signals to the global redundancy column plane.
Claim(s) 8-9 and 12-13 is rejected under 35 U.S.C. 103 as being unpatentable over Kim2 et al. (US 20240220149 A1) in view of Kim et al. (US 20160365131 A1).
Regarding claim 8: Kim2 discloses a semiconductor device with column access circuit comprising: receiving a plurality of data bits and at least one metadata bit (column access circuit receives a plurality of data units, including normal and meta data, par. 9) as part of a write operation.
Kim2 does not disclose activating a first column select signal associated with a first plurality of bit lines in a first column plane; activating a first write enable signal associated with the first plurality of bit lines in the first column plane; writing at least a portion of the plurality of data bits to the plurality of bit lines in the first column plane; activating a second column select signal associated with a second plurality of bit lines in a second column plane; activating a second write enable signal associated with a subset of the second plurality of bit lines; and writing the at least one metadata bit to the subset of the second plurality of bit lines.
Kim does disclose a memory device with odd and even column access comprising: activating a first column select signal (column select signal, par. 41) associated with a first plurality of bit lines (bit lines BL, FIG. 2) in a first column plane (memory cells arranged in columns, par. 6, FIG. 2; activating a first write enable signal (write command signal WT, par. 39 and 44-45) associated with the first plurality of bit lines in the first column plane (write command signal associated with bit lines/columns to be written to, par. 39); writing at least a portion of the plurality of data bits to the plurality of bit lines in the first column plane (writing to memory cells in bit lines corresponding column select signal, par. 41); activating a second column select signal (write command signal WT) associated with a second plurality of bit lines (bit lines BL, FIG. 2) in a second column plane (memory cells arranged in columns, par. 6, FIG. 2); activating a second write enable signal (write command signal WT) associated with a subset of the second plurality of bit lines; and writing the at least one metadata bit (write operation can include metadata bit) to the subset of the second plurality of bit lines.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Kim2 with the method of Kim to allow the method to follow a similar procedure as the claimed invention.
Regarding claim 9: Kim2 does not disclose the second write enable signal is associated with even or odd ones of the second plurality of bit lines, and wherein the subset is a subset of the even or the odd ones of the second plurality of bit lines.
Kim does disclose a memory device with odd and even column access comprising: wherein the second write enable signal (write command signal WT) is associated with even or odd ones of the second plurality of bit lines (for write command to subset of even/odd columns, par. 45), and wherein the subset is a subset of the even or the odd ones (for write command to subset of even/odd columns, par. 45) of the second plurality of bit lines.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Kim2 with the method of Kim to have the defined write signal be associated with the claimed subsets of bit lines.
Regarding claim 12: Kim2 discloses a semiconductor device with column access circuit comprising generating a plurality of parity bits based on the plurality of data bits and the at least one metadata bit (column access circuit receives a plurality of data units, including normal and meta data, par. 9) with an error correction code (ECC) circuit (ECC engine 340/350).
Kim2 does not disclose electing a first portion of a plurality of column planes based on a column plane select bit, wherein the first column plane is part of the first portion; and writing the plurality of parity bits to a second portion of the plurality of column planes.
Kim does disclose a memory device with odd and even column access comprising: selecting a first portion of a plurality of column planes (memory cells arranged in columns, par. 6, FIG. 2) based on a column plane select bit (via column select signal, par. 41), wherein the first column plane is part of the first portion; and writing the plurality of parity bits (write operation can include parity bits) to a second portion of the plurality of column planes (memory cells arranged in columns, par. 6, FIG. 2).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Kim2 with that of Kim to allow the system to allow the method to follow a similar procedure as the claimed invention.
Regarding claim 13: Kim2 discloses a semiconductor device with column access circuit comprising reading a plurality of bits from the second plurality of bit lines (column access circuit receives a plurality of data units, including normal and meta data, par. 9); selecting the at least one metadata bit from the plurality of bits (during read operation, selects and stores a unit of meta data, par. 112); and providing the at least one metadata bit to the ECC circuit (meta data to a n ECC sub engine, par. 86).
Claim(s) 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kim2 et al. (US 20240220149 A1) in view of Kim et al. (US 20160365131 A1), in further view of Ohsawa (US 20050226070 A1).
Regarding claim 10: Kims2 and Kim do not disclose providing the first write enable signal to an even sense amplifier region and an odd sense amplifier region at the first column plane; and providing the second write enable signal to one of the even sense amplifier region or the odd sense amplifier region at the second column plane.
Ohsawa does disclose a semiconductor device providing the first write enable signal to an even sense amplifier region (e.g. 10, FIG. 2) and an odd sense amplifier region (e.g. 20, FIG. 2) at the first column plane (FIG. 2); and providing the second write enable signal to one of the even sense amplifier region (e.g. 10, FIG. 2) or the odd sense amplifier region (e.g. 20, FIG. 2) at the second column plane.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Kim2 and Kim with the configuration of Ohsawa to have the defined sense amplifier regions in the memory array.
Claim(s) 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kim2 et al. (US 20240220149 A1) in view of Kim et al. (US 20160365131 A1), in further view of Nakai (US 20200183781 A1).
Regarding claim 14: Kim2 and Kim do not disclose repairing the first plurality of bit lines or the second plurality of bit lines to a global column repair (GCR) column plane; and providing the first write enable signal to the GCR column plane if the first plurality of bit lines was repaired or providing the second write enable signal to the GCR column plane if the second plurality of bit lines was repaired.
Nakai does disclose a redundancy scheme with dedicated error correction code circuit further comprising: repairing the first plurality of bit lines or the second plurality of bit lines to a global column repair (GCR) column plane (par. 38); and providing the first write enable signal to the GCR column plane if the first plurality of bit lines was repaired (par. 46) or providing the second write enable signal to the GCR column plane if the second plurality of bit lines was repaired (par. 46).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Kim2 and Kim with the configuration of Nakai to allow the redundancy plane and ECC circuit to determine and repair necessary columns.
Claim(s) 15-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20160365131 A1) in view of Ohsawa (US 20050226070 A1).
Regarding claim 15: Kim does disclose a memory device with odd and even column access comprising: a memory section (memory array, par. 2) comprising a first column plane and a second column plane (memory cells of memory array arranged in columns, par. 6, FIG. 2); a column decoder (column signal transmission unit 220, par. 39, FIG. 2) configured to provide a first write enable signal (write command signal WT, par. 39 and 44-45) which activates the first plurality of read/write transfer gates and the second plurality of read/write transfer gates as part of a write operation (write operation from write command signal, chosen by column select signal, par. 6 and 39-41) and configured to provide a second write enable signal which activates a selected subset of the third plurality of read/write transfer gates (write command signal WT for write command to even column with coupled transfer gates, par. 45) or a selected subset of a fourth plurality of read/write transfer gates (write command signal WT for write command to odd column with coupled transfer gates, par. 45) based on a value of the second write enable signal as part of the write operation.
Kim does not disclose a first sense amplifier region on a first side of the memory section the first sense amplifier region comprising a first plurality of read/write transfer gates associated with the first column plane and a second plurality of read/write transfer gates associated with the second column plane; a second sense amplifier region on a second side of the memory section comprising a third plurality of read/write transfer gates associated with the first column plane and a fourth plurality of read/write transfer gates associated with the second column plane.
Ohsawa does disclose a semiconductor memory device comprising: a first sense amplifier region (e.g. 10, FIG. 2) on a first side of the memory section (FIG. 2) the first sense amplifier region comprising a first plurality of read/write transfer gates (e.g. TGL1-2, FIG. 2) associated with the first column plane (via column select line CSL, FIG. 2) and a second plurality of read/write transfer gates (e.g. TGR1-2, FIG. 2) associated with the second column plane (via column select line CSL, FIG. 2); a second sense amplifier region (e.g. 20, FIG. 2)on a second side of the memory section (FIG. 2) comprising a third plurality of read/write transfer gates (e.g. TGL3-4, FIG. 2) associated with the first column plane (via column select line CSL, FIG. 2) and a fourth plurality of read/write transfer gates (e.g. TGR3-4, FIG. 2) associated with the second column plane(via column select line CSL, FIG. 2).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Kim with the configuration of Ohsawa to have the defined sense amplifier regions in the memory array.
Regarding claim 16: Kim does disclose a memory device with odd and even column access, wherein each value of the second write enable signal (write command signal WT) is configured to activate a selected pair of the third (for write command to subset of even columns, par. 45) or the fourth (for write command to subset of odd columns, par. 45) plurality of read/write transfer gates.
Regarding claim 17: Kim does disclose a memory device with odd and even column access, wherein each value of the second write enable signal (write command signal WT) is configured to activate a single one of the third (for write command to subset of even columns, par. 45) or the fourth (for write command to subset of odd columns, par. 45) plurality of read/write transfer gates.
Regarding claim 19: Kim does disclose a memory device with odd and even column access, comprising: a plurality of signal lines (via BUS lines, FIG. 2), each associated with one of the values of the second write enable signal (write command signal WT), wherein a first portion of the plurality of signal lines (e.g. BUS1, FIG. 2) is coupled to the third plurality of read/write transfer gates (transfer gates of associated banks and sense amplifiers of memory, FIG. 2) and a second portion of the plurality of signal lines (e.g. BUS2, FIG. 2) is coupled to the third plurality of read/write transfer gates (transfer gates of associated banks and sense amplifiers of memory, FIG. 2).
Regarding claim 20: Kim does disclose a memory device with odd and even column access, wherein the column decoder is further configured to provide a first column select signal (column select signal, par. 39-41) associated with a fist plurality of bit lines (writing to memory cells in bit lines corresponding column select signal, par. 41) coupled to the first and the second plurality of read/write transfer gates (transfer gates of associated banks and sense amplifiers of memory, FIG. 2) and configured to provide a second column select signal (column select signal, par. 39-41) associated with a second plurality of bit lines (writing to memory cells in bit lines corresponding column select signal, par. 41) coupled to the third and the fourth plurality of read/write transfer gates (transfer gates of associated banks and sense amplifiers of memory, FIG. 2).
Claim(s) 18 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20160365131 A1) in view of Ohsawa (US 20050226070 A1), in further view of Nakai (US 20200183781 A1).
Regarding claim 18: Kim does disclose a memory device with odd and even column access, providing the first write enable signal (write command signal WT, par. 45) or the second write enable signal (write command signal WT, par. 45) to the GCR column plane based on a repair signal (via column select signal, par. 41).
Kim and Ohsawa does not disclose wherein the memory section further comprises a global column repair (GCR) column plane.
Nakai does disclose a redundancy scheme with dedicated error correction code circuit further comprising: a global column redundancy (GCR) column plane (global column redundancy architecture, par. 40).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Kim and Ohsawa with the global redundancy planes of Nakai to allow the system to operate as the claimed invention and send signals to the global redundancy column plane.
Allowable Subject Matter
Claim(s) 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject
matter:
Claims include allowable subject matter since the prior art made of record and considered pertinent to the applicants’ disclosure, taken individually or in combination, does not teach or suggest the claimed invention having: further comprising providing a third write enable signal to the other of the even sense amplifier region or the odd sense amplifier region at the metadata second plane as in claim 11.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY THINH TANG whose telephone number is (571)272-6845. The examiner can normally be reached Monday-Friday 7:30-5:00 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTHONY THINH TANG/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
Prosecution Insights