Prosecution Insights
Last updated: April 19, 2026
Application No. 18/747,785

ASYMMETRIC POWER MODULE

Non-Final OA §102§103
Filed
Jun 19, 2024
Examiner
JAGER, RYAN C
Art Unit
2842
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Infineon Technologies AG
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
2y 0m
To Grant
92%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allow Rate
824 granted / 921 resolved
+21.5% vs TC avg
Minimal +3% lift
Without
With
+3.0%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
14 currently pending
Career history
935
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
35.9%
-4.1% vs TC avg
§102
37.0%
-3.0% vs TC avg
§112
18.5%
-21.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 921 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Non-Final communication in response to communication filed 6/19/24. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1,2,8, 14,15,17-19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Uozumi 20170346666. With respect to claim 1, figures 6 and 7 of Uozumi discloses a power module, comprising: a module control terminal [S1], a first module load terminal [Vin], and a second module load terminal [top SW1]; and at least one power switch comprising a plurality of switching devices [SW10/11/19] coupled in parallel, wherein: each switching device of the plurality of switching devices comprises a device control terminal [receives S1], a first load terminal [connection to resistors], and a second load terminal [connection to SW1], the device control terminals of the plurality of switching devices are coupled to the module control terminal via a plurality of control paths [connections to S1], the first load terminals of the plurality of switching devices are coupled to the first module load terminal via a plurality of first load paths [connections to Vin], the second load terminals of the plurality of switching devices are coupled to the second module load terminal via a plurality of second load paths [connections to SW1], and a control path of the plurality of control paths, or a first load path [through resistors R10-19] of the plurality of first load paths or a second load path of the plurality of second load paths has an electrical parameter that is respectively different from other control paths of the plurality of control paths, other first load paths of the plurality of load paths [para 0079; R10 to R19 are mutually different ], or other second load paths of the plurality of load paths. With respect to claim 2, figures 6 and 7 of Uozumi discloses the power module of claim 1, wherein the electrical parameter is a resistance, an inductance, or a capacitance. With respect to claim 8, figures 6 and 7 of Uozumi discloses the power module of claim 1, wherein a control path of the plurality of control paths, a first load path of the plurality of first load paths, or a second load path of the plurality of second load paths includes at least one of a resistive element and a capacitor. With respect to claim 14, figures 6 and 7 of Uozumi discloses a method of operating a power module comprising: a module control terminal [S1], a first module load terminal [Vin], and a second module load terminal [connection to SW1], and at least one power switch comprising a plurality of switching devices [SW10-SW19] coupled in parallel, wherein each switching device of the plurality of switching devices comprises a device control terminal [receives S1], a first load terminal [connection to Vin], and a second load terminal [connection to SW1], the device control terminals of the plurality of switching devices are coupled to the module control terminal via a plurality of control paths, the first load terminals of the plurality of switching devices are coupled to the first module load terminal via a plurality of first load paths, the second load terminals of the plurality of switching devices are coupled to the second module load terminal via a plurality of second load paths, and a control path of the plurality of control paths has a first electrical parameter different from other control paths of the plurality of control paths, or a first load path of the plurality of first load paths has a second electrical parameter different from other first load paths of the plurality of load paths [para 0079; R10 to R19 are mutually different ], or a second load path of the plurality of second load paths has a third electrical parameter different from other second load paths of the plurality of load paths, the method comprising: applying a switch control signal to the module control terminal; and applying, by the at least one power switch, a switching signal to the first module load terminal and the second module load terminal in response to applying the switch control signal. With respect to claim 15, figures 6 and 7 of Uozumi discloses the method of claim 14, further comprising applying power to a load coupled to the first module load terminal and the second module load terminal. With respect to claim 17, figures 6 and 7 of Uozumi discloses the method of claim 14, wherein the electrical parameter is a resistance, an inductance, or a capacitance. With respect to claim 18, figures 6 and 7 of Uozumi discloses a power module, comprising: a module control terminal [S1], a first module load terminal [Vin], and a second module load terminal [connection to S1]; a power switch comprising a plurality of transistors [SW10-SW19] coupled in parallel, each transistor having a control terminal [receives S1], a first load terminal [connection to Vin], and a second load terminal [connection to SW1]; and a substrate [para 103] comprising: a first conductive structure forming a portion of a plurality of first load paths coupling the first load terminals of the plurality of transistors to the first module load terminal, and a second conductive structure forming a portion of a plurality of second load paths coupling the second load terminals of the plurality of transistors to the second module load terminal, [each transistor connection has a different conductive structure] wherein at least one of the plurality of first load paths has a different resistance, inductance or capacitance from other ones of the plurality of first load paths, or at least one of the plurality of second load paths has a different a different resistance, inductance or capacitance from other ones of the plurality of second load paths. With respect to claim 19, figures 6 and 7 of Uozumi discloses the power module of claim 18, wherein the substrate further comprises a third conductive structure forming a portion of a plurality of control paths coupling the control terminals of the plurality of transistors to the module control terminal. Claim(s) 1-4, 7-10, 14, 15,17-19 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Nakashima 20070126476. With respect to claim 1, figures 3 6 and 7 of Nakashima discloses a power module [figs 3,6,7], comprising: a module control terminal [18], a first module load terminal [12], and a second module load terminal [19]; and at least one power switch [15,16, 65,66] comprising a plurality of switching devices coupled in parallel, wherein: each switching device of the plurality of switching devices comprises a device control terminal [connected to 18], a first load terminal [connected to 12], and a second load terminal [connected to 19], the device control terminals of the plurality of switching devices are coupled to the module control terminal via a plurality of control paths [paths to 18], the first load terminals of the plurality of switching devices are coupled to the first module load terminal via a plurality of first load paths [paths to 12], the second load terminals of the plurality of switching devices are coupled to the second module load terminal via a plurality of second load paths [paths to 19], and a control path of the plurality of control paths, or a first load path of the plurality of first load paths or a second load path of the plurality of second load paths has an electrical parameter that is respectively different [fig 3 Ra,Rb,Rc,Rd] from other control paths of the plurality of control paths, other first load paths of the plurality of load paths, or other second load paths of the plurality of load paths. With respect to claim 2, figures 3 6 and 7 of Nakashima discloses The power module of claim 1, wherein the electrical parameter is a resistance [wire resistance], an inductance, or a capacitance. With respect to claim 3, figures 3 6 and 7 of Nakashima discloses the power module of claim 1, further comprising a substrate layer [fig 7], wherein: the substrate layer comprises a first section [outside] and a second section [inside] separate from the first section; the plurality of first load paths is formed by at least a portion of the first section and the plurality of second load paths is formed by at least a portion of the second section; each path of the plurality of first load paths has a path length along the first section; each path of the plurality of second load paths has a path length along the second section; and a path length of the first load path of the plurality of first load paths is different from path lengths of the other first load paths of the plurality of first load paths, or a path length of the second load path of the plurality of second load paths is different from path lengths of the other second load paths of the plurality of second load paths. [figs 3 and 7 disclose different path lengths and resistances] With respect to claim 4, figures 3 6 and 7 of Nakashima discloses the power module of claim 3, wherein the first section or the second section comprises at least one slit. With respect to claim 7, figures 3 6 and 7 of Nakashima discloses the power module of claim 3, wherein: the substrate layer comprises a third section separate from the first section and the second section; the plurality of control paths is formed at least in part on the third section; each path of the plurality of control paths has a path length along the third section; and a path length of the first load path of the plurality of first load paths is different from path lengths of the other first load paths of the plurality of first load paths, or a path length of the second load path of the plurality of second load paths is different from path lengths of the other second load paths of the plurality of second load paths, or a path length of the control path of the plurality of control paths is different from path lengths of the other control paths of the plurality of control paths. [All shown in figure 7] With respect to claim 8, figures 3 6 and 7 of Nakashima discloses the power module of claim 1, wherein a control path of the plurality of control paths, a first load path of the plurality of first load paths, or a second load path of the plurality of second load paths includes at least one of a resistive element [the wire] and a capacitor. With respect to claim 9, figures 3 6 and 7 of Nakashima discloses the power module of claim 1, further comprising a control coupling structure having a plurality of control coupling paths, each control coupling path corresponding to a control path of the plurality of control paths, wherein at least one control coupling path of the plurality of control coupling paths has a resistance differing from resistances of other control coupling paths of the plurality of control coupling paths. [Nakashima discloses different path lengths have different resistances] With respect to claim 10, figures 3 6 and 7 of Nakashima discloses the power module of claim 1, wherein at least one switching device of the plurality of switching devices has a different device layout from other switching devices of the plurality of switching devices [see figure 7], the different device layout configured to: cause the control path of the plurality of control paths, or the first load path of the plurality of first load paths, or the second load path of the plurality of second load paths to have the electrical parameter that is respectively different from the other control paths of the plurality of control paths, the other first load paths of the plurality of load paths, or the other second load paths of the plurality of load paths. With respect to claim 14, figures 3 6 and 7 of Nakashima discloses a method of operating a power module comprising: a module control terminal [18], a first module load terminal [12], and a second module load terminal [19], and at least one power switch [15,16,65,66] comprising a plurality of switching devices coupled in parallel [see fig 6], wherein each switching device of the plurality of switching devices comprises a device control terminal [gate], a first load terminal [drain], and a second load terminal [source], the device control terminals of the plurality of switching devices are coupled to the module control terminal via a plurality of control paths [connections from gates to 18], the first load terminals of the plurality of switching devices are coupled to the first module load terminal via a plurality of first load paths [connections to 12], the second load terminals of the plurality of switching devices are coupled to the second module load terminal via a plurality of second load paths [connections to 19], and a control path of the plurality of control paths has a first electrical parameter different from other control paths of the plurality of control paths, or a first load path of the plurality of first load paths has a second electrical parameter different from other first load paths of the plurality of load paths, or a second load path of the plurality of second load paths has a third electrical parameter different from other second load paths of the plurality of load paths, the method comprising: applying a switch control signal to the module control terminal; and applying, by the at least one power switch, a switching signal to the first module load terminal and the second module load terminal in response to applying the switch control signal. With respect to claim 15, figures 3 6 and 7 of Nakashima discloses the method of claim 14, further comprising applying power to a load coupled to the first module load terminal and the second module load terminal. With respect to claim 17, figures 3 6 and 7 of Nakashima discloses the method of claim 14, wherein the electrical parameter is a resistance, an inductance, or a capacitance. With respect to claim 18, figures 3 6 and 7 of Nakashima discloses a power module, comprising: a module control terminal [18], a first module load terminal [12], and a second module load terminal [19]; a power switch comprising a plurality of transistors [15,16,65,66] coupled in parallel, each transistor having a control terminal [gate], a first load terminal [drain], and a second load terminal [source]; and a substrate [Fig. 7] comprising: a first conductive structure [13] forming a portion of a plurality of first load paths coupling the first load terminals of the plurality of transistors to the first module load terminal, and a second conductive structure [14] forming a portion of a plurality of second load paths coupling the second load terminals of the plurality of transistors to the second module load terminal, wherein at least one of the plurality of first load paths has a different resistance [fig. 3], inductance or capacitance from other ones of the plurality of first load paths, or at least one of the plurality of second load paths has a different a different resistance [fig. 3], inductance or capacitance from other ones of the plurality of second load paths. With respect to claim 19, figures 3 6 and 7 of Nakashima discloses the power module of claim 18, wherein the substrate further comprises a third conductive structure [18, fig. 7] forming a portion of a plurality of control paths coupling the control terminals of the plurality of transistors to the module control terminal. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 5,6 are rejected under 35 U.S.C. 103 as being unpatentable over Nakashima 20070126476. With respect to claim 5, Nakashima discloses the power module of claim 3, but does not disclose wherein: the first section comprises a first plurality of coupling structures and the second section comprises a second plurality of coupling structures, the first plurality of coupling structures and the second plurality of coupling structures respectively extending in parallel; the plurality of first load paths is at least in part formed on the first plurality of coupling structures and the plurality of second load paths is at least in part formed on the second plurality of coupling structures; and at least one coupling structure of at least one of the first plurality of coupling structures or the second plurality of coupling structures has a length respectively differing from lengths of other coupling structures of the first plurality of coupling structures or of the second plurality of coupling structures. However, It would have been obvious to one skilled in the art at the time the invention was made to arrange the elements as described above , since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70 With respect to claim 6, the above modification discloses the power module of claim 3, wherein: the first section comprises a first plurality of coupling structures and the second section comprises a second plurality of coupling structures, the first plurality of coupling structures and the second plurality of coupling structures respectively having a meandering shape; the plurality of first load paths is at least in part formed on the first plurality of coupling structures and the plurality of second load paths is at least in part formed on the second plurality of coupling structures; and at least one coupling structure of at least one of the first plurality of coupling structures or the second plurality of coupling structures has a length respectively differing from lengths of other coupling structures of the first plurality of coupling structures or of the second plurality of coupling structures. Claims 11,12 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Nakashima 20070126476 in view of Prasad 20230361771 With respect to claim 11, figures 3 6 and 7 of Nakashima discloses the power module of claim 1, but does not disclose wherein the at least one power switch is configured to block voltages greater than 400 V. However, Prasad et al .20230361771 discloses a parallel switch [fig. 9; 204s] capable of blocking 400V [para 0040] fabricated as IGBTs, SiCs or GaN Fets. [para 0040] It would have been obvious to one skilled in the art at the time the invention was to use transistors rated to the appropriate voltages for the use, since it has been held to be withing the general kill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. With respect to claim 12, the above combination discloses the power module of claim 1, wherein the plurality of switching devices are silicon carbide (SiC) MOSFETs, silicon IGBTs, or gallium nitride (GaN) HEMTs. With respect to claim 20, the power module of claim 18, wherein the first conductive structure and the second conductive structure comprise copper. [para 0040] Allowable Subject Matter Claims 13, 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN C JAGER whose telephone number is (571)272-7016. The examiner can normally be reached on 8:30 - 5:30 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lincoln Donovan can be reached on 571-272-7016. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RYAN JAGER/ Primary Examiner, Art Unit 2842 2/10/26
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Prosecution Timeline

Jun 19, 2024
Application Filed
Feb 14, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
92%
With Interview (+3.0%)
2y 0m
Median Time to Grant
Low
PTA Risk
Based on 921 resolved cases by this examiner. Grant probability derived from career allow rate.

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