DETAILED ACTION
This office action is in response to the application and claims filed on June 19, 2024. Claims 1-19 are pending, with claims 1, 10, and 16 in independent form.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The prior art documents submitted by Applicant in the Information Disclosure Statements filed on June 19, 2024, have been considered and made of record (note attached copy of forms PTO-1449). Note that the Marchetti NPL Reference on page 3 has not been considered and lined-through. There was no formal copy of such NPL document submitted into the file, as of the date of this office action.
Drawings
The original drawings (eleven (11) pages) were received on June 19, 2024. These drawings are acknowledged.
Claim Objections
Claims 13 and 17 are objected to because of the following informalities: regarding dependent claim 13, the phrase “the first alignment pin is apart from the second alignment pin are apart in a horizontal direction” is awkward and needs re-drafting. Regarding claim 17, the typo in the term “an length” should read “a length.” Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-19 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. U.S. Patent No. 10,852,476 B2, and further in view of Morgan et al. US 2024/0027697 A1.
Regarding independent claims 1 and 10, Chen et al. U.S. Patent No. 10,852,476 B2 teaches (ABS; Figs. 9-13, 15; corresponding text, in particular column 6, line 39 through column 9, line 5; Claims) a semiconductor package 100a (most notably Fig. 12) comprising: a package substrate (substrate not expressly shown, but Chen notes that the features such as optical structures can be formed on a substrate as part of 110, column 3, lines 18-29); a photonic integrated circuit chip 110a (as in Figs. 9-13) disposed on the package substrate (noting column 3, lines 18-20), the photonic integrated circuit chip include a groove extending inwardly from a side surface of the photonic integrated circuit chip (see Figs. 9-10, the groove formed in 110a to receive portion(s) of an optical fiber connector (160a, at “F”), and a photo-electron conversion unit including an edge coupler (edge coupler at 112a, in which light is coupled into the chip and where photo-electron conversion occurs (to/from an emitter and/or receiver); an optical fiber connector (160a, at “F”) including a frame (housing, implied structural portion to hold the fiber(s)), an optical fiber mounted in the groove of the photonic integrated circuit chip (see mounting in Figs. 10 and 12, for example; at different directions (vertical (Fig. 10) and horizontal (Fig. 12)); in which the edge coupler is located at one end of the (internally located) photo-electron conversion unit (112a “edge coupler” is located at the edge facing the connected fiber, Fig. 12). Regarding second independent claim 10, Chen US ‘476 teaches a plurality of terminal edge coupling features (“optical couplers 112”, as in the description of Fig. 10), while a complementary semiconductor chip 120 is also shown in Figs. 9-12, and plural optical fibers 130.
Regarding independent claims 1 and 10, Chen US ‘476 does not expressly and exactly teach that the package substrate includes an “alignment hole” extending inwardly from a side surface, and that the frame (of the optical fiber connector) includes an “alignment pin” extending from the frame to an inside of the alignment hole.
Morgan et al. US 2024/0027697 A1 teaches (ABS; Figs. 1A, 1B, 2, 3A-3C; corresponding text; Claims) a semiconductor connected package that includes an optical fiber connector (as in Fig. 2, to the right), in which such a connector is connected to a photonic integrated circuit chip (PIC, see Fig. 1B), and in that there is a substrate (210, Fig. 2) for connecting such connected optical fiber feature to the substrate, and a “alignment hole” 214 which extends inwardly from a side surface of the package substrate (see the hole / recess extending into the substrate, Fig. 2) and in that a frame of a connector (at 220, Fig. 2) includes at least a first alignment pin 224 extending from the frame and (when connected) to an inside of the first alignment hole. See Figs. 1A and 1B for the connected configuration in which the substrate and connector are mated.
Since Chen and Morgan are both from the same field of endeavor, the purpose disclosed by Morgan would have been recognized in the pertinent art of Chen.
A person having ordinary skill in the art at a time before the effective filing date of the current application would have recognized the teaching of Morgan, to use an optical fiber connector frame that includes alignment pin(s), for corresponding alignment hole(s), in a connected package substrate, such as the substrate / chip feature of the primary reference of Chen, and the base design thereof (using a connected fiber -> groove -> edge coupler(s) -> chip features to include photo-electron conversion (for I/O), to allow for secure and redundant positioning of the fiber, but also to have visual “alignment hole(s)” for a technician or robot to connect the fiber connector to the chip / package. Further, it would have required no undue burden or unnecessary experimentation to arrive at such feature of a frame of an optical fiber connector to have alignment pins for corresponding alignment holes on a package. See KSR v. Teleflex, 127 S.Ct. 1727 (2007). For these reasons, independent claims 1 and 10 are found obvious over Chen and further in view of Morgan (henceforth “COMBO”).
Regarding further dependent claims 2-9 and 11-15, the formulation of COMBO’s hypothetical device as found in claims 1 and/or 10 makes obvious the additional claimed features. For example, the edge coupler features of Chen having “constant thickness” (claim 2); the optical fiber having a core/clad and being vertically aligned to the edge coupler (claim 3); and the preferred horizontal lengths of the features of frame and groove (claim 6) are all obvious design choices for sizing constraints and tolerances to include these optical/electrical features on a design chip and during manufacture. For example, and at a time before the effective filing date of the current application, it would have been an obvious matter of common skill and design choice to a person of ordinary skill in the art to use features such as those outlined by dependent claims 2, 3, and 6, because Applicant has not disclosed that using such features provides an advantage, is used for a particular purpose, or solves a stated problem. One of ordinary skill in the art, furthermore, would have expected COMBO to perform equally well with such features as having the constant thickness of the edge coupler(s), or to have the vertical and/or horizontal alignment features of the optical fiber in the groove, because these claim terms would have been easily integrated and would have also been recognized by one with common skill in the art to improve optical signal propagation coupling in (and out) from the edge coupler(s) to connected fiber(s). It would have required no undue burden or unnecessary experimentation to arrive at those features with a semiconductor package device such as in COMBO. Further, the base structure of the independent claims 1 and 10 is found obvious over COMBO as outlined herein. Therefore, it would have been an obvious matter of common skill and design choice to modify (and/or update) COMBO to obtain the invention as specified in claims 2, 3, and 6. See KSR v. Teleflex, 127 S.Ct. 1727 (2007).
Regarding dependent claims 4-5, the frame and integrated circuit chip would have those features facing each other in COMBO. Claim 5’s features are obvious design choices for POSITA to properly and securely the fiber in the groove. KSR.
Regarding claim 7, the alignment hole is “apart” from the upper and lower surfaces of the package substrate (space between the hole and both upper/lower).
Regarding claim 8, the alignment pin of Morgan has a number of regions with different cross-sectional areas (see 224 in Fig. 2), which meets the claimed structure. Therefore, such structure is found obvious. KSR.
Regarding claim 9, the PIC chip of Chen includes through vias for optical and/or electrical contact (Figs. 1A-1B). Therefore, such structure is found obvious. KSR Regarding claims 11-12, the plurality of connected fibers 130 in Morgan’s connector are capable of transmitting multiple wavelengths of optical signals (claim 12) and different wavelengths as input/output (claim 13). Therefore, such intended use of the fibers for transmission of multiple/different wavelength signals is an obvious intended use of structure that is capable of such use. KSR.
Regarding claim 13, Morgan shows at least as second alignment pin (Fig. 2, 224), which is apart in a horizontal direction (note frame-of-reference of horizontal).
Regarding claim 14, making the pins far apart would have been obvious to POSITA to improve stabilization of the securing pin. KSR.
Regarding claim 15, Morgan shows at least as second alignment pin (Fig. 2, 224), which is apart in a vertical direction (note frame-of-reference of vertical), which can be viewed as overlapping based on the perspective of the viewer.
Regarding 3rd independent claim 16, the features of Chen include a semiconductor chip 120 (complementary; as in Figs. 9-12), while this primary reference (of COMBO) teaches a plurality of terminal edge coupling features (“optical couplers 112”, as in the description of Fig. 10) and plural optical fibers 130. Therefore, claim 19 is found obvious over the same logic and rationale from COMBO, with the first alignment hole being apart from the upper and lower surfaces of the package substrate (in between those surfaces, as in Morgan (Fig. 2).
Regarding dependent claim 17, such overall dimensional features are obvious design choices for the length of the groove in relation to length of the first alignment hole as it extends. Therefore, there is no criticality found to such features. Further, it would have required no undue burden or unnecessary experimentation to arrive at such design for relative lengths. KSR.
Regarding claims 18-19, the alignment pin includes different thicknesses (Morgan Fig. 2 element 224) in axial directions (claim 18), and the first and second alignment pins (Morgan Fig. 2) are “apart” at least in one of horizontal and/or vertical directions (note frame-of-reference for such terms).
Inventorship
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: PTO-892 form references C-I, which pertain to the state of the art of optical / photonic integrated circuit chips that optically couple an external fiber/cable to the chip by using grooved features, or by using edge couplers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Daniel Petkovsek whose telephone number is (571) 272-4174. The examiner can normally be reached M-F 7:30 - 6 PM.
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/DANIEL PETKOVSEK/Primary Examiner, Art Unit 2874 September 17, 2026
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