CTFR 18/748,173 CTFR 89467 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 12-151 AIA 26-51 12-51 Status of Claims Claims 1-20 are pending. Claims 1, 9-11, 13-17, 19, and 20 have been amended as per Applicants' request. Papers Submitted It is hereby acknowledged that the following papers have been received and placed of record in the file: Amended Claims as filed on March 09, 2026 Claim Objections 07-29-01 AIA Claim s 9-11, 13, 15-17, and 20 are objected to because of the following informalities: There are multiple instances of “a process”, but there are prior recitation of “a process” and should be amended “the process” if referring to the previous “a process” . Appropriate correction is required. Claim Rejections - 35 USC § 112 07-30-01 AIA The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. 07-31-01 Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 1 recites “wherein the second memory controller is configured to identify non-performance of a process for a second memory causing congestion at a shared upstream resource” and claim 15 recites “identifying whether the second memory controller is non-performing a process for a second memory causing congestion at a shared upstream resource from the memory controller information”. The description of specification at paragraph [0102] discloses the determination block 704 of Fig.7A (Identify Whether Process For Memory Of Side Band Connected Memory Controller Using Shared Resource) and paragraph [0105] discloses the branch of (identifying that the one or more sideband connected memory controllers is not performing one or more processes for the one or more memories that use the shared upstream resource from the memory controller information (i.e., determination block 704=“No”)”. There is nothing in the specification that discloses identification process of non-performance of a process, and because the specification provides no structural, algorithmic, or procedural details as to what constitutes as identifying the non-performance of a process or how it is executed, the disclosure fails to demonstrate that the inventor was in possession of the claimed invention. “ Similarly, original claims may lack written description when the claims define the invention in functional language specifying a desired result but the specification does not sufficiently describe how the function is performed or the result is achieved. For software, this can occur when the algorithm or steps/procedure for performing the computer function are not explained at all or are not explained in sufficient detail (simply restating the function recited in the claim is not necessarily sufficient). In other words, the algorithm or steps/procedure taken to perform the function must be described with sufficient detail so that one of ordinary skill in the art would understand how the inventor intended the function to be performed. See MPEP §§ 2163.02 and 2181, subsection IV ” (MPEP 2161.01 (I)) Therefore the specification as originally filed does not provide support for “wherein the second memory controller is configured to identify non-performance of a process for a second memory causing congestion at a shared upstream resource” or “identifying whether the second memory controller is non-performing a process for a second memory causing congestion at a shared upstream resource from the memory controller information”. Claims 2-14 and 16-20 depends of claims 1 and 15 and would inherit this deficiency. 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites “wherein the second memory controller is configured to identify non-performance of a process for a second memory causing congestion at a shared upstream resource” and claim 15 recites “identifying whether the second memory controller is non-performing a process for a second memory causing congestion at a shared upstream resource from the memory controller information”. There is nothing in the specification that discloses the identifying non-performance of a process (see 112(a) above), and therefore it is unclear as to how the identification is being perform or what it entails. Is the process performed via polling, checking a list, looking for flags, determining values of resources, etc. Can non-performance of a process mean that the process is already finished or scheduled to perform in the future, or something else since the process is currently not doing anything? It is also unclear as to what the scope of the “identifying non-performance of a process” includes as there is no disclosure on this type of identification. “ A claim, although clear on its face, may also be indefinite when a conflict or inconsistency between the claimed subject matter and the specification disclosure renders the scope of the claim uncertain as inconsistency with the specification disclosure or prior art teachings may make an otherwise definite claim take on an unreasonable degree of uncertainty ” (MPEP 2173.03) Furthermore the claims have been amended to use the term non-performance/non-performing, and there is no disclosure of what such a term means in the specification. It is unclear as to what these terms mean, does it mean that the process is stall, busy, not running, has no processing cycles allocated to it, etc. “ The specification should ideally serve as a glossary to the claim terms so that the examiner and the public can clearly ascertain the meaning of the claim terms. Correspondence between the specification and claims is required by 37 CFR 1.75(d)(1), which provides that claim terms must find clear support or antecedent basis in the specification so that the meaning of the terms may be ascertainable by reference to the specification ” (MPEP 2173.03) and “ The meaning of every term used in a claim should be apparent from the prior art or from the specification and drawings at the time the application is filed. Claim language may not be "ambiguous, vague, incoherent, opaque, or otherwise unclear in describing and defining the claimed invention." In re Packard, 751 F.3d 1307, 1311, 110 USPQ2d 1785, 1787 (Fed. Cir. 2014). Applicants need not confine themselves to the terminology used in the prior art, but are required to make clear and precise the terms that are used to define the invention whereby the metes and bounds of the claimed invention can be ascertained ” (MPEP 2173.05(a)). For purposes of examining examiner will interpret the limitation to the identification of any process that is not currently being executed. It is also unclear as to what is “causing congestion”, the limitation as worded can be interpreted as the act of the memory controller being configured to identifying/performing the identification causing the congestion or the process itself is the cause of the congestions. Examiner suggests the use of a wherein clause to help clarify any misinterpretations, such as “… , wherein the process for a second memory is causing congestion at a shared upstream resource”. For purposes of examination examiner will interpret the limitation as in the suggestion. Claims 2-14 and 16-20 depends of claims 1 and 15 and would inherit this deficiency. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim 1, 5, 6, 9-11, 13, 15-17, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over KOJIMA (US 2009/0271796) (hereinafter Kojima) (October 29, 2009) in view of Nguyen et al. (US 2022/0244966) (hereinafter Nguyen) (published August 04, 2022) . Regarding Claim 1 , Kojima discloses a computing system, comprising: a first memory controller configured to connect to a shared upstream resource via a first channel and to connect to a first memory via a first memory channel; “The master processor 11 and the slave processor 21 are capable of accessing a shared memory 30 . The shared memory 30 is used as a data storage area for tasks to be executed in the master processor 11 and the slave processor 21” (Kojima [0027] see fig. 1 ) “ A dedicated memory 12 is used as a storage area for an OS 120 and an application program (AP) 121 to be read and executed by the master processor 11 and as a storage area for data to be used by those programs” (Kojima [0029] see fig. 1 ) a second memory controller configured to connect to the shared upstream resource via a second channel and to connect to a second memory via a second memory channel, “The master processor 11 and the slave processor 21 are capable of accessing a shared memory 30 . The shared memory 30 is used as a data storage area for tasks to be executed in the master processor 11 and the slave processor 21 ” (Kojima [0027] see fig. 1 ) “On the other hand, a dedicated memory 22 is used as a storage area for an OS 220 and an AP 221 to be read and executed by the slave processor 21 and as a storage area for data to be used by those programs” (Kojima [0031] see fig. 1 ) wherein the second memory controller is configured to identify non-performance of a process for a second memory causing congestion at a shared upstream resource “When a processing request is made from the task A, which is one of the request source tasks, at T4, the communication processing task is activated and creates a child task a. The execution priority of the child task a in the slave processor 21 is set higher than the execution priority of the child task c, which is currently running. Thus, the child task a is dispatched in place of the child task c by the task scheduling after the end of the communication processing task (OP-A) ” (Kojima [0055] see fig. 7, task c is identified as lower priority and is stalled/non-performing at T4, also task b is non-performing at T2 since it has been completed ) But does not explicitly state a first sideband bus configured to connect the first memory controller with the second memory controller and transmit sideband connected memory controller signals between the first memory controller and the second memory controller. However Kojima does disclose communications between the master process and the slave processor (see fig. 1 of Kojima). Nguyen discloses a first sideband bus configured to connect the first memory controller with the second memory controller and transmit sideband connected memory controller signals between the first memory controller and the second memory controller. “To parallelize the boot operation of the second, slave CPU 106(1), the execution of the boot program code 118(0) by the first, master CPU 106(0) also involves setting up a side band communication channel 126 on a side band communication link 128 between the master CPU socket 102(0) and the slave CPU socket 102(1) . The first, master CPU 106(0) is configured to communicate a slave boot-up synchronization signal 130 indicating the boot-up state on the sideband communication channel 126 based on the CPUs 106(0) execution of the boot program code 118(0)” (Nguyen [0021]) It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to modify the communication between the processors of the system in Kojima to be the side band communication channel disclosed by Nguyen. The motivation for doing so would be to reduce congestion and latency as a sideband channel provides a dedicated lane for low-latency signals and ensures that they arrive regardless of how busy the main bus is. Regarding Claim 5 , the combination of Kojima and Nguyen further discloses wherein: the first channel is a first subchannel of a third channel and the second channel is a second subchannel of the third channel; and the first memory channel is a first memory subchannel of a third memory channel and the second memory channel is a second memory subchannel of the third memory channel. The combination of Kojima and Nguyen teach a first channel, a second channel, a first memory channel, and a second memory channel (see rejection above, Fig.1 of Kojima, and Fig. 1 of Nguyen). While Kojima and Nguyen does not explicitly recite that these channels are "subchannels of a third channel" or "subchannels of a third memory channel" this limitation is a mere subdivision or duplication of structural units with no change in function. Under MPEP 2144.04(VI), the "mere duplication of parts has no patentable significance unless a new and unexpected result is produced". Here, the "third channel" or “third memory channel” acts as a mere container or logical grouping for the existing first and second channels or first and second memory channels, and the applicant has not shown that this hierarchical naming produces any result beyond the separate, sequential operation of the channels already known in the art. Furthermore, the configuration of the first and second channels as subchannels of a larger channel or the configuration of the first and second memory channels as subchannels of a larger memory channel is a matter of design choice regarding the logical layout of the computing system. As noted in MPEP 2144.04(VI), the particular placement or grouping of components is generally obvious where the components perform the same function regardless of their label. A person of ordinary skill in the art, seeking to organize data paths in a multi-channel memory system, would have found it obvious to treat individual channels as sub-units of a common bus, “third channel”, or "third memory channel" to simplify addressing or routing logic. The modification is a routine application of well-known architectural principles and provides no unexpected technical advantage. Regarding Claim 6 , the combination of Kojima and Nguyen further discloses wherein the first channel is a first subchannel of a third channel and the second channel is a second subchannel of a fourth channel; and the first memory channel is a first memory subchannel of a third memory channel and the second memory channel is a second memory subchannel of a fourth memory channel. While the combination of Kojima and Nguyen does not explicitly label the first channel as a subchannel of a "third channel", the second channel as a subchannel of a "fourth channel", the first memory channel as a subchannel of a "third memory channel", and the second memory channel as a subchannel of a "fourth memory channel", this limitation is a mere subdivision or redundant duplication of structural units. Under MPEP 2144.04(VI), the "mere duplication of parts has no patentable significance unless a new and unexpected result is produced." In this instance, the "third" and "fourth" channels and the "third" and "fourth" memory channels function as mere logical containers or higher-level abstractions for the existing channels already taught by Kojima and Nguyen. The applicant has not demonstrated that nesting these channels within additional named hierarchies produces any functional shift beyond the data transfer operations already known in the art. Furthermore, the arrangement of the first and second channels as sub-units of separate "third" and "fourth" channels is a routine design choice regarding the hierarchical naming and logical layout of the computing system. As noted in MPEP 2144.04(VI), the particular grouping or labeling of components is generally obvious where the components perform the same function regardless of their hierarchical designation. A person of ordinary skill in the art, seeking to scale or categorize data paths in a multi-channel architecture, would have found it obvious to classify individual channels as "subchannels" of respective parent controllers or buses to facilitate organized system mapping. This modification is a routine application of well-known architectural principles and provides no unexpected technical advantage over the separate channels taught in the prior art. Regarding Claim 9 , Kojima further discloses wherein the first memory controller comprises a processor system configured to: poll the second memory controller for memory controller information; “A task which is executed in the master processor 11 and makes a processing request to the slave processor 21 is referred to hereinafter as a "request source task". In Step S11, it is determined whether transmission of a processing request to the slave processor 21 is possible. Specifically, it may be determined whether an available free space of the shared memory 30 is large enough for interprocessor communication, that is, whether it is large enough to store communication data containing a processing request ” (Kojima [0034] checks the slave processor information ) identify whether the second memory controller is non-performing a process for the second memory, causing the congestion at the shared upstream resource from the memory controller information; and “When a processing request is made from the task A, which is one of the request source tasks, at T4, the communication processing task is activated and creates a child task a. The execution priority of the child task a in the slave processor 21 is set higher than the execution priority of the child task c, which is currently running. Thus, the child task a is dispatched in place of the child task c by the task scheduling after the end of the communication processing task (OP-A) ” (Kojima [0055] see fig. 7, task c is identified as lower priority and is stalled/non-performing at T4, also task b is non-performing at T2 since it has been completed ) provide a scheduler executed by the processor system with an indication to schedule a process for the first memory that uses the shared upstream resource in response to identifying that the second memory controller is non-performing a process for the second memory causing the congestion at the shared upstream resource. “In Step S16, the request source task waits until processing of the slave processor 21 is completed. The request source task suspends execution and changes to "wait status", and then sequentially changes to "ready status" and to "run status" in response to reception of an interrupt signal from the slave processor 21, which is described later, and finally confirms communication data indicating a processing completion result . The processing to change the operating status of the request source task to "ready status" in response to the occurrence of an interrupt from the slave processor 21 can be easily implemented by an interrupt handler that is activated upon occurrence of an interrupt” (Kojima [0043]) “Specifically, the interrupt handler may notify the occurrence of a processing request to the communication processing task in "wait status", change the communication processing task to "ready status", and request task scheduling to the OS. It is preferred to give the highest execution priority in the slave processor 21 to the communication processing task in order that the communication processing task is executed preferentially ” (Kojima [0044]) “When a processing request is made from the task A, which is one of the request source tasks, at T4, the communication processing task is activated and creates a child task a. The execution priority of the child task a in the slave processor 21 is set higher than the execution priority of the child task c, which is currently running. Thus, the child task a is dispatched in place of the child task c by the task scheduling after the end of the communication processing task (OP-A) ” (Kojima [0055]) Regarding Claim 10 , Kojima further discloses wherein the processor system is further configured to: identify whether the second memory controller is non-scheduled to perform a process for the second memory causing the congestion at the shared upstream resource from the memory controller information in response to identifying that the second memory controller is non performing a process for the second memory causing the congestion at the shared upstream resource; and “If it is determined that a processing request to the slave processor 21 is acceptable (YES in Step S11), a memory area for interprocessor communication is reserved in Step S12. Specifically, a communication management flag is set in the memory space reserved in advance for interprocessor communication. The communication management flag is flag information indicating whether the area for storing communication data exchanged by interprocessor communication is in use or not ” (Kojima [0035] the flag would indicated if there is a process being performed or scheduled to be performed using the shared memory ) “Next, when a processing request is made from the task C, which is one of the request source tasks, at time T2, the communication processing task creates a child task c in the slave processor 21. The child task c starts running immediately after the end of the communication processing task because there is no other child task (OP-C1)” (Kojima [0053] at right before T2 there is no scheduled process to be performed ) provide the scheduler executed by the processor system with the indication to schedule a process for the first memory that uses the shared upstream resource in response to identifying that the second memory controller is non-performing a process for the second memory causing the congestion at the shared upstream resource and identifying that the second memory controller is non scheduled to perform a process for the second memory causing the congestion at the shared upstream resource. “Specifically, the interrupt handler may notify the occurrence of a processing request to the communication processing task in "wait status", change the communication processing task to "ready status", and request task scheduling to the OS. It is preferred to give the highest execution priority in the slave processor 21 to the communication processing task in order that the communication processing task is executed preferentially ” (Kojima [0044]) “Next, when a processing request is made from the task C, which is one of the request source tasks, at time T2, the communication processing task creates a child task c in the slave processor 21. The child task c starts running immediately after the end of the communication processing task because there is no other child task (OP-C1) ” (Kojima [0053] when there is no tasks in progress at T2, task C is scheduled and executed ) Regarding Claim 11 , Kojima further discloses wherein in response to identifying that the second memory controller is non-performing a process for the second memory causing the congestion at the shared upstream resource the processor system is further configured to: identify whether the second memory controller is scheduled to perform a process for the second memory causing the congestion at the shared upstream resource from the memory controller information; identify whether the first memory controller has priority to perform a process for the first memory using the shared upstream resource over the second memory controller; and provide the scheduler executed by the processor system with the indication to schedule a process for the first memory that uses the shared upstream resource in response to identifying that the second memory controller is scheduled to perform a process for the second memory causing the congestion at the shared upstream resource, and identifying that the first memory controller has priority to perform a process for the first memory using the shared upstream resource over the second memory controller. “When a processing request is made from the task A , which is one of the request source tasks, at T4, the communication processing task is activated and creates a child task a. The execution priority of the child task a in the slave processor 21 is set higher than the execution priority of the child task c , which is currently running. Thus, the child task a is dispatched in place of the child task c by the task scheduling after the end of the communication processing task (OP-A) ” (Kojima [0055] child tasks c and d are created from the master processor, child task A also from the master processor has priority and is scheduled to be performed first ) Regarding Claim 13 , Kojima further discloses wherein the first memory controller comprises a processor system configured to: poll the second memory controller for memory controller information; “A task which is executed in the master processor 11 and makes a processing request to the slave processor 21 is referred to hereinafter as a "request source task". In Step S11, it is determined whether transmission of a processing request to the slave processor 21 is possible. Specifically, it may be determined whether an available free space of the shared memory 30 is large enough for interprocessor communication, that is, whether it is large enough to store communication data containing a processing request ” (Kojima [0034] checks the slave processor information ) identify whether the second memory controller is performing a process for the second memory causing the congestion at the shared upstream resource from the memory controller information; and “When a processing request is made from the task A, which is one of the request source tasks, at T4, the communication processing task is activated and creates a child task a. The execution priority of the child task a in the slave processor 21 is set higher than the execution priority of the child task c, which is currently running. Thus, the child task a is dispatched in place of the child task c by the task scheduling after the end of the communication processing task (OP-A) ” (Kojima [0055] see fig. 7, task c is identified as lower priority and is stalled/non-performing at T4, also task b is non-performing at T2 since it has been completed ) provide a scheduler executed by the processor system with an indication to postpone a process for the first memory using the shared upstream resource in response to identifying that the second memory controller is performing a process for the second memory causing the congestion at the shared upstream resource. “In Step S16, the request source task waits until processing of the slave processor 21 is completed. The request source task suspends execution and changes to "wait status", and then sequentially changes to "ready status" and to "run status" in response to reception of an interrupt signal from the slave processor 21, which is described later, and finally confirms communication data indicating a processing completion result . The processing to change the operating status of the request source task to "ready status" in response to the occurrence of an interrupt from the slave processor 21 can be easily implemented by an interrupt handler that is activated upon occurrence of an interrupt” (Kojima [0043]) “Specifically, the interrupt handler may notify the occurrence of a processing request to the communication processing task in "wait status", change the communication processing task to "ready status", and request task scheduling to the OS. It is preferred to give the highest execution priority in the slave processor 21 to the communication processing task in order that the communication processing task is executed preferentially ” (Kojima [0044]) “This is because the relative relationship of the execution priorities of the request source tasks C and D in the master processor 11 is reflected on the execution priorities of the child tasks c and d. Thus, the child task d does not start running until the other tasks with the higher execution priority than the child task d end or those tasks release the rights to use the slave processor 21 for some reason ” (Kojima [0054] task D is postponed due to a running child task C that has a higher priority ) Regarding Claim 15 , Kojima discloses a method of memory controller scheduling implemented by at least one processor system of a first memory controller of a first memory, comprising: polling a second memory controller for memory controller information; “A task which is executed in the master processor 11 and makes a processing request to the slave processor 21 is referred to hereinafter as a "request source task". In Step S11, it is determined whether transmission of a processing request to the slave processor 21 is possible. Specifically, it may be determined whether an available free space of the shared memory 30 is large enough for interprocessor communication, that is, whether it is large enough to store communication data containing a processing request ” (Kojima [0034] checks the slave processor information ) identifying whether the second memory controller is non-performing a process for a second memory causing congestion at a shared upstream resource from the memory controller information; and “When a processing request is made from the task A, which is one of the request source tasks, at T4, the communication processing task is activated and creates a child task a. The execution priority of the child task a in the slave processor 21 is set higher than the execution priority of the child task c, which is currently running. Thus, the child task a is dispatched in place of the child task c by the task scheduling after the end of the communication processing task (OP-A) ” (Kojima [0055] see fig. 7, task c is identified as lower priority and is stalled/non-performing at T4, also task b is non-performing at T2 since it has been completed ) providing a scheduler executed by the at least one processor system with an indication to schedule a process for the first memory that uses the shared upstream resource in response to identifying that the second memory controller is non-performing a process for the second memory causing the congestion at the shared upstream resource. “In Step S16, the request source task waits until processing of the slave processor 21 is completed. The request source task suspends execution and changes to "wait status", and then sequentially changes to "ready status" and to "run status" in response to reception of an interrupt signal from the slave processor 21, which is described later, and finally confirms communication data indicating a processing completion result . The processing to change the operating status of the request source task to "ready status" in response to the occurrence of an interrupt from the slave processor 21 can be easily implemented by an interrupt handler that is activated upon occurrence of an interrupt” (Kojima [0043]) “Specifically, the interrupt handler may notify the occurrence of a processing request to the communication processing task in "wait status", change the communication processing task to "ready status", and request task scheduling to the OS. It is preferred to give the highest execution priority in the slave processor 21 to the communication processing task in order that the communication processing task is executed preferentially ” (Kojima [0044]) But does not explicitly state via a sideband bus connecting the first memory controller and the second memory controller. Nguyen discloses via a sideband bus connecting the first memory controller and the second memory controller. “To parallelize the boot operation of the second, slave CPU 106(1), the execution of the boot program code 118(0) by the first, master CPU 106(0) also involves setting up a side band communication channel 126 on a side band communication link 128 between the master CPU socket 102(0) and the slave CPU socket 102(1) . The first, master CPU 106(0) is configured to communicate a slave boot-up synchronization signal 130 indicating the boot-up state on the sideband communication channel 126 based on the CPUs 106(0) execution of the boot program code 118(0)” (Nguyen [0021]) It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to modify the communication between the processors of the system in Kojima to be the side band communication channel disclosed by Nguyen. The motivation for doing so would be to reduce congestion and latency as a sideband channel provides a dedicated lane for low-latency signals and ensures that they arrive regardless of how busy the main bus is. Regarding Claim 16 , Kojima further discloses further comprising, in response to identifying that the second memory controller is non-performing a process for the second memory causing the congestion at the shared upstream resource: identifying whether the second memory controller is non-scheduled to perform a process for the second memory causing the congestion at the shared upstream resource from the memory controller information in response to identifying that the second memory controller is non-performing a process for the second memory causing the congestion at the shared upstream resource, “If it is determined that a processing request to the slave processor 21 is acceptable (YES in Step S11), a memory area for interprocessor communication is reserved in Step S12. Specifically, a communication management flag is set in the memory space reserved in advance for interprocessor communication. The communication management flag is flag information indicating whether the area for storing communication data exchanged by interprocessor communication is in use or not ” (Kojima [0035] the flag would indicated if there is a process being performed or scheduled to be performed using the shared memory ) “Next, when a processing request is made from the task C, which is one of the request source tasks, at time T2, the communication processing task creates a child task c in the slave processor 21. The child task c starts running immediately after the end of the communication processing task because there is no other child task (OP-C1)” (Kojima [0053] at right before T2 there is no scheduled process to be performed ) wherein providing the scheduler executed by the at least one processor system with the indication to schedule the process for the first memory that uses the shared upstream resource in response to identifying that the second memory controller is non-performing a process for the second memory causing the congestion at the shared upstream resource comprises providing the scheduler executed by the at least one processor system with the indication to schedule the process for the first memory that uses the shared upstream resource in response to identifying that the second memory controller is non-scheduled to perform a process for the second memory causing the congestion at the shared upstream resource. “Specifically, the interrupt handler may notify the occurrence of a processing request to the communication processing task in "wait status", change the communication processing task to "ready status", and request task scheduling to the OS. It is preferred to give the highest execution priority in the slave processor 21 to the communication processing task in order that the communication processing task is executed preferentially ” (Kojima [0044]) “Next, when a processing request is made from the task C, which is one of the request source tasks, at time T2, the communication processing task creates a child task c in the slave processor 21. The child task c starts running immediately after the end of the communication processing task because there is no other child task (OP-C1) ” (Kojima [0053] when there is no tasks in progress at T2, task C is scheduled and executed ) Regarding Claim 17 , Kojima further discloses further comprising, in response to identifying that the second memory controller is non-performing a process for the second memory causing the congestion at the shared upstream resource: identifying whether the second memory controller is scheduled to perform a process for the second memory causing the congestion at the shared upstream resource from the memory controller information; and identifying whether the first memory controller has priority to perform a process for the first memory using the shared upstream resource over the second memory controller, wherein providing the scheduler executed by the at least one processor system with the indication to schedule the process for the first memory that uses the shared upstream resource in response to identifying that the second memory controller is non-performing a process for the second memory causing the congestion at the shared upstream resource comprises providing the scheduler executed by the at least one processor system with the indication to schedule the process for the first memory that uses the shared upstream resource in response to identifying that the second memory controller is scheduled to perform a process for the second memory causing the congestion at the shared upstream resource and identifying that the first memory controller has priority to perform a process for the first memory using the shared upstream resource over the second memory controller. “When a processing request is made from the task A , which is one of the request source tasks, at T4, the communication processing task is activated and creates a child task a. The execution priority of the child task a in the slave processor 21 is set higher than the execution priority of the child task c , which is currently running. Thus, the child task a is dispatched in place of the child task c by the task scheduling after the end of the communication processing task (OP-A) ” (Kojima [0055] child tasks c and d are created from the master processor, child task A also from the master processor has priority and is scheduled to be performed first ) Regarding Claim 19 , Kojima further discloses further comprising providing the scheduler executed by the at least one processor system with an indication to postpone the process for the first memory using the shared upstream resource in response to identifying that the second memory controller is performing a process for the second memory causing the congestion at the shared upstream resource. “In Step S16, the request source task waits until processing of the slave processor 21 is completed. The request source task suspends execution and changes to "wait status", and then sequentially changes to "ready status" and to "run status" in response to reception of an interrupt signal from the slave processor 21, which is described later, and finally confirms communication data indicating a processing completion result . The processing to change the operating status of the request source task to "ready status" in response to the occurrence of an interrupt from the slave processor 21 can be easily implemented by an interrupt handler that is activated upon occurrence of an interrupt” (Kojima [0043]) “Specifically, the interrupt handler may notify the occurrence of a processing request to the communication processing task in "wait status", change the communication processing task to "ready status", and request task scheduling to the OS. It is preferred to give the highest execution priority in the slave processor 21 to the communication processing task in order that the communication processing task is executed preferentially ” (Kojima [0044]) “This is because the relative relationship of the execution priorities of the request source tasks C and D in the master processor 11 is reflected on the execution priorities of the child tasks c and d. Thus, the child task d does not start running until the other tasks with the higher execution priority than the child task d end or those tasks release the rights to use the slave processor 21 for some reason ” (Kojima [0054] task D is postponed due to a running child task C that has a higher priority ) 07-22-aia AIA Claim s 2-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kojima (October 29, 2009) and Nguyen (published August 04, 2022) as applied to claim 1 above, and further in view of Zilavy (US 2002/0161975) (hereinafter Zilavy) (published October 31, 2002) . Regarding Claim 2 , the combination of Kojima and Nguyen disclosed the system of claim 1, but does not explicitly state further comprising a third memory controller configured to connect to the shared upstream resource via a third channel and to connect to a third memory via a third memory channel, wherein the first sideband bus is further configured to: connect the first memory controller with the third memory controller; connect the second memory controller with the third memory controller; and transmit sideband connected memory controller signals between the first memory controller and the third memory controller and between the second memory controller and the third memory controller. Zilavy discloses further comprising a third memory controller configured to connect to the shared upstream resource via a third channel and to connect to a third memory via a third memory channel, wherein the first sideband bus is further configured to: connect the first memory controller with the third memory controller; connect the second memory controller with the third memory controller; and transmit sideband connected memory controller signals between the first memory controller and the third memory controller and between the second memory controller and the third memory controller. “Unshared "clean data present" sideband signals, or HITC signals (on conductors 44, 46, 50, and 52 ) are added to the computer system 10 to enable cache to cache copying of clean data. (The term "sideband" refers to the fact that the signals are not a part of the standard bus architecture in the preferred exemplary embodiment.) Each of the sideband signal conductors 44-52 are connected to every processor 12-20 in the computer system 10 ” (Zilavy [0032]) It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the connecting of the sideband signals to multiple processors in Zilavy with the system in the combination of Kojima and Nguyen. The motivation for doing so would be to reduce congestion and latency for the third controller/processor as a sideband channel provides a dedicated lane for low-latency signals and ensures that they arrive regardless of how busy the main bus is. Regarding Claim 3 , the combination of Kojima, Nguyen, and Zilavy further discloses wherein: the first channel, the second channel, and the third channel are subchannels of a fourth channel; and the first memory channel, the second memory channel, and the third memory channel are memory subchannels of a fourth memory channel. The combination of Kojima, Nguyen, and Zilavy teaches teach a first channel, a second channel, third channel, a first memory channel, second memory channel, and a third memory channel (see rejection above, Fig.1 of Kojima, Fig. 1 of Nguyen, and Fig. 1 of Zilavy). While Kojima, Nguyen, and Zilavy does not explicitly recite that these channels are "subchannels of a fourth channel" or “subchannels of a fourth memory channel”, this limitation is a mere subdivision or duplication of structural units with no change in function. Under MPEP 2144.04(VI), the "mere duplication of parts has no patentable significance unless a new and unexpected result is produced". Here, the "fourth channel" or “fourth memory channel” acts as a mere container or logical grouping for the existing first, second, and third channels, or first, second, and third memory channels, and the applicant has not shown that this hierarchical naming produces any result beyond the separate, sequential operation of the channels already known in the art. Furthermore, the configuration of the first, second, and third channels as subchannels of a larger channel or the configuration of the first, second, and third memory channels as subchannels of a larger memory channel is a matter of design choice regarding the logical layout of the computing system. As noted in MPEP 2144.04(VI), the particular placement or grouping of components is generally obvious where the components perform the same function regardless of their label. A person of ordinary skill in the art, seeking to organize data paths in a multi-channel memory system, would have found it obvious to treat individual channels as sub-units of a common bus, "fourth channel", or “fourth memory channel” to simplify addressing or routing logic. The modification is a routine application of well-known architectural principles and provides no unexpected technical advantage. Regarding Claim 4 , The combination of Kojima and Nguyen disclosed the system of claim 1 but does not explicitly state further comprising: a third memory controller configured to connect to the shared upstream resource via a third channel and to connect to a third memory via a third memory channel; and a second sideband bus configured to connect the first memory controller and the third memory controller and configured to transmit sideband connected memory controller signals between the first memory controller and the third memory controller. Zilavy discloses further comprising: a third memory controller configured to connect to the shared upstream resource via a third channel and to connect to a third memory via a third memory channel; and “ the address and data buses 36 and 38 and the HIT and HITM signals 42 and 40 allow processors to coordinate transfers of data throughout the computer system 10 . A first example will now be given which describes the behavior of the computer system 10 having a shared "clean data present" signal 42 without the sideband signals which enable cache to cache copying of clean data, to be described hereinafter. In this first example, data is contained in the external memory 32 and in the caches 24 and 26 of processors 1 14 and 2 16 (both in clean form)” (Zilavy [0029]) a second sideband bus configured to connect the first memory controller and the third memory controller and configured to transmit sideband connected memory controller signals between the first memory controller and the third memory controller. “Unshared "clean data present" sideband signals, or HITC signals (on conductors 44, 46, 50, and 52 ) are added to the computer system 10 to enable cache to cache copying of clean data. (The term "sideband" refers to the fact that the signals are not a part of the standard bus architecture in the preferred exemplary embodiment.) Each of the sideband signal conductors 44-52 are connected to every processor 12-20 in the computer system 10 ” (Zilavy [0032] see fig. 1 there are four buses/conductors for the HITC signals ) It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the connecting of the sideband signals to multiple processors in Zilavy with the system in the combination of Kojima and Nguyen. The motivation for doing so would be to reduce congestion and latency for the third controller/processor as a sideband channel provides a dedicated lane for low-latency signals and ensures that they arrive regardless of how busy the main bus is . 07-22-aia AIA Claim s 7 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kojima (October 29, 2009) and Nguyen (published August 04, 2022) as applied to claim 1 above, and further in view of Stufflebeam (US 6,460,106) (hereinafter Stufflebeam) (published October 1, 2002) . Regarding Claim 7 , the combination of Kojima and Nguyen disclosed the system of claim 1, but does not explicitly state wherein the first sideband bus is a parallel bus. Stufflebeam discloses wherein the first sideband bus is a parallel bus. “These sideband signals typically connect to the I/O controller but may be connected to virtually any component within the computer. Examples of sideband signals include power and ground signals, interrupt signals, and I/O signals such as serial and parallel port signals , keyboard and mouse signals, and audio and video signals” (Stufflebeam col 3 lines 6-15) It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to configure the side band bus as either a parallel bus or a serial bus because these represent a limited number of identified, predictable solutions for interconnecting components withing a computing system. A designer seeking to establish a side band communication path between processors would be faces with the routine technical choice of selecting a bus width based on the specific trade-offs between pin count and data throughput and given that both serial and parallel interfaces are well-known standard options the selection of one over the other is the product of ordinary skill and common sense. Furthermore there is a high expectation of success in the implementation of either bus types to achieve the same results of data transmission. Regarding Claim 8 , the combination of Kojima and Nguyen disclosed the system of claim 1, but does not explicitly state wherein the first sideband bus is a serial bus. Stufflebeam discloses wherein the first sideband bus is a serial bus. “These sideband signals typically connect to the I/O controller but may be connected to virtually any component within the computer. Examples of sideband signals include power and ground signals, interrupt signals, and I/O signals such as serial and parallel port signals , keyboard and mouse signals, and audio and video signals” (Stufflebeam col 3 lines 6-15) It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to configure the side band bus as either a parallel bus or a serial bus because these represent a limited number of identified, predictable solutions for interconnecting components withing a computing system. A designer seeking to establish a side band communication path between processors would be faces with the routine technical choice of selecting a bus width based on the specific trade-offs between pin count and data throughput and given that both serial and parallel interfaces are well-known standard options the selection of one over the other is the product of ordinary skill and common sense. Furthermore there is a high expectation of success in the implementation of either bus types to achieve the same results of data transmission . 07-22-aia AIA Claim s 12 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kojima (October 29, 2009) and Nguyen (published August 04, 2022) as applied to claim s 1 and 15 above, and further in view of Wang et al. (US 2022/0028450) (hereinafter Wang) (published January 27, 2022) . Regarding Claim 12 , the combination of Kojima and Nguyen disclosed the system of claim 12 but does not explicitly state wherein the process for the first memory is at least one of an all-bank refresh, a per-bank refresh, transaction batching, DRAM memory calibration, or DRAM memory training. Wang discloses wherein the process for the first memory is at least one of an all-bank refresh, a per-bank refresh, transaction batching, DRAM memory calibration, or DRAM memory training. “ Automatic refresh logic 220 enables the memory controller to periodically refresh the DRAMs with the auto-refresh commands . Automatic refresh logic 220 may be limited, such as by only allowing selecting a single rank, one bank, or multiple banks, at a time, for example. Fine granularity automatic refresh may be included with automatic refresh logic 220 and may be utilized for DDR4 memory products. Automatic refresh logic 220 may include logic that tracks when a refresh is needed and may send refresh command requests to arbiter 260 for subsequent transmission to the DRAM based on the tracking. Automatic refresh logic 220 may enable per bank refresh as supported in DRAM technologies where it is permitted , such as LPDDR4/HBM, for example” (Wang [0031]) It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the processes of per back refresh with the system in the combination of Kojima and Nguyen. The motivation for doing so would be to improve data integrity through the application of automatically refreshing the DRAM memories. Regarding Claim 18 , the combination of Kojima and Nguyen disclosed the method of claim 15 but does not explicitly state wherein the process for the first memory is at least one of an all-bank refresh, a per-bank refresh, transaction batching, DRAM memory calibration, or DRAM memory training. Wang discloses wherein the process for the first memory is at least one of an all-bank refresh, a per-bank refresh, transaction batching, DRAM memory calibration, or DRAM memory training. “ Automatic refresh logic 220 enables the memory controller to periodically refresh the DRAMs with the auto-refresh commands . Automatic refresh logic 220 may be limited, such as by only allowing selecting a single rank, one bank, or multiple banks, at a time, for example. Fine granularity automatic refresh may be included with automatic refresh logic 220 and may be utilized for DDR4 memory products. Automatic refresh logic 220 may include logic that tracks when a refresh is needed and may send refresh command requests to arbiter 260 for subsequent transmission to the DRAM based on the tracking. Automatic refresh logic 220 may enable per bank refresh as supported in DRAM technologies where it is permitted , such as LPDDR4/HBM, for example” (Wang [0031]) It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the processes of per back refresh with the system in the combination of Kojima and Nguyen. The motivation for doing so would be to improve data integrity through the application of automatically refreshing the DRAM memories . 07-22-aia AIA Claim s 14 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kojima (October 29, 2009) and Nguyen (published August 04, 2022) as applied to claim s 1 and 15 above, and further in view of Nagarajan et al. (US 2016/0188469) (hereinafter Nagarajan) (published June 30, 2016) . Regarding Claim 14 , the combination of Kojima and Nguyen disclosed the system of claim 1, and Kojima further discloses wherein the first memory controller comprises a processor system configured to: poll the second memory controller for memory controller information; “A task which is executed in the master processor 11 and makes a processing request to the slave processor 21 is referred to hereinafter as a "request source task". In Step S11, it is determined whether transmission of a processing request to the slave processor 21 is possible. Specifically, it may be determined whether an available free space of the shared memory 30 is large enough for interprocessor communication, that is, whether it is large enough to store communication data containing a processing request ” (Kojima [0034] checks the slave processor information ) identify whether the second memory controller is performing a process for the second memory causing the congestion at the shared upstream resource from the memory controller information; “ FIG. 7 is a timing chart showing a transition process of execution tasks in the master processor 11 and the slave processor 21 in the information processing system 1 according to the embodiment . The information processing system 1 is capable of executing the tasks in the same sequence as in the single processor shown in FIG. 6, in spite of a multiprocessor configuration. This is described in detail hereinbelow” (Kojima [0055] see fig. 7, tasks being performed are identified whenever they are running ) But does not explicitly state identify whether a delay for implementing a process for the first memory using the shared upstream resource exceeds a delay threshold; and provide a scheduler executed by the processor system with an indication to schedule the process for the first memory using the shared upstream resource in response to identifying that the second memory controller is performing a process for the second memory causing the congestion at the shared upstream resource and identifying that the delay for implementing the process for the first memory using the shared upstream resource exceeds the delay threshold. Nagarajan and Kojima discloses identify whether a delay for implementing a process for the first memory using the shared upstream resource exceeds a delay threshold; and “Once the last read request is sent to the memory controller, if the number of entries in the flush pool is above the casual flush limit, a counter called the casual flush timer starts incrementing every′ clock cycle. If no new read requests to memory are received by the fabric and the casual flush timer reaches the value specified by the casual flush delay , which is a threshold stored in a configuration register, the memory scheduler begins sending write requests to the memory controller. This casual flush continues until the number of entries in the flush pool is less than the casual flush limit or until a new read request is received by the fabric” (Nagarajan [0107]) provide a scheduler executed by the processor system with an indication to schedule the process for the first memory using the shared upstream resource in response to identifying that the second memory controller is performing a process for the second memory causing the congestion at the shared upstream resource and identifying that the delay for implementing the process for the first memory using the shared upstream resource exceeds the delay threshold. “Once the last read request is sent to the memory controller, if the number of entries in the flush pool is above the casual flush limit, a counter called the casual flush timer starts incrementing every′ clock cycle. If no new read requests to memory are received by the fabric and the casual flush timer reaches the value specified by the casual flush delay , which is a threshold stored in a configuration register, the memory scheduler begins sending write requests to the memory controller. This casual flush continues until the number of entries in the flush pool is less than the casual flush limit or until a new read request is received by the fabric ” (Nagarajan [0107]) “Specifically, the interrupt handler may notify the occurrence of a processing request to the communication processing task in "wait status", change the communication processing task to "ready status", and request task scheduling to the OS. It is preferred to give the highest execution priority in the slave processor 21 to the communication processing task in order that the communication processing task is executed preferentially ” (Kojima [0044]) “Then, when a processing request is made from the task D, which is one of the request source tasks, at T3 during the running of the child task c, the communication processing task is activated and creates a child task d . The execution priority of the child task d in the slave processor 21 is set lower than the execution priority of the child task c, which is currently running” (Kojima [0054] task D is scheduled during processing of child task C ) It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the delay before flushing the commands according to a threshold in Nagarajan with the system in the combination of Kojima and Nguyen. The motivation for doing so would be to improve efficiency by not clogging up the memory pipeline and be able to schedule the bursts of commands according to priority as disclosed by Nagarajan. “ the memory scheduler uses configurable threshold values to specify when to start and stop transferring a burst of write requests to the memory controller. The memory scheduler may perform different types of transfers of write data to memory. e.g., a high priority transfer and a low priority transfer, also termed herein as a high priority flush of write requests and casual flush of write requests to memory, respectively. When the number of entries in the flush pool reaches or exceeds a threshold value (the flush high water mark), the memory scheduler begins scheduling a high priority write flush to memory and begins sending write requests to the memory controller ” (Nagarajan [0106]) Regarding Claim 20 , the combination of Kojima and Nguyen disclosed the method of claim 15, but does not explicitly state further comprising: identifying whether a delay for implementing the process for the first memory using the shared upstream resource exceeds a delay threshold; and providing a scheduler executed by the at least one processor system with an indication to schedule the process for the first memory using the shared upstream resource in response to identifying that the second memory controller is performing a process for the second memory causing the congestion at the shared upstream resource and identifying that the delay for implementing the process for the first memory using the shared upstream resource exceeds the delay threshold. Nagarajan and Kojima discloses further comprising: identifying whether a delay for implementing the process for the first memory using the shared upstream resource exceeds a delay threshold; and “Once the last read request is sent to the memory controller, if the number of entries in the flush pool is above the casual flush limit, a counter called the casual flush timer starts incrementing every′ clock cycle. If no new read requests to memory are received by the fabric and the casual flush timer reaches the value specified by the casual flush delay , which is a threshold stored in a configuration register, the memory scheduler begins sending write requests to the memory controller. This casual flush continues until the number of entries in the flush pool is less than the casual flush limit or until a new read request is received by the fabric” (Nagarajan [0107]) providing a scheduler executed by the at least one processor system with an indication to schedule the process for the first memory using the shared upstream resource in response to identifying that the second memory controller is performing a process for the second memory causing the congestion at the shared upstream resource and identifying that the delay for implementing the process for the first memory using the shared upstream resource exceeds the delay threshold. “Once the last read request is sent to the memory controller, if the number of entries in the flush pool is above the casual flush limit, a counter called the casual flush timer starts incrementing every′ clock cycle. If no new read requests to memory are received by the fabric and the casual flush timer reaches the value specified by the casual flush delay , which is a threshold stored in a configuration register, the memory scheduler begins sending write requests to the memory controller. This casual flush continues until the number of entries in the flush pool is less than the casual flush limit or until a new read request is received by the fabric ” (Nagarajan [0107]) “Specifically, the interrupt handler may notify the occurrence of a processing request to the communication processing task in "wait status", change the communication processing task to "ready status", and request task scheduling to the OS. It is preferred to give the highest execution priority in the slave processor 21 to the communication processing task in order that the communication processing task is executed preferentially ” (Kojima [0044]) “Then, when a processing request is made from the task D, which is one of the request source tasks, at T3 during the running of the child task c, the communication processing task is activated and creates a child task d . The execution priority of the child task d in the slave processor 21 is set lower than the execution priority of the child task c, which is currently running” (Kojima [0054] task D is scheduled during processing of child task C ) It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the delay before flushing the commands according to a threshold in Nagarajan with the system in the combination of Kojima and Nguyen. The motivation for doing so would be to improve efficiency by not clogging up the memory pipeline and be able to schedule the bursts of commands according to priority as disclosed by Nagarajan. “ the memory scheduler uses configurable threshold values to specify when to start and stop transferring a burst of write requests to the memory controller. The memory scheduler may perform different types of transfers of write data to memory. e.g., a high priority transfer and a low priority transfer, also termed herein as a high priority flush of write requests and casual flush of write requests to memory, respectively. When the number of entries in the flush pool reaches or exceeds a threshold value (the flush high water mark), the memory scheduler begins scheduling a high priority write flush to memory and begins sending write requests to the memory controller ” (Nagarajan [0106]) Response to Arguments Rejections under 35 U.S.C. § 112 07-37 AIA Applicant's arguments filed March 09, 2026 have been fully considered but they are not persuasive. Applicant Argues: a) The applicant asserts that the Office's interpretation extends the scope of the claims beyond their plain and ordinary meaning. Specifically, the claims do not encompass all forms of processing with congestion, but rather address congestion caused by shared upstream contention. The Applicant contends that the claims satisfy §112(b) when, viewed in light of the specification and prosecution history, that is, the claims reasonably inform a person of ordinary skill in the art ("POSITA") of the scope of the invention with reasonable certainty. With respect to (a) , applicant appears to misinterpret the 112(b) rejection, the 112(b) rejection in the non-final action is directed to being unsure of what is causing the congestion, the language in the claims can have multiple interpretations as if it is the memory controller causing the congestion or the process causing the congestion. A suggestion was made by the examiner (above in 112(b)) to modify that part of the limitation with a wherein clause to help clarify and not have any confusion. Rejections under 35 U.S.C. § 103 07-37 AIA Applicant's arguments filed March 09, 2026 have been fully considered but they are not persuasive. Applicant Argues: b) Neither, KOJIMA nor NGUYEN teaches, suggests, or discloses "a second memory controller configured to connect to the shared upstream resource via a second channel and to connect to a second memory via a second memory channel, wherein the second memory controller is configured to identify non-performing a process for a second memory causing congestion at a shared upstream resource" as recited in amended independent claim 1. With respect to (b) , the amended portions of “wherein the second memory controller is configured to identify non-performing a process for a second memory causing congestion at a shared upstream resource” is interpreted as the identification of a process that is currently not being executed and is disclosed by Kojima at paragraph [0055]. Conclusion 07-40 AIA Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SIDNEY LI whose telephone number is (571)270-5967. The examiner can normally be reached Monday to Friday 10:00 AM to 6:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan P Savla can be reached at (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /S.L./Examiner, Art Unit 2137 /Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137 Application/Control Number: 18/748,173 Page 2 Art Unit: 2137 Application/Control Number: 18/748,173 Page 3 Art Unit: 2137 Application/Control Number: 18/748,173 Page 4 Art Unit: 2137 Application/Control Number: 18/748,173 Page 5 Art Unit: 2137 Application/Control Number: 18/748,173 Page 6 Art Unit: 2137 Application/Control Number: 18/748,173 Page 9 Art Unit: 2137 Application/Control Number: 18/748,173 Page 10 Art Unit: 2137 Application/Control Number: 18/748,173 Page 11 Art Unit: 2137 Application/Control Number: 18/748,173 Page 14 Art Unit: 2137 Application/Control Number: 18/748,173 Page 16 Art Unit: 2137 Application/Control Number: 18/748,173 Page 17 Art Unit: 2137 Application/Control Number: 18/748,173 Page 18 Art Unit: 2137 Application/Control Number: 18/748,173 Page 19 Art Unit: 2137 Application/Control Number: 18/748,173 Page 20 Art Unit: 2137 Application/Control Number: 18/748,173 Page 21 Art Unit: 2137 Application/Control Number: 18/748,173 Page 22 Art Unit: 2137 Application/Control Number: 18/748,173 Page 23 Art Unit: 2137 Application/Control Number: 18/748,173 Page 24 Art Unit: 2137 Application/Control Number: 18/748,173 Page 26 Art Unit: 2137 Application/Control Number: 18/748,173 Page 27 Art Unit: 2137 Application/Control Number: 18/748,173 Page 28 Art Unit: 2137 Application/Control Number: 18/748,173 Page 29 Art Unit: 2137 Application/Control Number: 18/748,173 Page 30 Art Unit: 2137 Application/Control Number: 18/748,173 Page 31 Art Unit: 2137 Application/Control Number: 18/748,173 Page 32 Art Unit: 2137
Prosecution Insights