DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
In response to the filing of this application, the status of the claims is as follows:
Claims 1-11 are pending.
Claims 1-11 are examined on the merits below.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in China on 03/05/2024, as indicated in the Application Data Sheet (ADS). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. It is noted that there is no filed translation of the certified foreign priority document at this time. Should Applicant wish to overcome the effective date of an intervening prior art reference in the future, Applicant will need to file an English translation of the certified foreign priority, along with a statement that the translation of the certified copy is accurate. (See MPEP 215 & 216.)
Specification
The disclosure is objected to because of the following informalities:
Drawings:
Page 13, line 3 “…channel layers 130” should read “…channel layer 130…”
Page 13, line 10 “…layer 130 obviously cause…” should read “…layer 130 cause…”
Page 15, line 14 “At S1000, the substrate…”, here S1000 is not properly defined. Similarly, S1100 (line 15), S1200 (line18), S1300 (line 21), S1400 (line 24), as well as S1500, S1600, S1700, S2000, S2100, S2200, S2300, S2400, S2500, S3000, S3100, S3200, S3300, S3400, S3500, S3600, S4100, S4200 in other pages lacks clarity on how they are numbered/labelled.
Claim Objections
Claim 8 is objected to because of the following informalities: “aluminum nitride” is recited a 2nd time in line 4, and is thus duplicative. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 5-6, 8 are rejected under 35 U.S.C. 103 as being unpatentable over Barlage et al. (US 20240055529 A1, referred to hereinafter as Barlage) in view of Cao et al. (US 20180097081 A1, referred to hereinafter as Cao).
Regarding Claim 1, Barlage teaches a P-channel device ([0068], Fig. 2a, TFT 200 is a P-channel device), comprising:
a gate dielectric layer ([0070], Fig. 2a, dielectric layer 214 is a gate dielectric layer),
a first source ([0069], Fig. 2a, source 206 is a first source),
a first drain ([0069], Fig. 2a, drain 210 is a first drain), and
a first gate ([0069], Fig. 2a, gate 202 is a first gate);
wherein the P-channel device 200 is sequentially provided with following layers from bottom to top (the phrase “sequentially provided with following layers from bottom to top” is a process limitation that does not structurally limit order placement of the layers in the device structure as claimed):
a first N-type material layer ([0071], Fig. 2a, N-type semiconductor layer 216 is a first N-type material layer), and a P-type channel layer ([0072], Fig. 2a, source-channel interfacial member 250 is a P-type channel layer) arranged on the first N-type material layer 216 ([0072], Fig. 2a, P-type channel layer 250 is arranged on the first N-type material layer 216), the P-type channel layer 250 being provided with a groove (Fig. 2a, region between first source 206 and first drain 210 is a groove, hereinafter, groove 206/210) and the first source 206 ([0069], Fig. 2a, P-type channel layer 250 is provided with a groove 206/210 and the first source 206), the gate dielectric layer 214 being located above the groove (groove 206/210), and the first gate 202 being arranged on the gate dielectric layer 214 (Fig. 2a).
Barlage does not explicitly teach the following limitations in combination with the rest of the claim;
a second source,
the second source being arranged on the first N-type material layer;
a second N-type material layer located on the P-type channel layer,
the first drain being arranged on the second N-type material layer.
However, Cao teaches a P-channel device ([0020], Fig. 7, a semiconductor channel) comprising:
the second source (Cao, [0056], Fig. 7, 321, a second source hereinafter)
being arranged on the first N-type material layer (Cao, [0056], FIG. 7, 308 is a N-layer. 321 is arranged over 308 in Fig. 7.)
a second N-type material layer (Cao, [0053], FIG. 7, 304 is a n-type GaN and so is 302, 304/302 a second N-type material layer hereinafter)
located on the P-type channel layer (Cao, [0053], FIG. 7, 306 is a P-type and 304/302 is located on 306; a P-type channel layer hereinafter),
the first drain (Cao, [0056], Fig. 7, 326, a first drain hereinafter)
being arranged on the second N-type material layer (Cao, FIG. 7, 326 is arranged on 304/302).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Barlage as modified by Cao above such that the newly formed material now has a second source being arranged on first N-type material layer, and a drain arranged on second N-type material which is located on P-type channel layer. The materials such as first N-type material layer, P-channel layer etc. that were taught by Barlage are also taught by Cao, which has an additional teaching for a second N-type material layer. As such, we use the combination of such teachings from different prior arts which would now teach the disclosed invention. The motivation of the teachings of Cao is that such arrangement creates a uniform doping profile, and the N-P-N arrangement of the embodiment. This layered arrangement of source, drain and gate with a source channel at the interface helps scale a lower dimension of the Thin Film Transistor (TFT) while with the gate dielectric layer, its tuning with appropriate doping improves the performance of the channel, which also improves the threshold voltage control capability and hence the performance of the device (Cao [0003],[0006]).
Regarding claim 5, Barlage as modified by Cao above, as discussed in claim 1, further teaches the following:
wherein a base layer is provided below the first N-type material layer (Barlage, Fig. 2a, 220 is a base layer below the first N-type material layer 216),
and the base layer comprises at least one of a substrate, a stress buffer layer, a channel layer, a barrier layer, or a P-type material layer (Barlage, [0070], Fig. 2a, base layer 220 comprises a substrate).
Regarding claim 6, Barlage as modified by Cao above, as discussed in claim 5, further teaches the following:
wherein a main material of the base layer comprises, but is not limited to, silicon (Barlage, [0084], Fig. 2a, 220 consist of silicon).
Regarding claim 8, Barlage as modified by Cao above, as discussed in claim 1, further teaches the following:
wherein a main material of the gate dielectric layer comprises silicon nitride (Barlage, [0081], Fig. 2a, 214 consist of silicon nitride).
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Barlage in view of Cao, further in view of Kim et al. (US 20190296131 A1, referred to hereinafter as Kim).
Regarding claim 2, Barlage as modified by Cao above, teaches a P-channel device as discussed in claim 1, however, does not teach the following:
wherein each of the first N-type material layer, the P-type channel layer and the second N-type material layer has a multi-layer structure;
and different layers of the first N-type material layer, the P-type channel layer and the second N-type material layer are composed of different main materials
and doping elements,
and different layers of the first N-type material layer, the P-type channel layer and the second N-type material layer have different doping concentrations.
However, Kim teaches a device ([0180], Fig. 13, 1300);
wherein each of the first N-type material layer (Fig. 13, 1301/1302/1303), the P-type channel layer (Fig. 13, 1304/1306) and the second N-type material layer (Fig. 13, 1307/1308) has a multi-layer structure (Table 1, [0226], and Fig. 13);
and different layers of the first N-type material layer, the P-type channel layer and the second N-type material layer are composed of different main materials (Table 1; [0226])
and doping elements (Table 1; [0229], Fig. 13),
and different layers of the first N-type material layer, the P-type channel layer and the second N-type material layer have different doping concentrations (Table 1 and [0229], [0230], Fig. 13).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Barlage as modified by Cao and further modified by Kim above such that the newly formed P-type channel device for the teaching purpose of present invention now has each of the first N-type material layer, the P-type channel layer and the second N-type material layer as multi layered, where the different layers are composed of different main materials, doping elements and their concentrations. The combination of the teachings of Kim is important because such teaching in a P-channel device as taught by Barlage and Cao in claim 1 would allow the operation of device under low voltage, as well as tune the carrier concentration within the layers (Kim, [0137], [0143])
Regarding claim 3, Barlage as modified by Cao and Kim above, as discussed in claim 2, further teaches the following:
wherein a doping concentration of the first N-type material layer ranges from 0 to 1022 cm-3 (Kim, Table 1, Fig. 13, 1301/1302/1303),
a doping concentration of the P-type channel layer ranges from 1012 to 1022 cm-3 (Kim, [0228], Fig. 13, 1304/1306),
and a doping concentration of the second N-type material layer ranges from 1012 to 1022 cm-3 (Kim, Table 1, Fig. 13, 1307/1308).
Regarding claim 4, Barlage as modified by Cao and Kim above, as discussed in claim 2, further teaches the following:
wherein the main materials of the first N-type material layer (Cao, Fig. 7, 308), the P-type channel layer (Cao, Fig. 7, 306) and the second N-type material layer (Cao, Fig. 304) comprise at least one of gallium nitride (Cao, [0053], [0056]);
and the doping elements of the first N-type material layer and second N-type material layer comprise at least one of silicon (Kim, [0229]),
and the doping elements of the P-type channel layer comprise at least one of magnesium (Kim, [0229])
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Barlage in view of Cao, further in view of Hua et al. (CN 115020469 A, referred to hereinafter as Hua). For Hua, the English translation is used for the citation purpose
Regarding claim 9, Barlage as modified by Cao above, as discussed in claim 1, teaches a P-channel device ([0068], Fig. 2a, TFT 200 is a P-channel device), however does not explicitly teach the following:
An integrated circuit, comprising the P-channel device of claim 1.
However, Hua teaches an integrated circuit comprising a P-channel device ([n0016], Fig. 4)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Barlage as modified by Cao and further modified by Hua above such that the P-channel device is a component of an integrated circuit. This modification is essential as the presence of integrated circuit with a P-channel device reduces the cost as well as complexity of driving the device (Hua, [n0002]).
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Barlage in view of Cao and Hua as discussed above, and further in view of Xu et al. (CN 114937983 A, referred to hereinafter as Xu). For Xu, the English translation is used for the citation purpose.
Regarding claim 10, Barlage as modified by Cao and Hua above, as discussed in claim 9, teaches an integrated circuit, but does not explicitly teach the following:
wherein the integrated circuit comprises an N-channel device
the integrated circuit comprises a base layer,
the base layer is located below a first N-type material layer,
the N-channel device is provided with a second drain,
and a second gate,
wherein the second drain and the second gate are all in contact with the base layer.
However, Hua teaches an integrated circuit comprising a P-channel device ([n0016], Fig. 4) in which:
wherein the integrated circuit comprises an N-channel device (Hua, [n0082], Fig. 4)
the integrated circuit comprises a base layer (Hua, [n0082], Fig. 4, substrate 110 is a base layer)
the base layer is located below a first N-type material layer (Hua, [n0027], Fig. 4, base layer 110 is located below first N-type material layer 220);
the N-channel device is provided with a second drain (Hua, [n0027], Fig. 4, 250), and a second gate (Hua, [n0027], Fig. 4, 230); and
wherein the second drain and the second gate are all in contact with the base layer (Hua, [n0018], Fig. 4).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Barlage as modified by Cao, and further modified by Hua to include an integrated circuit comprising a base layer below the first N-type material layer and the formed N-channel device provided with a second drain and second gate, all of which are in contact with the base layer. This modification is essential to reduce the cost as well as complexity of driving, and improve the performance of the device, (Hua, [n0002]).
Barlage as modified by Cao and further as modified by Hua as above does not teach the following:
the N-channel device is provided with a third source
wherein the third source is in contact with the base layer.
However, Xu teaches a N-channel device ([n0026], Fig. 1, 102), with a third source ([n0454], Fig. 1, ESD 120 has a third source) and base layer ([n0030], p-substrate is a base layer)
wherein the third source is in contact with the base layer ([n0434], third source is fabricated in a substrate).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Barlage as modified by Cao, and further modified by Hua, and further modified by Xu with a N-channel device with a third source in contact with the base layer. This helps scaling down the size of circuit which would then consume less power offering speed and more functionality during its operation (Xu, [0002]).
Regarding claim 11 Barlage as modified by Cao, Hua and Xu above, as discussed in claim 10, further teaches the following:
wherein the base layer comprises a channel layer (Hua, [n0027], Fig. 4, 113 is a channel layer) and a barrier layer (Hua, [n0027], Fig. 4, 114 is a barrier layer);
and a two-dimensional electron gas is provided between the channel layer and the barrier layer (Hua, [n0027], Fig. 4, 115 is a channel layer two-dimensional electron gas).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Barlage in view of Cao, as discussed above, and further in view of Haruyama et al. (CN 117878058 A, referred to hereinafter as Haruyama). For Haruyama, the English translation is used for the citation purpose.
Regarding claim 7, Barlage as modified by Cao above, teaches the P-channel device as discussed in claim 1, further teaches the following:
wherein the P-type channel layer is provided with a first connecting electrode (Barlage, Fig. 2a, source electrode 208 is a first connecting electrode)
a second connecting electrode (Barlage, Fig. 2a, drain electrode 212 is a second connecting electrode),
Barlage as modified by Cao above does not teach the following:
a wire
and wherein the first connecting electrode and the second connecting electrode are connected through the wire.
However, Haruyama teaches a P-channel device ([n0030], Fig. 13), that has
a wire ([n0036], Fig. 13, 31), the first connecting electrode ([n0036], Fig 13, 42), the second connecting electrode ([n0036], Fig 13, 43),
and wherein the first connecting electrode ([n0036], Fig 13, 42) and the second connecting electrode ([n0036], Fig 13, 43) are connected through the wire ([n0036], Fig. 13, 42 and 43 are connected by a wire 31).
Therefore, it would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to modify the teachings of Barlage as modified by Cao and further modified by Haruyama to have a wire to connect the first and second electrodes. This connection helps prevent the short circuit at the load and immediate damage to the system (Haruyama, [n0001], [n0003]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRABIN BARAL whose telephone number is (571)270-5330. The examiner can normally be reached Mo -Fr, 9:00 AM-5:00 PM US Eastern Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PRABIN BARAL/Examiner, Art Unit 2812 /DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
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