DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-9, 11-16 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Schramm et al. [US 2020/0045843], in view of Tran et al. [US 2015/0318630].
Regarding claim 1, Schramm et al., disclose a computing device card system (100, figures 1-8), comprising:
a primary circuit board (151, figures 1A-1B and 2A-2B) that includes a primary circuit board top surface (a top surface of the primary circuit board, where a component 112 is mounted thereon, figures 1A-1B and 2A-2B), a primary circuit board bottom surface (an opposite surface of the top surface of the primary circuit board 151, figures 1A-1B and 2A-2B) that is located opposite the primary circuit board from the primary circuit board top surface, and a primary circuit board edge (a bottom edge of the primary circuit board 151, figures 1A-1B and 2A-2B) that extends between the primary circuit board top surface and the primary circuit board bottom surface and that defines a primary circuit board edge plane (a bottom edge surface of the primary circuit board 151, figures 1A-1B and 2A-2B) that is perpendicular to the primary circuit board top surface and the primary circuit board bottom surface;
a secondary circuit board (152, figures 1A-1B and 2A-2B) that is connected to the primary circuit board bottom surface and that includes a secondary circuit board top surface (a top surface of the secondary circuit board 152 where a connector 155 is mounted thereon, figures 1A-1B and 2A-2B), a secondary circuit board bottom surface (an opposite the top surface of the secondary circuit board 152, figures 1A-1B and 2A-2B) that is located opposite the secondary circuit board from the secondary circuit board top surface, a secondary circuit board edge (a bottom edge of the second circuit board 152, figures 1A-1B and 2A-2B) that extends between the secondary circuit board top surface and the secondary circuit board bottom surface and that defines a secondary circuit board edge plane (an edge plane is connected between the top and the bottom surfaces of the second circuit board 152, figures 1A-1B and 2A-2B) that is perpendicular to the secondary circuit board top surface and the secondary circuit board bottom surface, and a plurality of exposed conductive connector contact elements (153, figures 1A-1B and 2A-2B) formed directly on the secondary circuit board top surface and the secondary circuit board bottom surface adjacent the secondary circuit board edge to provide a plurality of computing device connectors (figures 1A-1B and 2A-2B), wherein the plurality of exposed conductive connector contact elements are configured to electrically engage a card connector (a plurality of sockets is disposed on a mainboard, figure 6) when portions of the secondary circuit board that provide the plurality of computing device connectors are each received in a card connector slot (figure 6) defined by that card connector, wherein the secondary circuit board extends from the primary circuit board edge and through the primary circuit board edge plane such that the secondary circuit board edge plane is spaced apart from the primary circuit board edge plane (figures 1A-1B and 2A);
a bottom surface component envelope that is defined adjacent the primary circuitboard bottom surface and that is based on the plurality of computing device connectorsincluded on the secondary circuit board edge (figures 1A-1B and 2A); and
at least one bottom surface component that extends from the primary circuit boardbottom surface and that is located within the bottom surface component envelope (113/154, figures 1A-1B and 2A).
Schramm et al., disclose the claimed invention except for wherein the primary circuit board has a primary circuit board thickness between the primary circuit board top surface and the primary circuit board bottom surface that is greater than a multi-connector edge thickness of the multi-connector edge between the second circuit board top surface and the secondary circuit board bottom surface.
Tran et al., disclose a printed circuit board assembly (figure 7) comprising a first printed circuit board (536, figure 7) being coupled to a second printed circuit board (526, figure 7), wherein the second printed circuit board comprise a connector edge (531, figure 7), and wherein a thickness of the first printed circuit board (536, figure 7) that is greater than a connector edge thickness of the second printed circuit board (526, figure 7, paragraph 0027).
It would have been to one of ordinary skill in the art at the time the invention was made to set a thickness of the primary circuit board that is greater than a multi-connector edge thickness of a second printed circuit board in a computing device card system of Schramm et al., as suggested by Tran et al., in order to reduce the total thickness of a multi-board (first and second PCB) computing device card system.
Regarding claim 2, Schramm et al., in view of Tran et al., disclose wherein the plurality of computing device connectors are Pluggable Multipurpose Module (PMM) connectors (figure 6).
Regarding claim 3, Schramm et al., in view of Tran et al., disclose wherein the plurality of computing device connectors are Peripheral Component Interconnect express (PCIe) Card ElectroMechanical (CEM) connectors (100, figures 1A-1B; 2A-2B and 6, paragraph 0020).
Regarding claim 5, Schramm et al., in view of Tran et al., further disclose wherein the secondary circuit board (152, figures 1A-1B and 2A-2B) is directly connected to the primary circuit board (151, figures 1A-1B and 2A-2B).
Regarding claim 6, Schramm et al., in view of Tran et al., further disclose wherein the secondary circuit board is connected to the primary circuit board by a connector subsystem (154 & 155, figures 2B) that is mounted to at least one of the primary circuit board (154, figure 2B) and the secondary circuit board (155, figure 2B).
Regarding claim 7, Schramm et al., disclose an Information Handling System (HIS, figures 1-8), comprising:
a chassis (paragraph 0017);
a card connector (figure 6, paragraph 0017) that is housed in the chassis; and
a card (100, figures 1A-1B and 2A-2B) that is connected to the card connector, wherein the card includes:
a primary circuit board (151, figures 1A-1B and 2A-2B) that includes a primary circuit board top surface (a top surface of the primary circuit board, where a component 112 is mounted thereon, figures 1A-1B and 2A-2B), a primary circuit board bottom surface (an opposite surface of the top surface of the primary circuit board 151, figures 1A-1B and 2A-2B) that is located opposite the primary circuit board from the primary circuit board top surface, and a primary circuit board edge (a bottom edge of the primary circuit board 151, figures 1A-1B and 2A-2B) that extends between the primary circuit board top surface and the primary circuit board bottom surface and that defines a primary circuit board edge plane (a bottom edge surface of the primary circuit board 151, figures 1A-1B and 2A-2B) that is perpendicular to the primary circuit board top surface and the primary circuit board bottom surface;
a secondary circuit board (152, figures 1A-1B and 2A-2B) that is connected to the primary circuit board bottom surface and that includes a secondary circuit board top surface (a top surface of the secondary circuit board 152 where a connector 155 is mounted thereon, figures 1A-1B and 2A-2B), a secondary circuit board bottom surface (an opposite the top surface of the secondary circuit board 152, figures 1A-1B and 2A-2B) that is located opposite the secondary circuit board from the secondary circuit board top surface, a secondary circuit board edge (a bottom edge of the second circuit board 152, figures 1A-1B and 2A-2B) that extends between the secondary circuit board top surface and the secondary circuit board bottom surface and that defines a secondary circuit board edge plane (an edge plane is connected between the top and the bottom surfaces of the second circuit board 152, figures 1A-1B and 2A-2B) that is perpendicular to the secondary circuit board top surface and the secondary circuit board bottom surface, and a plurality of exposed conductive connector contact elements (153, figures 1A-1B and 2A-2B) formed directly on the secondary circuit board top surface and the secondary circuit board bottom surface adjacent the secondary circuit board edge to provide a plurality of computing device connectors (figures 1A-1B and 2A-2B), wherein the plurality of exposed conductive connector contact elements are configured to electrically engage a card connector (a plurality of sockets is disposed on a mainboard, figure 6) when portions of the secondary circuit board that provide the plurality of computing device connectors are each received in a card connector slot (figure 6) defined by that card connector, wherein the secondary circuit board extends from the primary circuit board edge and through the primary circuit board edge plane such that the secondary circuit board edge plane is spaced apart from the primary circuit board edge plane (figures 1A-1B and 2A);
a bottom surface component envelope that is defined adjacent the primary circuitboard bottom surface and that is based on the plurality of computing device connectorsincluded on the secondary circuit board edge (figures 1A-1B and 2A); and
at least one bottom surface component that extends from the primary circuit boardbottom surface and that is located within the bottom surface component envelope (113/154, figures 1A-1B and 2A).
Schramm et al., disclose the claimed invention except for wherein the primary circuit board has a primary circuit board thickness between the primary circuit board top surface and the primary circuit board bottom surface that is greater than a multi-connector edge thickness of the multi-connector edge between the second circuit board top surface and the secondary circuit board bottom surface.
Tran et al., disclose a printed circuit board assembly (figure 7) comprising a first printed circuit board (536, figure 7) being coupled to a second printed circuit board (526, figure 7), wherein the second printed circuit board comprise a connector edge (531, figure 7), and wherein a thickness of the first printed circuit board (536, figure 7) that is greater than a connector edge thickness of the second printed circuit board (526, figure 7, paragraph 0027).
It would have been to one of ordinary skill in the art at the time the invention was made to set a thickness of the primary circuit board that is greater than a multi-connector edge thickness of a second printed circuit board in a computing device card system of Schramm et al., as suggested by Tran et al., in order to reduce the total thickness of a multi-board (first and second PCB) computing device card system.
Regarding claim 8 Schramm et al., in view of Tran et al., disclose wherein the plurality of computing device connectors are Pluggable Multipurpose Module (PMM) connectors (figure 6).
Regarding claim 9, Schramm et al., in view of Tran et al., disclose wherein the plurality of computing device connectors are Peripheral Component Interconnect express (PCIe) Card ElectroMechanical (CEM) connectors (100, figures 1A-1B; 2A-2B and 6, paragraph 0020).
Regarding claim 11, Schramm et al., in view of Tran et al., further disclose wherein the secondary circuit board (152, figures 1A-1B and 2A-2B) is directly connected to the primary circuit board (151, figures 1A-1B and 2A-2B).
Regarding claim 12, Schramm et al., in view of Tran et al., further disclose wherein the secondary circuit board is connected to the primary circuit board by a connector subsystem (154 & 155, figures 2B) that is mounted to at least one of the primary circuit board (154, figure 2B) and the secondary circuit board (155, figure 2B).
Regarding claim 13, Schramm et al., in view of Tran et al., further disclose a top surface component envelope (115, figure 1A) that is located adjacent the primary circuit board top surface and that is based on the plurality of computing device connectors included on the secondary circuit board edge; and at least one top surface component (113, figure 1A) that extends from the primary circuit board top surface and that is located within the top surface component envelope.
Regarding claim 14, Schramm et al., disclose a method for providing a card component envelope for a card system (100, figures 1A-1B and 2A-2B) used with a computing device (figures 1-8), comprising:
providing a primary circuit board (151, figures 1A-1B and 2A-2B) that includes a primary circuit board top surface (a top surface of the primary circuit board, where a component 112 is mounted thereon, figures 1A-1B and 2A-2B), a primary circuit board bottom surface (an opposite surface of the top surface of the primary circuit board 151, figures 1A-1B and 2A-2B) that is located opposite the primary circuit board from the primary circuit board top surface, and a primary circuit board edge (a bottom edge of the primary circuit board 151, figures 1A-1B and 2A-2B) that extends between the primary circuit board top surface and the primary circuit board bottom surface and that defines a primary circuit board edge plane (a bottom edge surface of the primary circuit board 151, figures 1A-1B and 2A-2B) that is perpendicular to the primary circuit board top surface and the primary circuit board bottom surface;
providing a secondary circuit board (152, figures 1A-1B and 2A-2B) that includes a secondary circuit board top surface (a top surface of the secondary circuit board 152 where a connector 155 is mounted thereon, figures 1A-1B and 2A-2B), a secondary circuit board bottom surface (an opposite the top surface of the secondary circuit board 152, figures 1A-1B and 2A-2B) that is located opposite the secondary circuit board from the secondary circuit board top surface, a secondary circuit board edge (a bottom edge of the second circuit board 152, figures 1A-1B and 2A-2B) that extends between the secondary circuit board top surface and the secondary circuit board bottom surface and that defines a secondary circuit board edge plane (an edge plane is connected between the top and the bottom surfaces of the second circuit board 152, figures 1A-1B and 2A-2B) that is perpendicular to the secondary circuit board top surface and the secondary circuit board bottom surface, and a plurality of exposed conductive connector contact elements (153, figures 1A-1B and 2A-2B) formed directly on the secondary circuit board top surface and the secondary circuit board bottom surface adjacent the secondary circuit board edge to provide a plurality of computing device connectors (figures 1A-1B and 2A-2B), wherein the plurality of exposed conductive connector contact elements are configured to electrically engage a card connector (a plurality of sockets is disposed on a mainboard, figure 6) when portions of the secondary circuit board that provide the plurality of computing device connectors are each received in a card connector slot (figure 6) defined by that card connector;
connecting the secondary circuit board to the primary circuit board bottom surfacesuch that the secondary circuit board extends from the primary circuit board edge andthrough the primary circuit board edge plane and the secondary circuit board edge plane is spaced apart from the primary circuit board edge plane (figures 1A-1B and 2A); and
providing, on the primary circuit board, at least one bottom surface component that extends from the primary circuit board bottom surface and that is located within the bottom surface component envelope that is defined adjacent the primary circuit board bottomsurface and that is based on the plurality of computing device connectors included on thesecondary circuit board edge (113/154, figures 1A-1B and 2A).
Schramm et al., disclose the claimed invention except for wherein the primary circuit board has a primary circuit board thickness between the primary circuit board top surface and the primary circuit board bottom surface that is greater than a multi-connector edge thickness of the multi-connector edge between the second circuit board top surface and the secondary circuit board bottom surface.
Tran et al., disclose a printed circuit board assembly (figure 7) comprising a first printed circuit board (536, figure 7) being coupled to a second printed circuit board (526, figure 7), wherein the second printed circuit board comprise a connector edge (531, figure 7), and wherein a thickness of the first printed circuit board (536, figure 7) that is greater than a connector edge thickness of the second printed circuit board (526, figure 7, paragraph 0027).
It would have been to one of ordinary skill in the art at the time the invention was made to set a thickness of the primary circuit board that is greater than a multi-connector edge thickness of a second printed circuit board in a computing device card system of Schramm et al., as suggested by Tran et al., in order to reduce the total thickness of a multi-board (first and second PCB) computing device card system.
Regarding claim 15, Schramm et al., in view of Tran et al., disclose wherein the plurality of computing device connectors are Pluggable Multipurpose Module (PMM) connectors (figure 6).
Regarding claim 16, Schramm et al., in view of Tran et al., disclose wherein the plurality of computing device connectors are Peripheral Component Interconnect express (PCIe) Card ElectroMechanical (CEM) connectors (100, figures 1A-1B; 2A-2B and 6, paragraph 0020).
Regarding claim 18, Schramm et al., in view of Tran et al., further disclose wherein the secondary circuit board (152, figures 1A-1B and 2A-2B) is directly connected to the primary circuit board (151, figures 1A-1B and 2A-2B).
Regarding claim 19, Schramm et al., in view of Tran et al., further disclose wherein the secondary circuit board is connected to the primary circuit board by a connector subsystem (154 & 155, figures 2B) that is mounted to at least one of the primary circuit board (154, figure 2B) and the secondary circuit board (155, figure 2B).
Regarding claim 20, Schramm et al., in view of Tran et al., further disclose on the primary circuit board (151, figures 1A-1B and 2A-2B), at least one top surface component (113/115, figure 1A) that extends from the primary circuit board top surface and is located within a top surface component envelope that is defined adjacent the primary circuit board top surface and that is based on the plurality of computing device connectors included on the secondary circuit board edge.
Claims 4, 10 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Schramm et al., in view of Tran et al., as applied to claim 4, 7 and 14 above, and further in view of Vergis et al. [US 2023/0005882].
Regarding claims 4, 10 and 17, Schramm et al., in view of Tran et al., disclose the claimed invention except for wherein the least one bottom surface component includes at least one Compression Attached Memory Module (CAMM) component.
Vergis et al., disclose a card system (figures 1-7) comprising a primary circuit board (202, figure 2B) coupled to a secondary circuit board (216, figure 2B), wherein at least one bottom surface component (213, figure 2B; paragraph 0034) is a Compression Attached Memory Module (CAMM) component mounted on the card system.
It would have been to one of ordinary skill in the art at the time the invention was made to use at least one compression attached memory module component on a bottom surface component of a computing card system of Schramm et al., in view of Tran et al., as suggested by Vergis et al., in order to provide high-capacity, high performance, and power-efficient memory in a compact shape of a computing device card system.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Shaffer et al.[US 5,200,917] disclose stacked printed circuit board device;
Uezono [US 2004/0184244] discloses circuit board assembling structure; and
Yamada et al. [US 2005/0159024] disclose relay arrangement structure.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Hung S. Bui whose telephone number is (571)272-2102. The examiner can normally be reached on M-F: 8am-6pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Allen L. Parker can be reached on (303) 297-4722. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov.
Visit https://www.uspto.gov/patents/apply/patent-center.
for more information about Patent Center and
https://www.uspto.gov/patents/docx for information about filing in DOCX format.
For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HUNG S. BUI/
Primary Examiner
Art Unit 2841
/HUNG S. BUI/Primary Patent Examiner, 2841/2800
