DETAILED ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 5-8, 11-15 and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Brodsky et al. [US 9,325,086].
Regarding claim 1, Brodsky et al., disclose a computing device card system (figures 1-7), comprising:
a primary circuit board (62, figures 4-6) that includes a primary circuit board top surface (a top surface of the board 62, figure 6), a primary circuit board bottom surface (a bottom surface of the board 62, figure 6) that is located opposite the primary circuit board from the primary circuit board top surface, and a primary circuit board edge (a left side thickness of the board 62, figure 6) that extends between the primary circuit board top surface and the primary circuit board bottom surface and that defines a primary circuit board edge plane (see attached figure 6) that is perpendicular to the primary circuit board top surface and the primary circuit board bottom surface;
a secondary circuit board (52, figure 6) that is connected to the primary circuit board bottom surface and that includes a secondary circuit board top surface (a top surface of the board 52, figure 6), a secondary circuit board bottom surface (a bottom surface of the board 52, figure 6) that is located opposite the secondary circuit board from the secondary circuit board top surface, and a secondary circuit board edge (a left side thickness of the board 52, figure 6) that extends between the secondary circuit board top surface and the secondary circuit board bottom surface, that defines a secondary circuit board edge plane (see attached figure 6) that is perpendicular to the secondary circuit board top surface and the secondary circuit board bottom surface, and that includes a plurality of computing device connectors (54, figures 4-6), wherein the secondary circuit board extends from the primary circuit board edge and through the primary circuit board edge plane such that the secondary circuit board edge plane is spaced apart from the primary circuit board edge plane (see attached figure 6);
a bottom surface component envelope that is defined adjacent the primary circuit board bottom surface and that is based on the plurality of computing device connectors (64 & 58, figure 6) included on the secondary circuit board edge; and
at least one bottom surface component (64, figure 6) that extends from the primary circuit board bottom surface and that is located within the bottom surface component envelope.
Regarding claim 2, Brodsky et al., disclose wherein the plurality of computing device connectors are Pluggable Multipurpose Module (PMM) connectors (figures 4-6).
PNG
media_image1.png
589
885
media_image1.png
Greyscale
Regarding claim 5, Brodsky et al., disclose wherein the secondary circuit board (52, figure 6) is directly connected to the primary circuit board (62, figure 6).
Regarding claim 6, Brodsky et al., disclose wherein the secondary circuit board is connected to the primary circuit board by a connector subsystem (58 & 64, figure 6) that is mounted to at least one of the primary circuit board (64, figure 6) and the secondary circuit board (58, figure 6).
Regarding claim 7, Brodsky et al., disclose an Information Handling System (HIS, figures 1-7), comprising:
a chassis (82, figure 7);
a card connector (54a & 54b, 58a and 58b, figure 7) that is housed in the chassis; and
a card (figures 4-7) that is connected to the card connector, wherein the card includes:
a primary circuit board (62, figures 4-6) that includes a primary circuit board top surface (a top surface of the board 62, figure 6), a primary circuit board bottom surface (a bottom surface of the board 62, figure 6) that is located opposite the primary circuit board from the primary circuit board top surface, and a primary circuit board edge ((a left side thickness of the board 62, figure 6) that extends between the primary circuit board top surface and the primary circuit board bottom surface and that defines a primary circuit board edge plane (see attached above figure 6) that is perpendicular to the primary circuit board top surface and the primary circuit board bottom surface;
a secondary circuit board (52, figure 6) that is connected to the primary circuit board bottom surface and that includes a secondary circuit board top surface (a top surface of the board 52, figure 6), a secondary circuit board bottom surface (a bottom surface of the board 52, figure 6) that is located opposite the secondary circuit board from the secondary circuit board top surface, and a secondary circuit board edge (a left side thickness of the board 52, figure 6) that extends between the secondary circuit board top surface and the secondary circuit board bottom surface, that defines a secondary circuit board edge plane (see attached figure 6) that is perpendicular to the secondary circuit board top surface and the secondary circuit board bottom surface, and that includes a plurality of computing device connectors (54, figures 4-6), wherein the secondary circuit board extends from the primary circuit board edge and through the primary circuit board edge plane such that the secondary circuit board edge plane is spaced apart from the primary circuit board edge plane (see attached figure 6);
a bottom surface component envelope that is defined adjacent the primary circuit board bottom surface and that is based on the plurality of computing device connectors (64 & 58, figure 6) included on the secondary circuit board edge; and
at least one bottom surface component (64, figure 6) that extends from the primary circuit board bottom surface and that is located within the bottom surface component envelope.
Regarding claim 8, Brodsky et al., disclose wherein the card connector and the plurality of computing device connectors are Pluggable Multipurpose Module (PMM) connectors (figures 4-6).
Regarding claim 11, Brodsky et al., disclose wherein the secondary circuit board (52, figure 6) is directly connected to the primary circuit board (62, figure 6).
Regarding claim 12, Brodsky et al., disclose wherein the secondary circuit board is connected to the primary circuit board by a connector subsystem (58 & 64, figure 6) that is mounted to at least one of the primary circuit board (64, figure 6) and the secondary circuit board (58, figure 6).
Regarding claim 13, Brodsky et al., further disclose a top surface component envelope (figures 6-7) that is located adjacent the primary circuit board top surface and that is based on the plurality of computing device connectors (54, figure 6) included on the secondary circuit board edge; and at least one top surface component (66, figure 6) that extends from the primary circuit board top surface and that is located within the top surface component envelope.
Regarding claim 14, Brodsky et al., disclose a method for providing a card component envelope for a card system used with a computing device (figures 1-7), comprising:
providing a primary circuit board (62, figures 4-6) that includes a primary circuit board top surface (a top surface of the board 62, figure 6), a primary circuit board bottom surface (a bottom surface of the board 62, figure 6) that is located opposite the primary circuit board from the primary circuit board top surface, and a primary circuit board edge (a left side thickness of the board 62, figure 6) that extends between the primary circuit board top surface and the primary circuit board bottom surface and that defines a primary circuit board edge plane (see attached figure 6) that is perpendicular to the primary circuit board top surface and the primary circuit board bottom surface;
providing a secondary circuit board (52, figure 6) that includes a secondary circuit board top surface (a top surface of the board 52, figure 6), a secondary circuit board bottom surface (a bottom surface of the board 52, figure 6) that is located opposite the secondary circuit board from the secondary circuit board top surface, and a secondary circuit board edge (a left side thickness of the board 52, figure 6) that extends between the secondary circuit board top surface and the secondary circuit board bottom surface, that defines a secondary circuit board edge plane (see attached above figure 6) that is perpendicular to the secondary circuit board top surface and the secondary circuit board bottom surface, and that includes a plurality of computing device connectors (54, figure 6);
connecting the secondary circuit board to the primary circuit board bottom surface such that the secondary circuit board extends from the primary circuit board edge and through the primary circuit board edge plane and the secondary circuit board edge us-plane is spaced apart from the primary circuit board edge plane (see attached above figure 6); and
providing, on the primary circuit board, at least one bottom surface component (64, figure 6) that extends from the primary circuit board bottom surface and is located within a bottom surface component envelope that is defined adjacent the primary circuit board bottom surface and that is based on the plurality of computing device connectors (64 & 58, figure 6) included on the secondary circuit board edge (figure 6).
Regarding claim 15, Brodsky et al., disclose wherein the plurality of computing device connectors are Pluggable Multipurpose Module (PMM) connectors (figures 4-6).
Regarding claim 18, Brodsky et al., further disclose directly connecting the secondary circuit board (52, figure 6) to the primary circuit board (62, figure 6).
Regarding claim 19, Brodsky et al., disclose a step of connecting, via a connector subsystem (58 & 64, figure 6) that is mounted to at least one of the primary circuit board and the secondary circuit board, the secondary circuit board (58, figure 6) to the primary circuit board (64, figure 6).
Regarding claim 20, Brodsky et al., further disclose a step of providing, on the primary circuit board, at least one top surface component (66, figure 6) that extends from the primary circuit board top surface and is located within a top surface component envelope that is defined adjacent the primary circuit board top surface and that is based on the plurality of computing device connectors included on the secondary circuit board edge.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 9 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Brodsky et al., in view Krug et al. [US 4,936,785].
Regarding claims 3, 9 and 16, Brodsky et al., disclose the claimed invention except for wherein the plurality of computing device connectors are Peripheral Component Interconnect express (PCIe), Card ElectroMechanical (CEM) connectors.
Krug et al., disclose a computing device card system (figures 1-5), comprising a primary circuit board (10, figures 1-5) and a secondary circuit board (20, figures 1-5), wherein the plurality of computing device connectors of the secondary circuit board are Peripheral Component Interconnect express (PCIe), Card ElectroMechanical (CEM) connectors (46, 47 and 48, figures 1-5).
It would have been to one of ordinary skill in the art at the time the invention was directly made to use a Peripheral Component Interconnect express and/or Card ElectroMechanical connector(s) in a computing device card system of Brodsky et al., as suggested by Krug et al., in order to provide a standardized, high-speed interface for connecting peripheral components to a card system.
Claims 4, 10 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Brodsky et al., in view of Vergis et al. [US 2023/0005882].
Regarding claims 4, 10 and 17, Brodsky et al., disclose the claimed invention except for wherein the least one bottom surface component includes at least one Compression Attached Memory Module (CAMM) component.
Vergis et al., disclose a card assembly (figures 1-7) comprising a primary circuit board (202, figure 2B) coupled to a secondary circuit board (216, figure 2B), wherein the least one bottom surface component includes at least one Compression Attached Memory Module (CAMM) component (213, figure 2B, paragraph 0034).
It would have been to one of ordinary skill in the art at the time the invention was made to add a specific socket to mount at least one Compression Attached Memory Module (CAMM) component, in the computing device card system of Brodsky et al., as suggested by Vergis et al., in order to provide high-capacity, high performance, and power-efficient memory in a compact shape of a computing device card system.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Tate et al. [US 2017/0345803] disclose module stacking mechanism with integrated ground.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Hung S. Bui whose telephone number is (571)272-2102. The examiner can normally be reached on M-F: 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Allen L. Parker can be reached on (303) 297-4722. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov.
Visit https://www.uspto.gov/patents/apply/patent-center.
for more information about Patent Center and
https://www.uspto.gov/patents/docx for information about filing in DOCX format.
For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HUNG S. BUI/
Primary Examiner
Art Unit 2841
/Hung S. Bui/
Primary Examiner, Art Unit 2841