DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending for examination.
Double patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-17 of U.S. Patent No. 10,908,946 B2.
Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application are obvious over the claims of U. S. Patent No. 10,908,946 B2. See MPEP 804. The side-by-side comparison below of claim 1 of the instant application and claim 1 of U. S. Patent No. 10,908,946 B2 clearly shows limitation by limitation matching between the two conflicting claims.
Instant Application
Patent 10,908,946 B2
1.A system comprising:
a plurality of data processing nodes of a first type;
a data processing node of a second type; and
a hardware thread scheduler comprising:
a plurality of hardware task schedulers respectively coupled, and corresponding, to a set of the plurality of data processing nodes of the first type, each hardware task scheduler of the plurality of hardware task schedulers having at least one of a producer socket and a consumer socket;
a task scheduler configured to be coupled to the data processing node of the second type and having at least one of a producer socket and a consumer socket; and
a hardware scheduler crossbar configured to be coupled to each of the plurality of hardware task schedulers and the task scheduler via at least one of a pending signal indicating that consumable data is available and a decrement signal indicating that a block of produced data has been consumed;
wherein the hardware thread scheduler is configured to:
execute a first thread of tasks on select data processing nodes of the first type, including couple corresponding hardware task schedulers, via pending and decrement signals, in a first data processing order;
execute a second thread of tasks on at least one of the plurality of data processing nodes of the first type and the data processing node of the second type, including couple a corresponding at least one of the plurality of hardware task schedulers and the task scheduler, via pending and decrement signals, in a second data processing order; and
communicate a signal indicating completion of at least one task of the first and second threads of tasks.
1.A device comprising:
a first data processing node;
a second data processing node; and
a hardware thread scheduler coupled to the first data processing node and the second data processing node, the hardware thread scheduler comprising:
a first internal hardware task scheduler configured to schedule an execution of a first task on the first data processing node;
a second internal hardware task scheduler configured to schedule an execution of a second task on the second data processing node;
a proxy hardware task scheduler adapted to be coupled to an external data processing node, wherein the external data processing node is external to the device and the proxy hardware task scheduler is configured to schedule an execution of a third task on the external data processing node, wherein the first internal hardware task scheduler, the second internal hardware task scheduler, and the proxy hardware task scheduler each having respective producer socket and consumer socket for the first, second and third tasks; and
a scheduler crossbar connected to all of the respective producer socket and consumer socket;
wherein the hardware thread scheduler is configured to:
setting a respective memory buffer depth for each of the first, second, and third tasks;
determining which of the first, second, and third tasks will produce data blocks;
determining which of the first, second, and third will consume data blocks;
connect a pending signal of a producer socket from the determined one of the first, second and third tasks that will produce data blocks indicating data is pending via the scheduler crossbar to a decrement signal of a consumer socket from the determined one of the set of first, second, and third tasks that will consume data blocks, and connecting the decrement signal of the respective consumer socket from the determined one of the first, second and third tasks that will consume data blocks to the pending signal of the respective producer socket from the determined one from the first, second and third tasks that will produce data blocks, wherein the pending and decrement signals are used to indicate, respectively, availability and consumption of data blocks for the first, second and third tasks;
initiate the execution of the first task, the execution of the second task, and the execution of the third task;
determine a completion of the execution of the first task, the execution of the second task, and the execution of the third task;
communicate a signal indicating the completion of the execution of the first task, the execution of the second task, and the execution of the third task.
Although the claims at issue are not identical, they are not patentably distinct from each other because Patent ‘946’ is narrower than the instant application. The Patent ‘946’s narrower scope merely specifies that “connect a pending signal of a producer socket from the determined one of the first, second and third tasks that will produce data blocks indicating data is pending via the scheduler crossbar to a decrement signal of a consumer socket from the determined one of the set of first, second, and third tasks that will consume data blocks, and connecting the decrement signal of the respective consumer socket from the determined one of the first, second and third tasks that will consume data blocks to the pending signal of the respective producer socket from the determined one from the first, second and third tasks that will produce data blocks, wherein the pending and decrement signals are used to indicate, respectively, availability and consumption of data blocks for the first, second and third tasks” in claim 1 which has the same meaning compare to “a plurality of data processing nodes of a first type; a data processing node of a second type; and execute a first thread of tasks on select data processing nodes of the first type, including couple corresponding hardware task schedulers, via pending and decrement signals, in a first data processing order; execute a second thread of tasks on at least one of the plurality of data processing nodes of the first type and the data processing node of the second type, including couple a corresponding at least one of the plurality of hardware task schedulers and the task scheduler, via pending and decrement signals, in a second data processing order” of claim 1 of the instant application, because they are utilizing the first and second data processing node with consumer and producer socket and the pending and decrement signals for execution. And the using the second data processing node which is corresponding to the external node as indicated in the patent 946’(as second type).
In addition, the Patent ‘946’s narrower scope merely specifies that “a first internal hardware task scheduler”, “a second internal hardware task scheduler” and “a proxy hardware task scheduler adapted to be coupled to an external data processing node” which is the same thing but different words as compare to “a plurality of hardware task schedulers”, “a task scheduler configured to be coupled to the data processing node” and “a hardware scheduler crossbar configured to be coupled to each of the plurality of hardware task schedulers and the task scheduler via at least one of a pending signal” of claim 1 in the instant application.
Similar claim mappings for claims 2-15 of the instant application with the claims of 2-17 of Patent’946’ would have been obvious to a person having ordinary skill in the art but have been omitted for the sake of brevity.
Claims 1-15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,050,929 B2.
Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application are obvious over the claims of U. S. Patent No. 12,050,929 B2. See MPEP 804. The side-by-side comparison below of claim 1 of the instant application and claim 1 of U. S. Patent No. 12,050,929 B2 clearly shows limitation by limitation matching between the two conflicting claims.
Instant Application
Patent 12,050,929 B2
1.A system comprising:
a plurality of data processing nodes of a first type;
a data processing node of a second type; and
a hardware thread scheduler comprising:
a plurality of hardware task schedulers respectively coupled, and corresponding, to a set of the plurality of data processing nodes of the first type, each hardware task scheduler of the plurality of hardware task schedulers having at least one of a producer socket and a consumer socket;
a task scheduler configured to be coupled to the data processing node of the second type and having at least one of a producer socket and a consumer socket; and
a hardware scheduler crossbar configured to be coupled to each of the plurality of hardware task schedulers and the task scheduler via at least one of a pending signal indicating that consumable data is available and a decrement signal indicating that a block of produced data has been consumed;
wherein the hardware thread scheduler is configured to:
execute a first thread of tasks on select data processing nodes of the first type, including couple corresponding hardware task schedulers, via pending and decrement signals, in a first data processing order;
execute a second thread of tasks on at least one of the plurality of data processing nodes of the first type and the data processing node of the second type, including couple a corresponding at least one of the plurality of hardware task schedulers and the task scheduler, via pending and decrement signals, in a second data processing order; and
communicate a signal indicating completion of at least one task of the first and second threads of tasks.
1.A device comprising:
data processing nodes including a first data processing node associated with a first hardware accelerator, and
a second data processing node associated with a second hardware accelerator; and
a hardware thread scheduler including:
a plurality of internal hardware task schedulers, each including at least one of a producer socket and a consumer socket, each of the plurality of internal hardware task schedulers coupled to a different one of the data processing nodes; and
a hardware scheduler crossbar configured to be coupled to the producer sockets of the plurality of internal hardware task schedulers via respective pending signals and configured to be coupled to the consumer sockets of the plurality of internal hardware task schedulers via respective decrement signals, in which each pending signal indicates availability of consumable data, and each decrement signal indicates that a block of produced data has been consumed:
wherein the hardware thread scheduler is configured to:
configure a first subset of the plurality of internal hardware task schedulers to execute a first thread of tasks, including couple the first subset of the internal hardware task schedulers, via pending and decrement signals, in a first data processing order;
configure a second subset of the plurality of internal hardware task schedulers to execute a second thread of tasks at least partially overlapping execution of the first thread of tasks, including couple the second subset of the internal hardware task schedulers, via pending and decrement signals, in a second data processing order;
initiate execution of the first thread of tasks including a first task associated with the first data processing node and a second task associated with the second data processing node;
initiate execution of the second thread of tasks including a third task associated with a third data processing node of the data processing nodes and a fourth task associated with an external data processing node that is external to the first, second, and third data processing nodes;
determine a completion of the execution of the first task and the second task; and communicate a signal indicating the completion of the execution of the first task and the second task.
initiate the execution of the first task, the execution of the second task, and the execution of the third task;
determine a completion of the execution of the first task, the execution of the second task, and the execution of the third task;
communicate a signal indicating the completion of the execution of the first task, the execution of the second task, and the execution of the third task.
Although the claims at issue are not identical, they are not patentably distinct from each other because Patent ‘929 is narrower than the instant application. The Patent ‘929’s narrower scope merely specifies that “a plurality of internal hardware task schedulers, each including at least one of a producer socket and a consumer socket, each of the plurality of internal hardware task schedulers coupled to a different one of the data processing nodes; configure a first subset of the plurality of internal hardware task schedulers to execute a first thread of tasks, including couple the first subset of the internal hardware task schedulers, via pending and decrement signals, in a first data processing order; configure a second subset of the plurality of internal hardware task schedulers to execute a second thread of tasks at least partially overlapping execution of the first thread of tasks, including couple the second subset of the internal hardware task schedulers, via pending and decrement signals, in a second data processing order; initiate execution of the first thread of tasks including a first task associated with the first data processing node and a second task associated with the second data processing node; initiate execution of the second thread of tasks including a third task associated with a third data processing node of the data processing nodes and a fourth task associated with an external data processing node that is external to the first, second, and third data processing nodes;” in claim 1 which has the same meaning compare to “a plurality of data processing nodes of a first type; a data processing node of a second type; a task scheduler configured to be coupled to the data processing node of the second type and having at least one of a producer socket and a consumer socket and execute a first thread of tasks on select data processing nodes of the first type, including couple corresponding hardware task schedulers, via pending and decrement signals, in a first data processing order; execute a second thread of tasks on at least one of the plurality of data processing nodes of the first type and the data processing node of the second type, including couple a corresponding at least one of the plurality of hardware task schedulers and the task scheduler, via pending and decrement signals, in a second data processing order” of claim 1 of the instant application, because they are utilizing the first and second data processing node with consumer and producer socket and the pending and decrement signals for execution with the different hardware task schedulers.
Similar claim mappings for claims 2-15 of the instant application with the claims of 2-20 of Patent’929’ would have been obvious to a person having ordinary skill in the art but have been omitted for the sake of brevity.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) are: “a task scheduler configured to” in claim 1, “common data processing node of the first type is configured to” in claim 7, “internal data processing nodes configured to” in claim 11, and “an image capture device configured to” in claim 16.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
Claim limitations “a task scheduler configured to” in claim 1, “common data processing node of the first type is configured to” in claim 7, “internal data processing nodes configured to” in claim 11, and “an image capture device configured to” in claim 16 invokes 35 U.S.C. 112(f). The specification paragraph [0007] that discloses “a system includes an image capture device configured to receive images” and [0007] of the specification discloses “The VPAC has hardware accelerators as data processing nodes” and [0089] of the specification discloses “a hardware thread scheduler includes one or more proxy hardware task schedulers. One of ordinary skill in the art will understand embodiments without a proxy hardware task scheduler.” as performing corresponding structure. However, said “a task scheduler configured to” “common data processing node of the first type is configured to”, “internal data processing nodes configured to”, and “an image capture device configured to” without the detail about the means to accomplish the functions are not an adequate disclosure of corresponding structure (i.e., they are general purpose computer and they are not sufficient structure to be corresponding structure under 112(f). That is, the general purpose computer must be transformed into a specially programmed computer by way of an algorithm). MPEP § 2181(II)(B) specifically indicated that “For a computer-implemented 35 U.S.C. 112(f) claim limitation, the specification must disclose an algorithm for performing the claimed specific computer function, or else the claim is indefinite under 35 U.S.C. 112(b). See Net MoneyIN, Inc. v. Verisign. Inc., 545 F.3d 1359, 1367, 88 USPQ2d 1751, 1757 (Fed. Cir. 2008). See also In re Aoyama, 656 F.3d 1293, 1297, 99 USPQ2d 1936, 1939 (Fed. Cir. 2011) ("[W]hen the disclosed structure is a computer programmed to carry out an algorithm, ‘the disclosed structure is not the general purpose computer, but rather that special purpose computer programmed to perform the disclosed algorithm.’") (quoting WMS Gaming, Inc. v. Int’l Game Tech., 184 F.3d 1339, 1349, 51 USPQ2d 1385, 1391 (Fed. Cir. 1999))” and “The corresponding structure is not simply a general purpose computer by itself but the special purpose computer as programmed to perform the disclosed algorithm. Aristocrat, 521 F.3d at 1333, 86 USPQ2d at 1239. Thus, the specification must sufficiently disclose an algorithm to transform a general purpose microprocessor to the special purpose computer” Therefore, the claims (i.e., 1-20) are indefinite and is rejected under 35 U.S.C. 112(b).
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f);
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement.
The claims 1, 7, 11 and 16 contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention. As described above in 112(f) (i.e., “a task scheduler configured to” in claim 1, “common data processing node of the first type is configured to” in claim 7, “internal data processing nodes configured to” in claim 11, and “an image capture device configured to” in claim 16), the disclosure does not provide adequate structure to perform the claimed functions. The specification does not demonstrate that applicant has made an invention that achieves the claimed function because the invention is not described with sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention. See MPEP § 2181(II)(B) “When a claim containing a computer-implemented 35 U.S.C. 112(f) claim limitation is found to be indefinite under 35 U.S.C. 112(b) for failure to disclose sufficient corresponding structure (e.g., the computer and the algorithm) in the specification that performs the entire claimed function, it will also lack written description under 35 U.S.C. 112(a)”.
Claims 2-10, 12-15 and 17-20, they are depend on claims 1, 11 and 16 and do not overcome the deficiencies thereof, therefore they are rejected for the same reason as claims 1, 11 and 16 above.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
As per claims 1, 7, 11 and 16:
As described above in 112(f) (i.e., “a task scheduler configured to” in claim 1, “common data processing node of the first type is configured to” in claim 7, “internal data processing nodes configured to” in claim 11, and “an image capture device configured to” in claim 16 without the detail about the means to accomplish the functions are not an adequate disclosure of corresponding structure. The MPEP § 2181(II)(B) specifically indicated that “For a computer-implemented 35 U.S.C. 112(f) claim limitation, the specification must disclose an algorithm for performing the claimed specific computer function, or else the claim is indefinite under 35 U.S.C. 112(b). See Net MoneyIN, Inc. v. Verisign. Inc., 545 F.3d 1359, 1367, 88 USPQ2d 1751, 1757 (Fed. Cir. 2008). See also In re Aoyama, 656 F.3d 1293, 1297, 99 USPQ2d 1936, 1939 (Fed. Cir. 2011) ("[W]hen the disclosed structure is a computer programmed to carry out an algorithm, ‘the disclosed structure is not the general purpose computer, but rather that special purpose computer programmed to perform the disclosed algorithm.’") (quoting WMS Gaming, Inc. v. Int’l Game Tech., 184 F.3d 1339, 1349, 51 USPQ2d 1385, 1391 (Fed. Cir. 1999))”. Therefore, the claims (i.e., 1, 7, 11 and 16) are indefinite and is rejected under 35 U.S.C. 112(b).
As per claims 2-10, 12-15 and 17-20:
They are system and method claims that depend from rejected claims and do not resolve the deficiencies thereof and are therefore rejected for the same reasons as above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over NA (US Pub. 2014/0372810 A1) in view of Nalluri et al. (US Pub. 2014/0160138 A1) and further in view of Barner (US Pub. 2016/0139622 A1), Rupp (US Patent. 7,237,055 B1) and Verbeke et al. (US Pub. 2004/0019514 A1).
NA, Nalluri, Barner, Rupp and Verbeke were cited in the IDS filed on 06/20/2024.
As per claim 1, NA teaches the invention substantially as claimed including A system comprising (NA, Fig. 1):
a plurality of data processing nodes of a first type (NA, Fig. 1, 10 cores, Core 0 to 3; [0031] a multi-core processor 10 including a plurality of cores);
a data processing node (NA, Fig. 1, core n); and
a hardware thread scheduler comprising (NA, Fig. 1, 20 task scheduler):
a plurality of hardware task schedulers respectively coupled (NA, Fig. 1, 22a to 22c schedulers), and corresponding, to a set of the plurality of data processing nodes of the first type (NA, Fig. 1, schedulers 22a to core 0, scheduler 22b to core 1, scheduler 22c to core 3),
a task scheduler configured to be coupled to the data processing node ( NA, Fig. 1, 22d scheduler to core N); and
a hardware scheduler crossbar configured to be coupled to each of the plurality of hardware task schedulers and the task scheduler (NA, Fig. 1, 21 load balancer (as crossbar) couple to 22a to 22d schedulers);
wherein the hardware thread scheduler is configured to (NA, Fig. 1, 20 task scheduler):
execute a first thread of tasks on select data processing nodes of the first type, including couple corresponding hardware task schedulers (NA, Fig. 1, 23a, 23b respective execution queue associated with each cores with each internal hardware task schedulers; [0008] lines 1-7, managing tasks or processes (as thread/process of tasks/processes) (a scheduler, or a scheduling technique) have been applied to an operating system that runs on a multi-core processor…a multi-core based task scheduler has the advantage of assigning tasks to cores; [0032] lines 3-7,The load balancer 21 (within the task scheduler 10) determines the control of the sequence of the execution of the tasks assigned to the respective cores); [0034] lines 1-7, The respective cores perform the assigned tasks. In this case, the load balancer 21 may assign tasks to the respective cores in such a manner that the schedulers 22a, 22b, 22c and 22d provided for the respective cores input a plurality of pieces of information about the unit tasks to the respective execution queues 23a, 23b, 23c and 23d).;
execute a second thread of tasks on at least one of the plurality of data processing nodes of the first type and the data processing node, including couple a corresponding at least one of the plurality of hardware task schedulers and the task scheduler (NA, [0033] lines 1-3, the load balancer 21 divides the task into a plurality of smaller unit tasks (as thread tasks) so that the smaller unit tasks can be performed in parallel by the respective cores (as at least partially overlapping execution of the first thread of tasks); [0034] lines 1-7, The respective cores perform the assigned tasks. In this case, the load balancer 21 may assign tasks to the respective cores in such a manner that the schedulers 22a, 22b, 22c and 22d provided for the respective cores input a plurality of pieces of information about the unit tasks to the respective execution queues 23a, 23b, 23c and 23d).
NA fails to specifically teach a data processing node of a second type, each hardware task scheduler of the plurality of hardware task schedulers having at least one of a producer socket and a consumer socket; a task scheduler configured to be coupled to the data processing node of the second type and having at least one of a producer socket and a consumer socket; a hardware scheduler crossbar configured to be coupled to each of the plurality of hardware task schedulers and the task scheduler via at least one of a pending signal indicating that consumable data is available and a decrement signal indicating that a block of produced data has been consumed.
However, Nalluri teaches a data processing node of a second type (Nalluri, Fig. 1, 10 GPU),
each hardware task scheduler of the plurality of hardware task schedulers having at least one of a producer socket and a consumer socket (Nalluri, Fig. 1, 13 and 17 (as hardware task scheduler, please note: the hardware task schedulers were taught by NA); 17 Blitter command streamer (CS) (Producer), 51 sig/match/fwd (as producer socket); 13 Renderer command streamer (CS) (Consumer, 15 sig/match/fwd (as consumer socket));
a task scheduler configured to be coupled to the data processing node of the second type and having at least one of a producer socket and a consumer socket (Nalluri, Fig. 1, GPU (as processing node of the second type), 11 scheduler controller (as task scheduler), it has 26 and 28; [0023] a semaphore forward signal 28 (as consumer socket) is sent to the SHIM which replies with a semaphore forward acknowledgement (as producer socket). This allows resources to be allocated to the render engine. This allows the scheduler to look if the context ID received from the command scheduler matches an existing context that has retired due to semaphore wait. The command scheduler will then move the retired context to ready to be re-submitted on the next opportunity)); a hardware scheduler crossbar configured to be coupled to each of the plurality of hardware task schedulers and the task scheduler via at least one of a pending signal and a decrement signal (Nalluri, Fig. 1, 12 message channel (as hardware scheduler crossbar), 30 Signal Ack, 32 semaphore signal).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of NA with Nalluri because Nalluri’s teaching of coordinating the signal transfer between producer and consumer would have provided NA’s system with the advantage and capability to allow the system to ensure that the data/value/resource is ready for the consumer to use which improving the system performance and efficiency (see Nalluri, [0002] improving performance and [0004] ensure that the value is ready for the consumer to use).
Both NA and Nalluri fail to specifically teach a pending signal indicating that consumable data is available and a decrement signal indicating that a block of produced data has been consumed.
However, Barner teaches a pending signal indicating that consumable data is available and a decrement signal indicating that a block of produced data has been consumed (Barner, [0040] lines 1-7, The producer may produce data…may increment a counter... the consumer…used to decrement the counter).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of NA and Nalluri with Barner because Barner’s teaching of counter would have provided NA and Nalluri’s system with the advantage and capability to track the data that produced and consumed by the task which result in reducing a latency of data flowing from the producer task to the consumer task during the execution (Barner [0028] see reduce latency of data flowing).
NA, Nalluri and Barner fails to specifically teach when execute first thread of tasks, it is via pending and decrement signals, in a first data processing order, and when execute a second thread of tasks, it is via pending and decrement signals, in a second data processing order.
However, Rupp teaches when execute first thread of tasks, it is via pending and decrement signals, in a first data processing order (Rupp, Fig. 14, ALU column 1402, (0, 1, 2, 3), ALU column 1404 (0, 1) and ALU column 1406 (4, 5) (as plurality of internal hardware task schedulers that are connect with first data processing order, i.e., see input/output connection, as producer socket (output) and consumer socket (input)); Col 13, lines 43-58, FIG. 14 illustrates an example of using silo routing circuits 400 in a reconfigurable logic array system, according to one embodiment of the present invention. In this instance, reconfigurable logic array system 1400 is a reconfigurable data-path (as include first data processing order) system configured to perform a summation of eight numbers in parallel using statically-programmed silo routing circuits 400 (or alternatively silo router 1200) to align one of the input operands to each addition. System 1400 includes columns of reconfigurable computational elements as programmable Arithmetic Logic Units ("ALUs"), which are shown as ALU column 1402, ALU column 1404, and ALU column 1406. Silo routers ("R0") 1401, ("R1") 1403, ("R2") 1405 and ("R3") 1407 are arranged on each side of the array (i.e., system 1400) as well as between pairs of ALU columns and are used to route signals to one of the two operands of each ALU)), and
when execute a second thread of tasks, it is via pending and decrement signals, in a second data processing order (Rupp, Fig. 14, ALU column 1402, (4, 5, 6, 7), ALU column 1404 (4, 5) and ALU column 1406 (4, 5) (as second subset of the plurality of internal hardware task schedulers that are connect with second data processing order, i.e., see input/output connections between them); Col 13, lines 43-58, FIG. 14 illustrates an example of using silo routing circuits 400 in a reconfigurable logic array system, according to one embodiment of the present invention. In this instance, reconfigurable logic array system 1400 is a reconfigurable data-path (as include second data processing order) system configured to perform a summation of eight numbers in parallel using statically-programmed silo routing circuits 400 (or alternatively silo router 1200) to align one of the input operands to each addition. System 1400 includes columns of reconfigurable computational elements as programmable Arithmetic Logic Units ("ALUs"), which are shown as ALU column 1402, ALU column 1404, and ALU column 1406. Silo routers ("R0") 1401, ("R1") 1403, ("R2") 1405 and ("R3") 1407 are arranged on each side of the array (i.e., system 1400) as well as between pairs of ALU columns and are used to route signals to one of the two operands of each ALU)
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of NA, Nalluri and Barner with Rupp because Rupp’s teaching of connecting different input and out signals via the different ALU column components for data processing orders would have provided NA, Nalluri and Barner’s system with the advantage and capability to allow the system to route the different signals correctly in different data processing orders which improving the system performance and efficiency.
NA, Nalluri, Barner and Rupp fail to specifically teach communicate a signal indicating completion of at least one task of the first and second threads of tasks.
However, Verbeke teaches communicate a signal indicating completion of at least one task of the first and second threads of tasks (Verbeke, Fig. 7, 706, receive results of the job from the task dispatcher if the job has been completed; [0057] lines 13-17, results of the job may be received from the task dispatcher if the job has been completed. The contacting, receiving a job repository identification, polling, and receiving results may be performed using a peer-to-peer protocol, such as JXTA ([Examiner noted: receiving the job/jobs completion results (as communicate a signal indicating the completion)]).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of NA, Nalluri. Barner and Rupp with Verbeke because Verbeke’s teaching of initiating and determining the completion of the execution of tasks based on the monitoring would have provided NA, Nalluri. Barner and Rupp’s system with the advantage and capability to manage and run many different applications/tasks/jobs simultaneously which improving system performance and efficiency (see Verbeke, Abstract, provide the ability to manage and run many different applications simultaneously, in an efficient and reliable manner).
As per claim 8, NA, Nalluri, Barner, Rupp and Verbeke teach the invention according to claim 1 above. Nalluri further teaches wherein each of the plurality of hardware task schedulers and the task scheduler includes at least one producer socket and at least one consumer socket (Nalluri, Fig. 1, 13 and 17 (as hardware task scheduler, please note: the hardware task schedulers were taught by NA); 17 Blitter command streamer (CS) (Producer), 51 sig/match/fwd (as producer socket); 13 Renderer command streamer (CS) (Consumer, 15 sig/match/fwd (as consumer socket)).
As per claim 9, NA, Nalluri, Barner, Rupp and Verbeke teach the invention according to claim 1 above. Verbeke further teaches wherein the hardware thread scheduler is configured to communicate a signal indicating completion of each task of the first and second thread of tasks (Verbeke, Fig. 7, 706, receive results of the job from the task dispatcher if the job has been completed; [0057] lines 13-17, results of the job may be received from the task dispatcher if the job has been completed. The contacting, receiving a job repository identification, polling, and receiving results may be performed using a peer-to-peer protocol, such as JXTA ([Examiner noted: receiving the job/jobs completion results (as communicate a signal indicating the completion)]).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over NA, Nalluri, Barner, Rupp and Verbeke, as applied to claim 1 above, and further in view of Bshara et al. (US Pub. 2014/0310439 A1).
As per claim 4, NA, Nalluri, Barner, Rupp and Verbeke teach the invention according to claim 1 above. NA, Nalluri, Barner, Rupp and Verbeke fail to specifically teach wherein the hardware thread scheduler is configured to execute the first thread of tasks during a first time period and execute the second thread of tasks during a second time period that at least partially overlaps the first time period.
However, Bshara teaches wherein the hardware thread scheduler is configured to execute the first thread of tasks during a first time period and execute the second thread of tasks during a second time period that at least partially overlaps the first time period (Bshara, [0089] The multiple operations may be combined into a single operation, a single operation may be distributed in additional operations and operations may be executed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments; please note: the hardware thread scheduler is configured to execute the first thread of tasks and execute the second thread of tasks was taught by NA).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of NA, Nalluri, Barner, Rupp and Verbeke with Bshara because Bshara’s teaching of executing the operations overlapping in time would have provided NA, Nalluri, Barner, Rupp and Verbeke’s system with the advantage and capability to allow the system to operating the different thread of task in the same time in order to improving the processing speed and system efficiency.
Allowable Subject Matter
Claims 2-3, 5-7 and 10-20 are objected but would be allowable if overcomes the rejections under nonstatutory double patenting, 112(a) and 112(b) and rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons of Allowable Subject Matter:
The closest prior arts of record, NA (US Pub. 2014/0372810 A1) teaches a multi-processor system that including different internal schedulers that are coupled to respective processors. And each of respective internal scheduler and processor are scheduled for processing tasks individually.
Nalluri et al. (US Pub. 2014/0160138 A1) teaches a mechanism that having a scheduler crossbar that is coupled to different producer socket and different consumer socket for processing tasks based on the consumption and producer signals.
Barner (US Pub. 2016/0139622 A1) teaches a system that using a pending signal indicating that consumable data is available and a decrement signal indicating that a block of produced data has been consumed (see Barner, [0040] lines 1-7, The producer may produce data…may increment a counter... the consumer…used to decrement the counter).
Rupp (US Patent. 7,237,055 B1) teaches a computing system that reconfiguring different set of ALUs based on the data-path, so different sets/pairs of ALUs are connected with each other based on the data-path.
Verbeke et al. (US Pub. 2004/0019514 A1) teaches a mechanism that when the job is completed, results of the job will be received from the task dispatcher. And communicating a signal indicating the completion using a peer-to-peer protocol, such as JXTA.
The features “configuring internal data processing nodes to execute a first thread of tasks, including coupling hardware task schedulers, via pending and decrement signals communicated with a hardware scheduler crossbar, in a first data processing order, wherein the coupled hardware task schedulers and the internal data processing nodes configured to execute the first thread of tasks are respectively coupled and within a hardware thread scheduler that includes the hardware scheduler crossbar; configuring at least one internal data processing node within the hardware thread scheduler and an external data processing node not within the hardware thread scheduler to execute a second thread of tasks, including coupling at least one hardware task scheduler and a task scheduler, via pending and decrement signals communicated with the hardware scheduler crossbar, in a second data processing order, wherein the at least one internal data processing node is respectively coupled to the at least one hardware task scheduler, and the external data processing node is coupled to the task scheduler; and communicating a signal indicating completion of at least one task of the first and second threads of tasks, wherein each pending signal communicated indicates that consumable data is available and each decrement signal communicated indicates that a block of produced data has been consumed” when taken in the context of the claims as a whole, were not found in the prior art teachings.
Conclusion
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/ZUJIA XU/Primary Examiner, Art Unit 2195
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