DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities:
Paragraph 41- lines 7: “…7777697uu55resonant current…” should be “…resonant current…”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 7-10 and 13-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Norisada et. al. US 20190207527 (Norisada).
PNG
media_image1.png
489
740
media_image1.png
Greyscale
Regarding claim 1, Norisada discloses a power converter (i.e., 3) (Fig. 1), comprising: a cycloconverter (i.e., 11) (Fig. 1) comprising a first pair of AC FETs (i.e., S5P, S5N) (Fig. 1) and a second pair of AC FETs (i.e., S6P, S6N) (Fig. 1); and a controller (i.e., 7, 140) (Fig. 1 and Fig. 20) configured to detect (Norisada discloses the use of several sensors current sensors, for example see paragraph 250) when at least one of a to-be fault (Norisada discloses a returned current generated on the secondary side originated by disconnections causing that could cause the breakdown to the circuit, for example see paragraph 0051) or an ongoing fault occurs and open or close at least one of the first pair of AC FETs (i.e., S5P, S5N) (Fig. 1)or the second pair of AC FETs (i.e., S6P, S6N) (Fig. 1) such that remanent energy stored in a resonant tank of the power converter is depleted to a grid without causing the first pair of AC FETs (i.e., S6P, S6N) (Fig. 1) or the second pair of AC FETs (i.e., S6P, S6N) (Fig. 1) to avalanche.
Regarding claim 2, Norisada, as applied in linking claims, discloses wherein the at least one of the to-be fault or the ongoing fault is a hard-skip which corresponds to when the power converter immediately shuts-off ( for example Norisada discloses that the failure to secure a path for the return current to flow through could cause a breakdown to the circuit, for example see paragraph 0051).
Regarding claim 3, Norisada, as applied in linking claims, discloses the power converter comprising a first pair of DC FETs (i.e., D1, D2) (Fig. 1) and a second pair of DC FETs (i.e., D3, D4) (Fig. 1).
Regarding claim 4, Norisada, as applied in linking claims, discloses the first pair of AC FETs (i.e., S5P, S5N) (Fig. 1) and the second pair of AC FETs (i.e., S6P, S6N) (Fig. 1) are operable in switching states applicable for positive current and negative current of a leakage inductor of the resonant tank, and wherein in the switching states at least three FETs of the first pair of AC FETs (i.e., S5P, S5N) (Fig. 1) and the second pair of AC FETs (i.e., S6P, S6N) (Fig. 1)are on (for example see Fig. 5 and Fig. 21), two FETs of the first pair of DC FETs (i.e., D1, D2) (Fig. 1) and the second pair of DC FETs (i.e., D3, D4) (Fig. 1) are on (for example see Fig. 21), and two FETs of the first pair of DC FETs (i.e., D1, D2) (Fig. 1) and the second pair of DC FETs (i.e., D3, D4) (Fig. 1) are off (for example see Fig. 21).
Regarding claim 7, Norisada discloses a method for controlling switching in a power converter (i.e., 3) (Fig. 1), comprising: a cycloconverter (i.e., 11) (Fig. 1) comprising a first pair of AC FETs (i.e., S5P, S5N) (Fig. 1) and a second pair of AC FETs (i.e., S6P, S6N) (Fig. 1); and a controller (i.e., 7, 140) (Fig. 1 and Fig. 20) configured to detect (Norisada discloses the use of several sensors current sensors, for example see paragraph 250) when at least one of a to-be fault (Norisada discloses a returned current generated on the secondary side originated by disconnections causing that could cause the breakdown to the circuit, for example see paragraph 0051) or an ongoing fault occurs and open or close at least one of the first pair of AC FETs (i.e., S5P, S5N) (Fig. 1)or the second pair of AC FETs (i.e., S6P, S6N) (Fig. 1) such that remanent energy stored in a resonant tank of the power converter is depleted to a grid without causing the first pair of AC FETs (i.e., S6P, S6N) (Fig. 1) or the second pair of AC FETs (i.e., S6P, S6N) (Fig. 1) to avalanche.
Regarding claim 8, Norisada, as applied in linking claims, discloses wherein the at least one of the to-be fault or the ongoing fault is a hard-skip which corresponds to when the power converter immediately shuts-off ( for example Norisada discloses that the failure to secure a path for the return current to flow through could cause a breakdown to the circuit, for example see paragraph 0051).
Regarding claim 9, Norisada, as applied in linking claims, discloses the power converter comprising a first pair of DC FETs (i.e., D1, D2) (Fig. 1) and a second pair of DC FETs (i.e., D3, D4) (Fig. 1).
Regarding claim 10, Norisada, as applied in linking claims, discloses the first pair of AC FETs (i.e., S5P, S5N) (Fig. 1) and the second pair of AC FETs (i.e., S6P, S6N) (Fig. 1) are operable in switching states applicable for positive current and negative current of a leakage inductor of the resonant tank, and wherein in the switching states at least three FETs of the first pair of AC FETs (i.e., S5P, S5N) (Fig. 1) and the second pair of AC FETs (i.e., S6P, S6N) (Fig. 1)are on (for example see Fig. 5 and Fig. 21), two FETs of the first pair of DC FETs (i.e., D1, D2) (Fig. 1) and the second pair of DC FETs (i.e., D3, D4) (Fig. 1) are on (for example see Fig. 21), and two FETs of the first pair of DC FETs (i.e., D1, D2) (Fig. 1) and the second pair of DC FETs (i.e., D3, D4) (Fig. 1) are off (for example see Fig. 21).
Regarding claim 13, Norisada discloses a non-transitory computer readable storage medium having instructions stored thereon that when executed by a process performs (Norisada disclose the use a microcomputer including a central processing unit (CPU), a field-programmable gate array (FPGA), or an application specific integrated circuit (ASIC), for example see paragraph 0197) a method for controlling switching in a power converter (i.e., 3) (Fig. 1), comprising: a cycloconverter (i.e., 11) (Fig. 1) comprising a first pair of AC FETs (i.e., S5P, S5N) (Fig. 1) and a second pair of AC FETs (i.e., S6P, S6N) (Fig. 1); and a controller (i.e., 7, 140) (Fig. 1 and Fig. 20) configured to detect (Norisada discloses the use of several sensors current sensors, for example see paragraph 250) when at least one of a to-be fault (Norisada discloses a returned current generated on the secondary side originated by disconnections causing that could cause the breakdown to the circuit, for example see paragraph 0051) or an ongoing fault occurs and open or close at least one of the first pair of AC FETs (i.e., S5P, S5N) (Fig. 1)or the second pair of AC FETs (i.e., S6P, S6N) (Fig. 1) such that remanent energy stored in a resonant tank of the power converter is depleted to a grid without causing the first pair of AC FETs (i.e., S6P, S6N) (Fig. 1) or the second pair of AC FETs (i.e., S6P, S6N) (Fig. 1) to avalanche.
Regarding claim 14, Norisada, as applied in linking claims, discloses wherein the at least one of the to-be fault or the ongoing fault is a hard-skip which corresponds to when the power converter immediately shuts-off ( for example Norisada discloses that the failure to secure a path for the return current to flow through could cause a breakdown to the circuit, for example see paragraph 0051).
Regarding claim 15, Norisada, as applied in linking claims, discloses the power converter comprising a first pair of DC FETs (i.e., D1, D2) (Fig. 1) and a second pair of DC FETs (i.e., D3, D4) (Fig. 1).
Regarding claim 16, Norisada, as applied in linking claims, discloses the first pair of AC FETs (i.e., S5P, S5N) (Fig. 1) and the second pair of AC FETs (i.e., S6P, S6N) (Fig. 1) are operable in switching states applicable for positive current and negative current of a leakage inductor of the resonant tank, and wherein in the switching states at least three FETs of the first pair of AC FETs (i.e., S5P, S5N) (Fig. 1) and the second pair of AC FETs (i.e., S6P, S6N) (Fig. 1)are on (for example see Fig. 5 and Fig. 21), two FETs of the first pair of DC FETs (i.e., D1, D2) (Fig. 1) and the second pair of DC FETs (i.e., D3, D4) (Fig. 1) are on (for example see Fig. 21), and two FETs of the first pair of DC FETs (i.e., D1, D2) (Fig. 1) and the second pair of DC FETs (i.e., D3, D4) (Fig. 1) are off (for example see Fig. 21).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5, 11 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Norisada et. al. US Publication 20190207527 (Norisada) in view of Chen et. al. CN 114900027 (Chen)..
Regarding claim 5, 11 and 17, Norisada, as applied in respectively linking claims, fail to disclose the controller configured to switch off the power converter at a zero crossing of AC voltage subsequent to when at least one of the to-be fault or the ongoing fault is detected.
Chen in the same field of endeavor discloses the controller configured to switch off the power converter at a zero crossing of AC voltage subsequent to when at least one of the to-be fault or the ongoing fault is detected in order to protect the secondary side switch tube.
Therefore, It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have optionally provide the controller configured to switch off the power converter at a zero crossing of AC voltage subsequent to when at least one of the to-be fault or the ongoing fault is detected in Norisada, as taught by Chen, in order to protect the secondary side switch tube.
Claim 6, 12 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Norisada et. al. US Publication 20190207527 (Norisada) in view of Li et. al. US Publication 20190067932 (Li).
Regarding claim 6, 12 and 18, Norisada, as applied in respectively linking claims, discloses the use of any type of MOSFET as transistor but fail to disclose the MOSFETs comprising at least one of Si, SiC, or GaN.
Li in the same field of endeavor discloses the use of MOSFETs comprising at least one of Si, SiC, or GaN as an alternative for MOSFETs transistors.
Therefore, It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have optionally provide a MOSFET comprising at least one of Si, SiC, or GaN as transistor in Norisada, as taught by Li, in order to select MOSFETs comprising at least one of Si, SiC, or GaN as an alternative for MOSFETs transistors
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YAHVEH COMAS TORRES whose telephone number is (571)272-4011. The examiner can normally be reached Mondays - Thursday 830am.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V Tran can be reached on (571)270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/YAHVEH COMAS TORRES/Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838