DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Claims 1-2, 4-8, 10-14 and 16-18 are pending.
Claims 3, 9 and 15 were cancelled.
Response to Arguments
Applicant’s arguments, see remarks, filed 6/4/2026, with respect to the objection to specifications have been fully considered and are persuasive. The objection to the specifications has been withdrawn.
Applicant’s arguments with respect to claims 1-2, 4-8, 10-14 and 16-18 have been considered but are moot because a new ground of rejection is necessitated due to Applicant's amendment.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 7-8 and 13-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ransom US Patent 8,410,635 (Ransom).
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Regarding claim 1, Ransom discloses a power converter (i.e., 100) (Fig. 1), comprising: a cycloconverter (Fig. 1) comprising a first pair of AC FETs (i.e., S1, S2) (Fig. 1) and a second pair of AC FETs (i.e., S3, S6N) (Fig. 1) and a first pair of DC FETs (i.e., S9, S10) (Fig. 1) and a second pair of DC FETs (i.e., S11, S12) (Fig. 1);
and a controller (i.e., 116) (Fig. 1) configured to detect when at least one of a to-be fault or an ongoing fault occurs (see Fig. 2, element 202) and shut down the first pair of DC FETs (i.e., S9, S10) (Fig. 1) and the second pair of DC FETs (i.e., S11, S12) (Fig. 1) while maintaining the first pair of AC FETs (i.e., S1, S2) (Fig. 1) and the second pair of AC FET (i.e., S3, S4) (Fig. 1) in a prior switching state such that remanent energy stored in a resonant tank of the power converter is depleted to a grid without causing the first pair of AC FETs (i.e., S1, S2) (Fig. 1) or the second pair of AC FETs (i.e., S3, S4) (Fig. 1) to avalanche.
Regarding claim 2, Ransom, as applied in linking claims, discloses wherein the at least one of the to-be fault or the ongoing fault is a hard-skip which corresponds to when the power converter immediately shuts-off ( Ransom discloses the control module is configured to operate the first conversion module to deactivate the first conversion module when a magnitude of a current through the inductive element is less than a threshold value, for example see column 2 line 1-3).
Regarding claim 7, Ransom discloses a method for controlling switching in a power converter (i.e., 100) (Fig. 1), comprising detecting when at least one of a to-be fault or an ongoing fault occurs (i.e., 202) (see Fig. 2);
and shutting down the first pair of DC FETs (i.e., S9, S10) (Fig. 1) and the second pair of DC FETs (i.e., S11, S12) (Fig. 1) while maintaining the first pair of AC FETs (i.e., S1, S2) (Fig. 1) and the second pair of AC FET (i.e., S3, S4) (Fig. 1) in a prior switching state such that remanent energy stored in a resonant tank of the power converter is depleted to a grid without causing the first pair of AC FETs (i.e., S1, S2) (Fig. 1) or the second pair of AC FETs (i.e., S3, S4) (Fig. 1) to avalanche.
Regarding claim 8, Ransom, as applied in linking claims, discloses wherein the at least one of the to-be fault or the ongoing fault is a hard-skip which corresponds to when the power converter immediately shuts-off ( Ransom discloses the control module is configured to operate the first conversion module to deactivate the first conversion module when a magnitude of a current through the inductive element is less than a threshold value, for example see column 2 line 1-3).
Regarding claim 13, Ransom discloses a non-transitory computer readable storage medium having instructions stored thereon that when executed by a process performs (for example see column 13, lines 15-30) a method for controlling switching in a power converter (i.e., 100) (Fig. 1), comprising:
detecting when at least one of a to-be fault or an ongoing fault occurs (i.e., 202) (see Fig. 2);
and shutting down the first pair of DC FETs (i.e., S9, S10) (Fig. 1) and the second pair of DC FETs (i.e., S11, S12) (Fig. 1) while maintaining the first pair of AC FETs (i.e., S1, S2) (Fig. 1) and the second pair of AC FET (i.e., S3, S4) (Fig. 1) in a prior switching state such that remanent energy stored in a resonant tank of the power converter is depleted to a grid without causing the first pair of AC FETs (i.e., S1, S2) (Fig. 1) or the second pair of AC FETs (i.e., S3, S4) (Fig. 1) to avalanche.
Regarding claim 14, Ransom, as applied in linking claims, discloses wherein the at least one of the to-be fault or the ongoing fault is a hard-skip which corresponds to when the power converter immediately shuts-off ( Ransom discloses the control module is configured to operate the first conversion module to deactivate the first conversion module when a magnitude of a current through the inductive element is less than a threshold value, for example see column 2 line 1-3).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4, 7-8, 10, 13-14 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Norisada et. al. US 20190207527 (Norisada) in view of Ransom US Patent 8410635 (Ransom).
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Regarding claim 1, Norisada discloses a power converter (i.e., 3) (Fig. 1), comprising: a cycloconverter (i.e., 11) (Fig. 1) comprising a first pair of AC FETs (i.e., S5P, S5N) (Fig. 1) and a second pair of AC FETs (i.e., S6P, S6N) (Fig. 1) and a first pair of DC FETs (i.e., D1, D2) (Fig. 1) and a second pair of DC FETs (i.e., D3, D4) (Fig. 1);
and a controller (i.e., 7, 140) (Fig. 1 and Fig. 20) configured to detect (Norisada discloses the use of several sensors current sensors, for example see paragraph 250) when at least one of a to-be fault (Norisada discloses a returned current generated on the secondary side originated by disconnections causing that could cause the breakdown to the circuit, for example see paragraph 0051) or an ongoing fault occurs and shut down several switches such that remanent energy stored in a resonant tank of the power converter is depleted to a grid without causing the first pair of AC FETs (i.e., S6P, S6N) (Fig. 1) or the second pair of AC FETs (i.e., S6P, S6N) (Fig. 1) to avalanche.
Norisada fail to disclose a controller shutting down the first pair of DC FETs and the second pair of DC FETs while maintaining the first pair of AC FETs and the second pair of AC FET in a prior switching state such that remanent energy stored in a resonant tank of the power converter is depleted to a grid without causing the first pair of AC FETs or the second pair of AC FETs to avalanche.
Ransom, in the same field of endeavor, discloses a controller which shut down the first pair of DC FETs (i.e., S9, S10) (Fig. 1) and the second pair of DC FETs (i.e., S11, S12) (Fig. 1) while maintaining the first pair of AC FETs (i.e., S1, S2) (Fig. 1) and the second pair of AC FET (i.e., S3, S4) (Fig. 1) in a prior switching state such that remanent energy stored in a resonant tank of the power converter is depleted to a grid without causing the first pair of AC FETs (i.e., S1, S2) (Fig. 1) or the second pair of AC FETs (i.e., S3, S4) (Fig. 1) to avalanche in order to avoid abruptly stopping the current flowing through an inductor which may result in a transient voltage spike that exceeds the breakdown voltage of a semiconductor device.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have optionally provide a controller that shut down the first pair of DC FETs and the second pair of DC FETs while maintaining the first pair of AC FETs and the second pair of AC FET in a prior switching state such that remanent energy stored in a resonant tank of the power converter is depleted to a grid without causing the first pair of AC FETs or the second pair of AC FETs to avalanche in Norisada, as taught by Ransom, in order in order to avoid abruptly stopping the current flowing through an inductor which may result in a transient voltage spike that exceeds the breakdown voltage of a semiconductor device.
Regarding claim 2, Norisada in view of Ransom, as applied in linking claims, discloses wherein the at least one of the to-be fault or the ongoing fault is a hard-skip which corresponds to when the power converter immediately shuts-off ( for example Norisada discloses that the failure to secure a path for the return current to flow through could cause a breakdown to the circuit, for example see paragraph 0051).
Regarding claim 4, Norisada in view of Ransom, as applied in linking claims, discloses the first pair of AC FETs (i.e., S5P, S5N) (Fig. 1) and the second pair of AC FETs (i.e., S6P, S6N) (Fig. 1) are operable in switching states applicable for positive current and negative current of a leakage inductor of the resonant tank, and wherein in the switching states at least three FETs of the first pair of AC FETs (i.e., S5P, S5N) (Fig. 1) and the second pair of AC FETs (i.e., S6P, S6N) (Fig. 1)are on (for example see Fig. 5 and Fig. 21), two FETs of the first pair of DC FETs (i.e., D1, D2) (Fig. 1) and the second pair of DC FETs (i.e., D3, D4) (Fig. 1) are on (for example see Fig. 21), and two FETs of the first pair of DC FETs (i.e., D1, D2) (Fig. 1) and the second pair of DC FETs (i.e., D3, D4) (Fig. 1) are off (for example see Fig. 21).
Regarding claim 7, Norisada, discloses a method for controlling switching in a power converter (i.e., 3) (Fig. 1), comprising: detecting (Norisada discloses the use of several sensors current sensors, for example see paragraph 250) at least one of a to-be fault (Norisada discloses a returned current generated on the secondary side originated by disconnections causing that could cause the breakdown to the circuit, for example see paragraph 0051) or an ongoing fault occurs and shutting down several switches such that remanent energy stored in a resonant tank of the power converter is depleted to a grid without causing the first pair of AC FETs (i.e., S6P, S6N) (Fig. 1) or the second pair of AC FETs (i.e., S6P, S6N) (Fig. 1) to avalanche.
Norisada fail to disclose a controller shutting down the first pair of DC FETs and the second pair of DC FETs while maintaining the first pair of AC FETs and the second pair of AC FET in a prior switching state such that remanent energy stored in a resonant tank of the power converter is depleted to a grid without causing the first pair of AC FETs or the second pair of AC FETs to avalanche.
Ransom, in the same field of endeavor, discloses a controller which shut down the first pair of DC FETs (i.e., S9, S10) (Fig. 1) and the second pair of DC FETs (i.e., S11, S12) (Fig. 1) while maintaining the first pair of AC FETs (i.e., S1, S2) (Fig. 1) and the second pair of AC FET (i.e., S3, S4) (Fig. 1) in a prior switching state such that remanent energy stored in a resonant tank of the power converter is depleted to a grid without causing the first pair of AC FETs (i.e., S1, S2) (Fig. 1) or the second pair of AC FETs (i.e., S3, S4) (Fig. 1) to avalanche in order to avoid abruptly stopping the current flowing through an inductor which may result in a transient voltage spike that exceeds the breakdown voltage of a semiconductor device.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have optionally provide a controller that shut down the first pair of DC FETs and the second pair of DC FETs while maintaining the first pair of AC FETs and the second pair of AC FET in a prior switching state such that remanent energy stored in a resonant tank of the power converter is depleted to a grid without causing the first pair of AC FETs or the second pair of AC FETs to avalanche in Norisada, as taught by Ransom, in order in order to avoid abruptly stopping the current flowing through an inductor which may result in a transient voltage spike that exceeds the breakdown voltage of a semiconductor device.
Regarding claim 8, Norisada in view of Ransom, as applied in linking claims, discloses wherein the at least one of the to-be fault or the ongoing fault is a hard-skip which corresponds to when the power converter immediately shuts-off ( for example Norisada discloses that the failure to secure a path for the return current to flow through could cause a breakdown to the circuit, for example see paragraph 0051).
Regarding claim 10, Norisada in view of Ransom, as applied in linking claims, discloses the first pair of AC FETs (i.e., S5P, S5N) (Fig. 1) and the second pair of AC FETs (i.e., S6P, S6N) (Fig. 1) are operable in switching states applicable for positive current and negative current of a leakage inductor of the resonant tank, and wherein in the switching states at least three FETs of the first pair of AC FETs (i.e., S5P, S5N) (Fig. 1) and the second pair of AC FETs (i.e., S6P, S6N) (Fig. 1)are on (for example see Fig. 5 and Fig. 21), two FETs of the first pair of DC FETs (i.e., D1, D2) (Fig. 1) and the second pair of DC FETs (i.e., D3, D4) (Fig. 1) are on (for example see Fig. 21), and two FETs of the first pair of DC FETs (i.e., D1, D2) (Fig. 1) and the second pair of DC FETs (i.e., D3, D4) (Fig. 1) are off (for example see Fig. 21).
Regarding claim 13, Norisada discloses a non-transitory computer readable storage medium having instructions stored thereon that when executed by a process performs (Norisada disclose the use a microcomputer including a central processing unit (CPU), a field-programmable gate array (FPGA), or an application specific integrated circuit (ASIC), for example see paragraph 0197) a method for controlling switching in a power converter (i.e., 3) (Fig. 1), comprising: detecting (Norisada discloses the use of several sensors current sensors, for example see paragraph 250) at least one of a to-be fault (Norisada discloses a returned current generated on the secondary side originated by disconnections causing that could cause the breakdown to the circuit, for example see paragraph 0051) or an ongoing fault occurs and shutting down several switches such that remanent energy stored in a resonant tank of the power converter is depleted to a grid without causing the first pair of AC FETs (i.e., S6P, S6N) (Fig. 1) or the second pair of AC FETs (i.e., S6P, S6N) (Fig. 1) to avalanche.
Norisada fail to disclose a controller shutting down the first pair of DC FETs and the second pair of DC FETs while maintaining the first pair of AC FETs and the second pair of AC FET in a prior switching state such that remanent energy stored in a resonant tank of the power converter is depleted to a grid without causing the first pair of AC FETs or the second pair of AC FETs to avalanche.
Ransom, in the same field of endeavor, discloses a controller which shut down the first pair of DC FETs (i.e., S9, S10) (Fig. 1) and the second pair of DC FETs (i.e., S11, S12) (Fig. 1) while maintaining the first pair of AC FETs (i.e., S1, S2) (Fig. 1) and the second pair of AC FET (i.e., S3, S4) (Fig. 1) in a prior switching state such that remanent energy stored in a resonant tank of the power converter is depleted to a grid without causing the first pair of AC FETs (i.e., S1, S2) (Fig. 1) or the second pair of AC FETs (i.e., S3, S4) (Fig. 1) to avalanche in order to avoid abruptly stopping the current flowing through an inductor which may result in a transient voltage spike that exceeds the breakdown voltage of a semiconductor device.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have optionally provide a controller that shut down the first pair of DC FETs and the second pair of DC FETs while maintaining the first pair of AC FETs and the second pair of AC FET in a prior switching state such that remanent energy stored in a resonant tank of the power converter is depleted to a grid without causing the first pair of AC FETs or the second pair of AC FETs to avalanche in Norisada, as taught by Ransom, in order in order to avoid abruptly stopping the current flowing through an inductor which may result in a transient voltage spike that exceeds the breakdown voltage of a semiconductor device.
Regarding claim 14, Norisada in view of Ransom, as applied in linking claims, discloses wherein the at least one of the to-be fault or the ongoing fault is a hard-skip which corresponds to when the power converter immediately shuts-off ( for example Norisada discloses that the failure to secure a path for the return current to flow through could cause a breakdown to the circuit, for example see paragraph 0051).
Regarding claim 16, Norisada in view of Ransom, as applied in linking claims, discloses the first pair of AC FETs (i.e., S5P, S5N) (Fig. 1) and the second pair of AC FETs (i.e., S6P, S6N) (Fig. 1) are operable in switching states applicable for positive current and negative current of a leakage inductor of the resonant tank, and wherein in the switching states at least three FETs of the first pair of AC FETs (i.e., S5P, S5N) (Fig. 1) and the second pair of AC FETs (i.e., S6P, S6N) (Fig. 1)are on (for example see Fig. 5 and Fig. 21), two FETs of the first pair of DC FETs (i.e., D1, D2) (Fig. 1) and the second pair of DC FETs (i.e., D3, D4) (Fig. 1) are on (for example see Fig. 21), and two FETs of the first pair of DC FETs (i.e., D1, D2) (Fig. 1) and the second pair of DC FETs (i.e., D3, D4) (Fig. 1) are off (for example see Fig. 21).
Claim 5, 11 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Norisada et. al. US Publication 20190207527 (Norisada) ) in view of Ransom US Patent 8410635 (Ransom), and in further in view of Chen et. al. CN 114900027 (Chen)..
Regarding claim 5, 11 and 17, Norisada in view of Ransom, as applied in respectively linking claims, fail to disclose the controller configured to switch off the power converter at a zero crossing of AC voltage subsequent to when at least one of the to-be fault or the ongoing fault is detected.
Chen in the same field of endeavor discloses the controller configured to switch off the power converter at a zero crossing of AC voltage subsequent to when at least one of the to-be fault or the ongoing fault is detected in order to protect the secondary side switch tube.
Therefore, It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have optionally provide the controller configured to switch off the power converter at a zero crossing of AC voltage subsequent to when at least one of the to-be fault or the ongoing fault is detected in Norisada in view of Ransom, as taught by Chen, in order to protect the secondary side switch tube.
Claim 6, 12 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Norisada et. al. US Publication 20190207527 (Norisada) in view of Ransom US Patent 8410635 (Ransom), and in further in view of Li et. al. US Publication 20190067932 (Li).
Regarding claim 6, 12 and 18, Norisada in view of Ransom, as applied in respectively linking claims, discloses the use of any type of MOSFET as transistor but fail to disclose the MOSFETs comprising at least one of Si, SiC, or GaN.
Li in the same field of endeavor discloses the use of MOSFETs comprising at least one of Si, SiC, or GaN as an alternative for MOSFETs transistors.
Therefore, It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have optionally provide a MOSFET comprising at least one of Si, SiC, or GaN as transistor in Norisada in view of Ransom, as taught by Li, in order to select MOSFETs comprising at least one of Si, SiC, or GaN as an alternative for MOSFETs transistors.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/YAHVEH COMAS TORRES/Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
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