Reply Under 37 CFR 1.111
The Amendments and Applicant Arguments submitted on 04/14/2026 have been received and its contents have been carefully considered.
Claims 1-18 are pending in this application. Claims 1, 7 and 13, as currently amended, are presented for examination. Claims 2-6, 8-12 and 14-18, as previously submitted, are now presented again for examination.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 7-11 and 13-17 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Intel Corporation, Intel Server System M50CYP1UR Technical Product Specification, Rev. 1.43, August 2023 (hereinafter “Intel”).
In re Claim 1, Intel discloses a peripheral mounting system for use with an information handling system (Figure 1, p. 13), comprising: a first slot (OCP Adapter Area, Figure 3, p. 19), the first slot being configured to mount a first peripheral component (Figure 56, p. 74) and a first peripheral connector component (Figure 54, p. 73), the first peripheral component and the first peripheral connector component corresponding a first component standard (Open Compute Project OCP 3.0, Section 7.4, pp. 72-74); and, a second slot (Riser #1, Riser #2, Interposer Riser, Figure 3, p. 19), the second slot being configured to mount a second peripheral component (Section 7.2-7.3.4, pp. 67-72) and a second peripheral connector component (Figures 49-52, pp. 69-71, depending on which slot the component is in the configuration changes but various connectors disclosed and could be a “second peripheral connector component”), the second peripheral component and the second peripheral connector component corresponding to a second component standard (PCIe Standard, Section 7.2-7.3.4, pp. 67-72), the first component standard and the second component standard being different component specifications (OCP different from PCIe).
Furthermore, Intel also discloses wherein the peripheral mounting system is configured to mount the first peripheral component (OCP) and the second peripheral component (one of the PCIe components) within a single device bay (See Figure 41 below, “back bay”) of the information handling system.
PNG
media_image1.png
286
847
media_image1.png
Greyscale
In re Claims 2, 8 and 14, Intel discloses wherein: the peripheral mounting system is configured to be mounted within an information handling system chassis (Figure 2, p. 19) conforming to a 1U information handling system form factor (Section 1, p. 13, “1U rack mount server form factor”).
In re Claims 3, 9 and 15, Intel discloses wherein: the first peripheral connector component includes a first peripheral component connector (Figures 49-52, Slot1_PCIe_x16 connectors or edge connectors with gold fingers shown but not labeled); the second peripheral connector component includes a second peripheral component connector (not shown explicitly in Figures but described as connected with OCPv3 Adapter Connector as shown in Figure 8, p. 22); and, the first peripheral component connector and the second peripheral component connector are mounted in the peripheral mounting system substantially perpendicularly to each other (Figure 8, p. 22, Riser Slot #1, #2, #3 or Interposer Slot connections all being perpendicular normal to Server Board while OCPv3 Adapter Connector is facing parallel to Server Board and therefore perpendicular to PCIe edge connectors).
In re Claims 4, 10 and 16, Intel discloses wherein: the first slot (OCP Adapter Area, Figure 3, p. 19), includes a latching mechanism (Figures 55, 56 pp. 73-74, pull tab A and thumb screw B), the latching mechanism being configured to mount at least one of the first peripheral component and the first peripheral connector component to the peripheral mounting system.
In re Claims 5, 11 and 17, Intel discloses wherein: the first component standard comprises an open compute project (OCP) component standard (Section 7.4, pp. 72-73); and, the second component standard comprises a Peripheral Component Interconnect express (PCIe) component standard (Chapter 7, p. 64).
6. The peripheral mounting system of claim 5, wherein: the first connector component comprises a floating OCP (FLOP) connector component.
In re Claim 7, Intel discloses a peripheral tray system comprising: a chassis (Figure 1, p. 13); and, a peripheral mounting system mounted to the chassis (Figure 2, p. 19), the peripheral mounting system comprising a first slot (OCP Adapter Area, Figure 3, p. 19), the first slot being configured to mount a first peripheral component (Figure 56, p. 74) and a first peripheral connector component (Figure 54, p. 73), the first peripheral component and the first peripheral connector component corresponding a first component standard (Open Compute Project OCP 3.0, Section 7.4, pp. 72-74); and, a second slot (Riser #1, Riser #2, Interposer Riser, Figure 3, p. 19), the second slot being configured to mount a second peripheral component (Section 7.2-7.3.4, pp. 67-72) and a second peripheral connector component (Figures 49-52, pp. 69-71, depending on which slot the component is in the configuration changes but various connectors disclosed and could be a “second peripheral connector component”), the second peripheral component and the second peripheral connector component corresponding to a second component standard (PCIe Standard, Section 7.2-7.3.4, pp. 67-72), the first component standard and the second component standard being different component specifications (OCP different from PCIe).
Furthermore, Intel also discloses wherein the peripheral mounting system is configured to mount the first peripheral component (OCP) and the second peripheral component (one of the PCIe components) within a single device bay (See Figure 41 above, “back bay”) of the information handling system.
In re Claim 13, Intel discloses a system comprising: a chassis (Figure 1, p. 13); a processor (CPU 0, CPU 1) contained within the chassis ; a data bus coupled to the processor (Figures 7 and 8, data bus lanes between PCIe components and CPUs); and, a peripheral mounting system comprising a first slot (OCP Adapter Area, Figure 3, p. 19), the first slot being configured to mount a first peripheral component (Figure 56, p. 74) and a first peripheral connector component (Figure 54, p. 73), the first peripheral component and the first peripheral connector component corresponding a first component standard (Open Compute Project OCP 3.0, Section 7.4, pp. 72-74); and, a second slot (Riser #1, Riser #2, Interposer Riser, Figure 3, p. 19), the second slot being configured to mount a second peripheral component (Section 7.2-7.3.4, pp. 67-72) and a second peripheral connector component (Figures 49-52, pp. 69-71, depending on which slot the component is in the configuration changes but various connectors disclosed and could be a “second peripheral connector component”), the second peripheral component and the second peripheral connector component corresponding to a second component standard (PCIe Standard, Section 7.2-7.3.4, pp. 67-72), the first component standard and the second component standard being different component specifications (OCP different from PCIe).
Furthermore, Intel also discloses wherein the peripheral mounting system is configured to mount the first peripheral component (OCP) and the second peripheral component (one of the PCIe components) within a single device bay (See Figure 41 above, “back bay”) of the information handling system.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6, 12 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Intel Corporation, Intel Server System M50CYP1UR Technical Product Specification, Rev. 1.43, August 2023 (hereinafter “Intel”) in view of Schmitt (US Patent 5,652,695).
In re Claims 6, 12 and 18, Intel discloses the limitations as noted above but does not explicitly disclose a floating connector. However, providing such was not new in the art. For example, Schmitt discloses a first connector component 200 comprising a floating connector (See Figures 7A-7B, 9 and associated description). It would have been obvious to a person having ordinary skill in the art of modular electronics at a time before applicant’s filing date to have provided a floating connector like that disclosed in Schmitt in place of the connector as otherwise disclosed in Intel to improve the reliability of the electrical connection and to avoid damage in the event the connection is initially misaligned being a blind connection. Schmitt, col. 6 ll. 45-67; col. 7 ll. 1-10.
Response to Arguments
Applicant's arguments filed 04/14/2026 have been fully considered but they are not persuasive. Specifically, applicant argues that the newly added limitations to Claims 1, 7 and 13 are not disclosed in Intel. Applicant’s Arguments, p. 7. The office respectfully disagrees. The claims must be given their "broadest reasonable interpretation." See MPEP §2111. Applicant’s specification does not require the claimed “single device bay” to have any particular enclosure, cage structure, removability, orientation or arrangement beyond being a “bay area” of the information handling system configured to accommodate peripheral components. For example, Applicant’s Specification describes a riser cage, also referred to as a device bay, that can accommodate a plurality of card components, including OCP and PCIe components. Intel likewise discloses a server system having a back bay (Figure 41 as shown above) add-in card area that accommodates both PCIe add-in components and OCP add-in components. Thus, under a broadest reasonable interpretation Intel’s disclosed back bay is a “single device bay” of the information handling system configured to mount the first peripheral component (i.e. the OCP) and the second peripheral component (i.e. the PCIe) as claimed.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Adrian S Wilson whose telephone number is (571)270-3907. The examiner can normally be reached Monday through Friday, 9am to 5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Allen L Parker can be reached at 303-297-4722. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ADRIAN S WILSON/Primary Examiner, Art Unit 2841
Prosecution Insights